A

+5VPCU +3VPCU
SYS_HWPG(PCU)

From AC,Battery VIN

SUSON

MAINON

+5V +3V +2.5V +1.8V +1.5V +1.05V

HWPG_1.5V HWPG_1.05V

VRON
+VCC_CORE

From EC

From PWM

From EC
From PWM

STPCPU#

STPCLK#

CPUSLP#

DPSLP#

DPRSTP#

DPRSLPVR

RSTWARN

PLTRST#
CPU_PWRGD

CPURST#

From SCH

From SCH

From SCH

From SCH

From SCH

From SCH

From EC

From EC
From SCH

From SCH

ECPWROK

From EC

HWPG

CPU_COREPG

SLPRDY#(H Level)

From SCH

VRON

20us
100us

>5ms

>5ms

SLPMODE(L Level)

From SCH

MAINON

RSTRDY#(H Level)

From SCH

HWPG_1.8V (SUS)

+3VSUS +1.8VSUS +SMDDR_VREF +SMDDR_VTERM

>5ms

SUSON

From PWM

RSMRST#

From EC

+5V_S5

+3V_S5

NBSWON#
S5_ON

ZA3 Power On Sequence

From EC

From EC

From Power Button

From PWM

2ms

FAN Module

MOS CKT

Power Plane

+3VPCU

Battery

PWM FAN

Stuff

+3V

Date:

Size

Sunday, March 08, 2009

Sheet

PROJECT : ZA3
of

34

Rev
1A

Quanta Computer Inc.

Reserve

Power Sequence/ BOM Rule

Document Number

+3VPCU

CPU thermal Sensor EC EEPROM

Reserve

+3VSUS

Mini Card (3G)

Jmicron JMH330

+3V

Marvell 88SE8040

Description

Mini Card (WLAN/WMAX)

EC SMBUS Table

EC775 SDA2 / SCL2 (+3VPCU)

MOS CKT

+3V

RAM

Reserve Reserve

+3V

CLK GEN

EC775 SDA1 / SCL1 (+3VPCU)

Power Plane

FAN_PWM@

3G@

330@

8040@

Name

Poulsbo SCH SMBUS Table

(SMB_DATA) / (SMB_CLK) (+3V)

3G Module

PATA TO SATA BRIDGE

PATA TO SATA BRIDGE

Function

Items

BOM naming rule