68hc11 Instruction Set

68HC11 Instruction Set
1 of 11
http://www.ele.uri.edu/Courses/ele205/6811-Instructions/

Modified and corrected from Tom Dickens. Please notify me of any errors!
Mnemonic
Operation
ABA
Add
Accumulators
ABY
Add B to Y
ABX
ADCA
ADCB
ADDA
ADDB
ADDD
ANDA
ANDB
Instruction
Addressing
Bytes Cycles
Mode
Prebyte Opcode Operand
INH
Add B to X
INH
Add with
Carry to A
IMM
Add with
Carry to B
Add Memory
to A
Add Memory
to B
Add 16-Bit to
D
AND A with
Memory
AND B with
Memory
3A
89
ii
INH
18
DIR
IND, X
EXT
1B
3A
99
dd
2
2
4
3
B9
hh ll
IND, Y
18
A9
ff
DIR
IND, X
E9
8B
IMM
EXT
C9
IND, Y
18
DIR
IND, X
IMM
EXT
A9
ff
ii
F9
hh ll
E9
ff
D9
9B
dd
ff
ii
dd
BB
hh ll
IND, Y
18
AB
ff
DIR
DB
IND, X
EB
C3
jj kk
F3
hh ll
E3
ff
IMM
EXT
AB
CB
FB
hh ll
EB
ff
DIR
IND, X
E3
84
IND, Y
18
DIR
IND, X
IMM
EXT
18
EXT
ii
IND, Y
IMM
ff
D3
94
dd
ff
dd
ff
2
2
4
5
ii
dd
B4
hh ll
IND, Y
18
A4
ff
DIR
IND, X
IMM
EXT
A4
C4
F4
D4
E4
ff
ii
hh ll
dd
ff
Condition Codes
4
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ASL
ASLA
ASLB
ASLD
ASR
ASRA
ASRB
BCC
BCLR
BCS
BEQ
BGE
BGT
BHI
BHS
BITA
BITB
Arithmetic
Shift Left
Arithmetic
Shift Left A
Arithmetic
Shift Left B
Arithmetic
Shift Left D
Arithmetic
Shift Right
Arithmetic
Shift Right A
Arithmetic
Shift Right B
Branch if
Carry Clear
Clear Bit(s)
Branch if
Carry Set
Branch if =
Zero
Branch if
Zero
Branch if >
Zero
Branch if
Higher
Branch if
Higher or
Same
Bit(s) Test A
with Memory
Bit(s) Test B
with Memory
IND, Y
18
E4
IND, X
68
EXT
ff
78
hh ll
ff
ff
IND, Y
18
68
48
INH
58
INH
05
IND, X
INH
EXT
77
hh ll
IND, Y
18
67
47
ff
INH
57
REL
24
rr
1D
ff mm
25
rr
INH
67
ff
IND, Y
18
REL
27
rr
REL
2C
rr
REL
2E
rr
REL
22
rr
REL
24
rr
IMM
85
ii
B5
hh ll
IND, Y
18
A5
ff
DIR
IND, X
DIR
IND, X
EXT
IMM
EXT
IND, Y
1D
ff mm
95
A5
C5
18
dd
ff
REL
dd mm
DIR
IND, X
15
ii
F5
hh ll
E5
ff
D5
E5
dd
ff
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BLE
BLO
BLS
BLT
BMI
BNE
BPL
BRA
BRCLR
BRN
BRSET
BSET
BSR
BVC
BVS
Branch if
Zero
REL
2F
rr
Branch if
Lower or
Same
REL
25
rr
REL
23
rr
Branch if <
Zero
REL
2D
rr
Branch if Not
= Zero
REL
2B
rr
REL
26
rr
REL
2A
rr
REL
20
rr
1F
ff mm rr
21
rr
ff mm rr
dd mm
Branch if
Lower
Branch if
Minus
Branch if
Plus
Branch
Always
Branch if
Bit(s) Clear
Branch
Never
18
DIR
IND, Y
18
IND, X
1C
REL
Set Bit(s)
DIR
Branch to
Subroutine
Branch if
Overflow
Clear
Branch if
Overflow Set
CBA
Compare A
to B
CLR
IND, Y
IND, X
IND, X
Operation
CLI
Branch if
Bit(s) Set
Mnemonic
CLC
DIR
Clear Carry
Bit
Clear
Interrupt
Mask
Clear
Memory Byte
13
dd mm rr
1F
ff mm rr
12
dd mm rr
1E
ff mm rr
1E
14
5
4
8
6
ff mm
rr
IND, Y
18
8D
REL
28
rr
REL
29
rr
INH
11
INH
0C
INH
0E
EXT
7F
hh ll
IND, Y
18
6F
ff
REL
1C
ff mm
Instruction
Addressing
Bytes Cycles
Mode
IND, X
6F
ff
Condition Codes
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CLRA
CLRB
CLV
CMPA
CMPB
COM
COMA
COMB
CPD
CPX
CPY
DAA
Clear
Accumulator
A
Clear
Accumulator
B
Clear
Overflow
Flag
Compare A
to Memory
Compare B
to Memory
1's
Complement
Memory Byte
1's
Complement
A
1's
Complement
B
Compare D
to Memory
16-Bit
Compare X
to Memory
16-Bit
Compare Y
to Memory
16-Bit
Decimal
Adjust A
INH
4F
INH
5F
INH
0A
IMM
81
ii
B1
hh ll
IND, Y
18
A1
ff
DIR
IND, X
E1
73
hh ll
DIR
IND, X
EXT
IMM
EXT
A1
C1
IND, Y
18
IND, X
EXT
91
dd
ff
ii
F1
hh ll
E1
ff
D1
63
dd
ff
ff
2
2
4
6
IND, Y
18
63
ff
INH
43
INH
53
IMM
1A
83
jj kk
EXT
1A
B3
hh ll
IND, Y
CD
A3
ff
DIR
IND, X
DIR
IND, X
IMM
1A
1A
93
A3
dd
ff
8C
jj kk
BC
hh ll
IND, Y
CD
AC
ff
DIR
18
EXT
IMM
EXT
18
AC
dd
ff
8C
jj kk
18
BC
hh ll
18
AC
ff
IND, X
1A
INH
IND, Y
9C
9C
AC
19
dd
ff
3
1
7
2
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DEC
DECA
DECB
DES
DEX
DEY
EORA
EORB
FDIV
IDIV
INC
INCA
INCB
INS
INX
Decrement
Memory Byte
EXT
7A
hh ll
IND, Y
18
6A
ff
INH
4A
Decrement
Accumulator
B
INH
5A
Decrement
Index
Register X
INH
34
INH
09
INH
18
09
IMM
88
ii
B8
hh ll
IND, Y
18
A8
ff
DIR
IND, X
IND, Y
18
E8
INH
03
41
INH
02
41
EXT
7C
hh ll
IND, Y
18
6C
ff
INH
4C
Increment
Accumulator
B
INH
5C
Increment
Index
Register X
INH
31
INH
08
Decrement
Accumulator
A
Decrement
Stack Pointer
Decrement
Index
Register Y
Exclusive OR
A with
Memory
Exclusive OR
B with
Memory
Fractional
Divide 16 by
16
Integer
Divide 16 by
16
Increment
Memory Byte
Increment
Accumulator
A
Increment
Stack Pointer
IND, X
DIR
IND, X
EXT
IMM
EXT
IND, X
6A
98
A8
C8
ff
dd
ff
ii
F8
hh ll
E8
ff
D8
6C
dd
ff
ff
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INY
JMP
JSR
Mnemonic
LDAA
LDAB
LDD
LDS
LDX
LDY
LSL
Increment
Index
Register Y
Jump
Jump to
Subroutine
Operation
Load
Accumulator
A
Load
Accumulator
B
Load Double
Accumulator
D
Load Stack
Pointer
Load Index
Register X
Load Index
Register Y
Logical Shift
Left
INH
18
08
EXT
7E
hh ll
IND, Y
18
6E
ff
EXT
BD
hh ll
IND, Y
18
AD
ff
IMM
86
IND, Y
18
DIR
IND, X
E6
CC
jj kk
FC
hh ll
EC
ff
IND, X
DIR
IND, X
6E
9D
AD
ff
dd
ff
Instruction
Addressing
Bytes Cycles
Mode
DIR
IND, X
EXT
IMM
EXT
ii
B6
hh ll
A6
ff
96
A6
C6
dd
ff
ii
F6
hh ll
E6
ff
D6
dd
ff
IND, Y
18
DIR
DC
IND, X
EC
8E
jj kk
BE
hh ll
IND, Y
18
AE
ff
DIR
DE
IND, X
EE
18
CE
jj kk
FE
hh ll
EE
ff
IMM
EXT
IND, Y
18
DIR
IND, X
IMM
EXT
IMM
EXT
9E
AE
hh ll
EE
ff
IND, X
1A
EE
EXT
78
IND, X
FE
DE
18
18
IND, Y
ff
DIR
18
dd
jj kk
CD
EXT
ff
CE
IND, Y
IMM
dd
68
dd
ff
dd
ff
hh ll
ff
2
3
Condition Codes
5
5
6
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LSLA
LSLB
LSLD
LSR
LSRA
LSRB
LSRD
MUL
NEG
NEGA
NEGB
NOP
ORAA
ORAB
PSHA
PSHB
PSHX
PSHY
Logical Shift
Left A
Logical Shift
Left B
Logical Shift
Left Double
Logical Shift
Right
Logical Shift
Right A
Logical Shift
Right B
Logical Shift
Right Double
Multiply 8 by
8
2's
Complement
Memory Byte
2's
Complement
A
2's
Complement
B
No Operation
OR
Accumulator
A (Inclusive)
OR
Accumulator
B (Inclusive)
Push A onto
Stack
Push B onto
Stack
Push X onto
Stack
Push Y onto
Stack
IND, Y
18
68
48
ff
INH
58
INH
05
IND, X
INH
EXT
74
hh ll
IND, Y
18
64
44
ff
INH
54
INH
04
INH
3D
10
IND, X
60
INH
EXT
64
ff
2
1
70
hh ll
ff
6
2
IND, Y
18
60
ff
INH
40
INH
50
INH
01
DIR
9A
dd
IND, X
IMM
EXT
8A
ii
BA
hh ll
IND, Y
18
AA
ff
DIR
DA
IND, X
EA
36
IMM
EXT
AA
CA
ff
ii
FA
hh ll
EA
ff
dd
ff
IND, Y
18
INH
37
INH
3C
INH
18
3C
INH
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PULA
PULB
PULX
PULY
ROL
Pull A from
Stack
INH
32
Pull X from
Stack
INH
33
INH
38
INH
18
38
IND, X
Pull B from
Stack
Pull Y from
Stack
Rotate Left
ROLA
Rotate Left A
ROR
Rotate Right
ROLB
RORA
RORB
RTI
RTS
Rotate Left B
Rotate Right
A
Rotate Right
B
Return from
Interrupt
Return from
Subroutine
Mnemonic
Operation
SBA
Subtract B
from A
SBCA
SBCB
SEC
SEI
SEV
STAA
Subtract with
Carry from A
Subtract with
Carry from B
Set Carry
Set Interrupt
Mask
Set Overflow
Flag
Store
Accumulator
A
EXT
79
hh ll
ff
69
IND, Y
18
69
INH
59
INH
EXT
IND, X
ff
49
76
hh ll
ff
66
ff
IND, Y
18
66
46
INH
56
INH
3B
12
INH
39
INH
10
DIR
92
dd
IND, X
INH
Instruction
Addressing
Bytes Cycles
Mode
IMM
82
IND, Y
18
DIR
IND, X
E2
0D
INH
0B
EXT
B7
hh ll
EXT
IMM
EXT
B2
hh ll
A2
ff
A2
INH
IND, X
C2
18
DIR
IND, Y
INH
ii
ff
ii
F2
hh ll
E2
ff
D2
0F
97
A7
dd
ff
dd
ff
2
1
Condition Codes
4
2
4
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STAB
STD
STOP
STS
STX
STY
SUBA
SUBB
SUBD
SWI
TAB
TAP
Store
Accumulator
B
Store
Accumulator
D
Stop Internal
Clocks
Store Stack
Pointer
Store Index
Register X
Store Index
Register Y
Subtract
Memory from
A
Subtract
Memory from
B
Subtract
Memory from
D
Software
Interrupt
Transfer A to
B
Transfer A to
CC Register
IND, Y
18
EXT
DIR
IND, X
F7
hh ll
E7
ff
E7
DD
ED
CF
IND, Y
18
DIR
EXT
EXT
INH
D7
18
IND, X
ff
IND, Y
DIR
A7
dd
ff
dd
2
2
4
4
FD
hh ll
ED
ff
9F
ff
dd
2
1
5
2
BF
hh ll
IND, Y
18
AF
ff
EXT
IND, X
DIR
AF
DF
EF
18
DF
IND, X
1A
EF
IMM
IND, X
IND, Y
CD
EXT
18
DIR
ff
dd
2
2
5
4
FF
hh ll
EF
ff
ff
dd
2
3
5
5
FF
hh ll
18
EF
ff
DIR
90
dd
IND, X
IND, Y
EXT
80
ff
ii
B0
hh ll
IND, Y
18
A0
ff
DIR
IND, X
E0
83
jj kk
B3
hh ll
IND, Y
18
A3
ff
INH
INH
IMM
EXT
C0
IND, Y
18
DIR
IND, X
IMM
EXT
INH
A0
ff
ii
F0
hh ll
E0
ff
D0
93
A3
dd
ff
dd
ff
3F
16
06
2
2
4
5
14
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TBA
TEST
TPA
TST
TSTA
TSTB
TSX
TSY
TXS
TYS
WAI
XGDX
XGDY
Mnemonic
Transfer B to
A
TEST (Only
in Test
Modes)
Transfer CC
Register to A
Test for Zero
or Minus
INH
17
INH
00
INH
07
IND, X
EXT
7D
hh ll
IND, Y
18
6D
ff
INH
4D
INH
5D
INH
30
Transfer
Stack Pointer
to Y
INH
18
30
Transfer X to
Stack Pointer
Transfer Y to
Stack Pointer
INH
35
Wait for
Interrupt
INH
18
35
INH
3E
**
INH
8F
INH
18
8F
Test A for
Zero or
Minus
Test B for
Zero or
Minus
Transfer
Stack Pointer
to X
Exchange D
with X
Exchange D
with Y
Operation
6D
ff
Instruction
Addressing
Bytes Cycles
Mode
Condition Codes
Cycle:
* Infinity or until reset occurs.
** 12 cycles are used beginning with the opcode fetch. A wait state is entered which remains in effect for an
integer number of MPU E-clock cycles (n) until an interrupt is recognized. Finally, two additional cycles
are used to fetch the appropriate interrupt vector (total = 14 + n).
Operands:
dd = 8-bit direct address $0000-$00FF. (High byte assumed to be $00.)
ff
= 8-bit positive offset $00 (0) to $FF (255) added to index.
ii
jj
= One byte of immediate data.

= High order byte of 16-bit immediate data.
hh = High order byte of 16-bit extended address.

kk = Low order byte of 16-bit immediate data.
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ll
= Low order byte of 16-bit extended address.
rr
= Signed relative offset $80 (-128) to $7F (+127). Offset relative to the address following the machine
code offset byte.
mm = 8-bit bit mask (set bits to be affected).
Condition Codes:
Bit not changed.
Always cleared (logic 0).

Always set (logic 1).
Bit cleared or set depending on operation.

Bit may be cleared, cannot become set.
ELE 205 home
Last modified at 1:36 a.m. on 9/7/2005
1/23/2016 4:46 PM

68hc11 Instruction Set

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68hc11 Instruction Set

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68HC11 Instruction Set