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2/1/02
Introduction to Verilog
Verilog
Coding Styles
Behavioral C-like constructs
RTL Register Transfer Logic.
Refers to the subset of constructs that is said
to be synthesizable.
Structural Gate instantiations; Netlist
2/1/02
Introduction to Verilog
RTL
`timescale = 1n/1p
module testbench;
reg clk, reset, enable;
wire [15:0] dout;
counter i1( clk, reset, enable, dout);
initial begin
clk = 0;
forever #20 clk = !clk;
end
always @(dout)
$display (value = %d, dout);
initial begin
reset = 1;
enable = 0;
# 10 reset = 0;
# 100 enable = 1;
repeat(100) @(posedge clk);
$finish;
end
endmodule
2/1/02
Introduction to Verilog
Structural
m odule testbench;
2/1/02
Introduction to Verilog
Verilog Simulation
module testbench;
reg clk;
module testbench;
reg clk;
initial
begin
clk = 0;
forever #20 clk = !clk;
end
initial
begin
clk = 0;
forever #20 clk = !clk;
end
some_module dut(clk)
some_module dut(clk)
endmodule
endmodule
2/1/02
Introduction to Verilog
Verilog Simulation
verilog testbench.v design.v
or
verilog testbench.v design.v +gui -s
2/1/02
Introduction to Verilog
Verilog Simulation
Libraries
2/1/02
Verilog Simulation
Referencing Cell Libraries
Example 1. Referencing a library directory
Options:
-y <directory name>
+libext+<extensions>+
2/1/02
Introduction to Verilog
Verilog Simulation
Library References: The `uselib Directive
2/1/02
Introduction to Verilog
Verilog Simulation
Library References: The `uselib Directive
Syntax:
uselib <LIB_REF>
where LIB_REF includes any of the following:
file=<libfile.v>
dir=<libdir>
libext=<libext>
<empty>
2/1/02
Introduction to Verilog
10
Verilog Simulation
Library References: The `uselib Directive
Example:
`define BEH_LIB file=/home/cad/custom/cells.vb
module top(portlist.)
// use RTL models
`uselib dir=/home/cad/custom libext=.vr
asic1
asic2
asic3
u1(portlist);
u2(portlist);
u3(portlist);
// RTL model
endmodule
`uselib
`resetall
2/1/02
Introduction to Verilog
11
Waveform Viewers
Signalscan
Undertow
2/1/02
Introduction to Verilog
12
Waveform Viewers
Typical capability
Navigate Hierarchy
View selected signals
Group signals
Bundle Signals into buses
Expand buses into bits
Search for events
Save/restore do files
2/1/02
Introduction to Verilog
13
Waveform Viewers
Demo
2/1/02
Introduction to Verilog
14
Verilog HDL
Language Basics
2/1/02
Introduction to Verilog
15
Lexical Conventions
White Space
Verilog is a free format language
White space characters include spaces, tabs,
and carriage returns
Use white space to enhance readability.
2/1/02
Introduction to Verilog
16
Comments
Single line comments
Begin with // and end with a carriage return
May begin anywhere on the line
2/1/02
17
Identifiers
Identifiers include module names, variable
names, task names, function names, etc.
Identifiers are case sensitive.
Identifiers must begin with a alphabetical
character (a z , A Z)
Identifiers may contain letters, numbers,
underscores, and dollar signs
2/1/02
Introduction to Verilog
18
Case Sensitivity
Verilog is case sensitive
Identifiers
Identifiers that differ in case are considered
unique
Keywords
All Verilog keywords are lowercase
2/1/02
Introduction to Verilog
19
Data Types
Logic Values
Nets, Registers, Vectors
Integer, Real, Time
Arrays
Memories
Parameters
Strings
2/1/02
Introduction to Verilog
20
Logic Values
Verilog has 4 logic values
2/1/02
0
1
z or Z
x or X
Introduction to Verilog
21
Nets
Represent connections between h/w elements
Are continuously driven by device outputs
Do not store data, only propagate it
Keyword: wire
Syntax:
wire datain;
wire [15:0] some_bus;
2/1/02
Introduction to Verilog
22
Registers
Represent data storage elements
Retain their value until updated
Can be declared inside of named blocks
Keyword: reg
Syntax:
reg data_out;
reg [15:0] bus_driver;
2/1/02
Introduction to Verilog
23
Vectors
Nets and registers can be declared as
vectors having multi-bit widths.
Can be declared as:
[high# : low#] or [low# : high#]
The left-hand value always specifies
the index of the msb
Bit accessible
2/1/02
Introduction to Verilog
24
Memories
Declared as two-dimensional array of registers.
Syntax:
reg [msb : lsb] <memory name> [first_addr : last_addr];
where:
msb:lsb - specifies the width (word size)
first_addr : last_addr - specifies the depth (address range)
Example:
reg [15:0] my_mem [0:1023] // 1k x 16
reg [7:0] your_mem [0:511] // 512 x 8
Rarely synthesized
2/1/02
Introduction to Verilog
25
Memories
Memories are word accessible.
A bit or subrange is not directly accessible
May be initialized from a file using system
tasks:
$readmemb
$readmemh
2/1/02
Introduction to Verilog
26
Memories
$readmemh(<file_name>,
<register_array>,
[<start_addr>,[<end_addr>]])
Open file for reading, and loads the contents into a
register memory array
File must be ASCII with values represented in hex
($readmemh) or binary ($readmemb)
2/1/02
Introduction to Verilog
27
Numbers
Integer Constants
Syntax:
Width:
widthradix value
optional, defaults to 1
Radix:
optional
D or d :
H or h :
O or o :
B or b :
2/1/02
Decimal (default)
Hexidecimal
Octal
Binary
Introduction to Verilog
28
Numbers
Integer Constants
Examples:
16h A725
5b 11001
7o 155
5d 25
2/1/02
Introduction to Verilog
29
Numbers
Real Constants
Decimal Notation
Scientific Notation
Examples:
Y = 105.6
Y = 1.2e-6
2/1/02
Introduction to Verilog
30
Numbers
Parameters
Defined inside a module
Local scope
May be overridden at instantiation time
If multiple parameters are defined, they must be
overridden in the order they were defined. If an
overriding value is not specified, the default parameter
declaration values are used.
Introduction to Verilog
31
Numbers
Parameters Using Defparam
module secret_number;
parameter my_secret_number = 0;
initial
$display(Hello World, my secret number is %d, my_secret_number);
endmodule
--------------------------------------------------------------------------------------------module top;
defparam inst1.my_secret_number = 37,
inst2.my_secret_number = 16;
secret_number inst1();
secret_number inst2();
endmodule
2/1/02
Introduction to Verilog
32
Numbers
Parameter Overriding Values
module secret_number;
parameter my_secret_number = 0;
initial
$display(Hello World, my secret number is %d, my_secret_number);
endmodule
--------------------------------------------------------------------------------------module top;
secret_number #(37) inst1();
secret_number #(16) inst2();
endmodule
2/1/02
Introduction to Verilog
33
Numbers
Parameter Overriding Values
module secret_numbers;
parameter sn1 = 0;
parameter sn2 = 0;
parameter sn3 = 0;
initial
$display(Hello World, my secret numbers are %d %d %d, sn1, sn2, sn3);
endmodule
-----------------------------------------------------------------------------------------------module top;
secret_number #(37, 54, 23) inst1();
secret_number #(16, 20) inst2();
endmodule
2/1/02
Introduction to Verilog
34
Compiler Directives
`define
Specifies an alias that is resolved at compile time.
References to the alias are preceded with a ` (back
tick). These are commonly used as state names in
state machines
Example:
`define DATA_STATE 4h2
if (state == `DATA_STATE)
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Introduction to Verilog
35
Compiler Directives
`include
Used to include the contents of one source file
inside another. The included file is expanded at
compile time.
Example:
`include header.v
2/1/02
Introduction to Verilog
36
Design Methodology
Top Down
Bottom up
Both partition the design hierarchically.
Each functional block (and sub-block) is
described as a module in Verilog. A module
is the fundamental building block in
Verilog.
2/1/02
Introduction to Verilog
37
2/1/02
bottom up
top down
Design Methodology
Introduction to Verilog
38
Testbench
Generates stimulus
Checks response
2/1/02
Introduction to Verilog
39
Stimulus
Generator
DUT
Checker
2/1/02
Introduction to Verilog
40
Modules
A module is the fundamental building block
in Verilog.
Modules are declared by the keywords
module and endmodule
2/1/02
Introduction to Verilog
41
Modules
Example:
module <module name> [ ( <port list> ) ];
...
functional description
...
endmodule
2/1/02
Introduction to Verilog
42
Ports
The port list defines the order of the ports.
The port list does NOT specify the type of
the port (input, output, or inout), nor the
width of the port.
Port properties are specified inside the
module using the keywords input, output,
and inout.
2/1/02
Introduction to Verilog
43
Ports
module D_FF(clk, reset, d, q);
input clk, reset;
input [7:0] d;
output [7:0] q;
reg [7:0] q;
always @(posedge reset or posedge clk)
if (reset)
q <= 8'h00;
else
q <= d;
endmodule
2/1/02
Introduction to Verilog
44
Instances
Lower level modules are assembled into
higher level modules by way of
instantiation.
Interconnect is implemented either by order
or by name.
2/1/02
Introduction to Verilog
45
Instances
module pipe(clk, reset, x, y);
input clk, reset;
input x;
output y;
// connect by order
DFF
DFF
DFF
DFF
endmodule
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Introduction to Verilog
46
Instances
module pipe(clk, reset, x, y);
input clk, reset;
input x;
output y;
// connect by name
DFF
DFF
DFF
DFF
endmodule
2/1/02
Introduction to Verilog
47
Dataflow Modeling
RTL
Continuous Assignment
Operators
2/1/02
Arithmetic, Logical
Bitwise, Reduction
Relational, Equality, Conditional
Shift
Concatenation, Replication
Introduction to Verilog
48
Dataflow Modeling
2/1/02
assign
Examples
assign q = (a & b ) | c;
assign q = s ? d1 : d0;
Introduction to Verilog
49
Dataflow Modeling
Arithmetic Operators
Binary
Multiply
Divide
Add
Subtract
Modulus
*
/
+
%
Unary
Positive
Negative
2/1/02
+
Introduction to Verilog
50
Dataflow Modeling
Arithmetic Operators
Examples
A = 4b0011; B = 4b0010;
Y = A * B;
Y = A / B;
Y = A + B;
Y = A - B;
//
//
//
//
Y -> 4b1100
Y -> 4b0000
Y -> 4b0101
Y -> 4b0010
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Introduction to Verilog
51
Dataflow Modeling
Arithmetic Operators
Examples
16 % 5
16 % 4
-16 % 5
16 % -5
-> 1
-> 0
-> -1
-> 1
Introduction to Verilog
52
Dataflow Modeling
Logical Operators
Evaluates to 1-bit value
Operands equal to zero are FALSE, all
others are TRUE
Operators
Logical-and &&
Logical-or ||
Logical-not !
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Introduction to Verilog
53
Dataflow Modeling
Relational Operators
Evalutes to TRUE or FALSE
Evaluates to x if any operand bits are x or z
Operators
2/1/02
greater-than
less-than
greater-than-or-equal-to
less-than-or-equal-to
>
<
>=
<=
Introduction to Verilog
54
Dataflow Modeling
Equality Operators
Evalutes to TRUE or FALSE
Operators
2/1/02
Logical equality
Logical inequality
Case equality
Case inequality
==
!=
===
!==
Introduction to Verilog
55
Dataflow Modeling
Equality Operators
Expression Description
EvaluationValues
a == b
a equal to b, result
unknown if x or z in a or b
0, 1, x
a != b
0, 1, x
a === b
a equal to b, including x
and z
0, 1
a !== b
0, 1
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Introduction to Verilog
56
Dataflow Modeling
Bitwise Operators
Performs bit-by-bit operation on two n-bit
operands, yielding an n-bit result
If operands have differing lengths, the shorter one
is zero extended first
Operators
2/1/02
negation
and
or
xor
xnor
~
&
|
^
~^ , ^~
Introduction to Verilog
57
Bitwise Operators
Examples:
a = 4b0001;
b = 4b1001;
y = a & b;
y = a | b;
y = a ^ b;
2/1/02
// y -> 4b0001
// y -> 4b1001
// y -> 4b1000
Introduction to Verilog
58
Dataflow Modeling
Reduction Operators
Performs operation on all bits of a single
operand, yielding an 1-bit result
Operators
2/1/02
negation
and
or
xor
xnor
~
&
|
^
~^ , ^~
Introduction to Verilog
59
Reduction Operators
Examples:
x = 4b0001;
y = &x;
y = |x;
y = ^x;
2/1/02
// y -> 1b0
// y -> 1b1
// y -> 1b1
Introduction to Verilog
60
Dataflow Modeling
Shift Operators
Shifts a vector left or right by a specified
number of bits.
Zero fill
No wrap around
Operators
Right Shift
Left Shift
2/1/02
>>
<<
Introduction to Verilog
61
Shift Operator
Examples:
// X = 4b1100
Y = X >> 1 // Y -> 4b0110
Y = X << 1 // Y -> 4b1000
Y = X << 2 // Y -> 4b0000
2/1/02
Introduction to Verilog
62
Dataflow Modeling
Concatenation Operator
Appends multiple operands
Provides mechanism to bundle separate
signals and vectors into a single vector
Operator:
Operands:
{,}
Introduction to Verilog
63
Dataflow Modeling
Concatenation Operator
Example:
// A = 1b1, B = 2b01, C = 4b1100
Y = {A , B}
Y = {A , C[2:1] , 1b11}
2/1/02
=>
=>
Introduction to Verilog
3b101
5b11011
64
Dataflow Modeling
Replication Operator
Provides a mechanism to perform repetitive
concatenation.
Example:
// A = 1b1 B = 2b01 C = 3b101
Y = 4{A}
=> 4b1111
Y = 2{A , B}
=> 6b101101
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Introduction to Verilog
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Dataflow Modeling
Conditional Operator
Usage:
condition_expr ? true_expr : false_expr
Behaves like a 2-to-1 mux or an if-else
expression.
Example:
assign out = control ? in_1 : in_0
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Dataflow Modeling
Operator Precedence
2/1/02
Operator
Symbols
Precedence
Unary
Multiply, Divide, Modulus
+ - ! ~
* / %
highest
Add, Subtract
Shift
+ << >>
Relational
Equality
Reduction
& ~&
^ ^~
| ~|
Introduction to Verilog
67
Dataflow Modeling
Operator Precedence
2/1/02
Operator
Symbols
Logical
&&
||
Conditional
?:
Precedence
lowest
Introduction to Verilog
68
Dataflow Modeling
Perform Labs
2/1/02
Introduction to Verilog
69
Behavioral Modeling
2/1/02
Introduction to Verilog
70
Behavioral Modeling
Structured Procedures
Initial Blocks
Executed exactly one time
Always Blocks
Loop continuously for the duration of the simulation
2/1/02
Introduction to Verilog
71
Behavioral Modeling
Procedural Assignment
Types
Blocking assignment
Non-blocking assignment
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Introduction to Verilog
72
Behavioral Modeling
Blocking Assignment
Executed in the order they appear in a
procedural block
Example:
b = a;
a = x;
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Introduction to Verilog
73
Blocking Assignments
initial
begin
Event Queues
Execution
Order
a = b;
c = d;
e = f;
a <- b(t)
c <- d(t)
e <- f(t)
end
2/1/02
t+1
t+2
t+3
Time
Introduction to Verilog
74
Behavioral Modeling
Non-blocking assignment
Implements concurrency in a procedural block.
Schedules the assignment without blocking execution
of subsequent statements in a procedural block
Executes at the end of the time step
Order of execution is indeterminate
Example:
x <= a;
y <= x ;
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Non-blocking Assignments
initial
begin
Event Queues
a <= b;
2/1/02
Execution
Order
end
a <- b(t)
Introduction to Verilog
t+1
t+2
t+3
Time
76
Timing Controls
Delay-Based Timing Control
Event-Based Timing Control
Level Sensitive Timing Control
2/1/02
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Introduction to Verilog
78
Event Queues
#1 a = b;
a <- b(t+1)
2/1/02
Execution
Order
end
Introduction to Verilog
t+1
t+2
t+3
Time
79
Equivalent
initial
begin
#1 a = b;
#1 c = d;
#1 e = f;
#1
a = b;
#1
c = d;
#1
e = f;
end
end
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80
Event Queues
a <- b(t+1)
c <- d(t+2)
e <- f(t+3)
t+1
t+2
t+3
Execution
Order
#1 a = b;
#1 c = d;
#1 e = f;
end
Time
2/1/02
Introduction to Verilog
81
Blocking Intra-procedural
Delayed Assignment
initial
begin
Event Queues
a = #1 b;
a <- b(t)
2/1/02
Execution
Order
end
Introduction to Verilog
t+1
t+2
t+3
Time
82
Event Queues
#1 a <= b;
2/1/02
Execution
Order
end
a <- b(t+1)
Introduction to Verilog
t+1
t+2
t+3
Time
83
Non-blocking
Intra-procedural
Delayed Assignment
initial
begin
Event Queues
a <= #1 b;
2/1/02
Execution
Order
end
a <- b(t)
Introduction to Verilog
t+1
t+2
t+3
Time
84
Non-blocking
Intra-procedural
Delayed Assignment
initial
begin
Event Queues
end
Execution
Order
a <= #1 b;
c <= #1 d;
e <= #1 f;
a <- b(t)
c <- d(t)
e <- f(t)
t+1
t+2
t+3
Time
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end
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end
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Rules of Thumb
1. Use blocking assignments without delays
for combinational always blocks.
2. Use non-blocking assignments exclusively
for sequential always.
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93
QUIZ
always @(posedge clk)
a = b;
always @(posedge clk)
b = a;
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QUIZ
always @(posedge clk)
a <= b;
always @(posedge clk)
b <= a;
2/1/02
Introduction to Verilog
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Programming Statements
Branching
if
if - else
case, casex, casez
2/1/02
Iteration
Introduction to Verilog
repeat
forever
while
for
96
if
if (cond_expr)
statement or
statement_group
yes
cond_expr
TRUE?
no
Statement
Example:
if (enable)
dout = din;
2/1/02
or group
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if - else
if (cond_expr)
statement or
statement_group
else
statement or
statement_group
2/1/02
yes
cond_expr
TRUE?
no
Statement
Statement
or group
or group
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case
case (<reg or net>)
cond_1: statement or
group
cond_2,
cond_3: statement or
group
default: statement or
group
endcase
cond_1
yes
no
cond_2
yes
no
cond_3
yes
no
default
yes
no
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casez
Considers all occurrences of z in the case
expression or case alternatives to be dont
cares.
Compares only non-z positions in thecase
expression and case alternatives
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100
casex
Considers all occurrences x and z in the
case expression or case alternatives to be
dont cares.
Compares only non-x or -z positions in the
case expression and case alternatives
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while
while (while_expr)
statement or
statement group
Repetitively executes
the statement group
as long as the
while_expr is TRUE.
2/1/02
while_expr
TRUE?
Introduction to Verilog
yes
no
102
repeat
Repeat (<number of times>)
statement or
statement_group
Repetitively executes the statement_group a
fixed number of times
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repeat
Example
//Hold reset high for 20 clock periods
initial
begin
reset = 1b1;
repeat (20) @(posedge clk);
reset = 1b0;
end
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forever
forever
statement or
statement_group
Repetitively executes the statement group
until the simulation is terminated with the
$finish system task.
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forever
Example
//Generate a clock with period of 10
initial
begin
clk = 1b0;
forever #5 clk = ~clk;
end
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for
for (initial_assignment;
cont_expr;
step_assignment)
statement or
statement_group
initial
assignment
cont_expr
TRUE?
no
exit
yes
statement
group
step
assignment
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for
Example
//intialize RAM with checkerboard pattern
initial
begin
for(addr = 0; addr < 32;addr = addr + 2)
ram[addr] = 8h55;
for(addr = 1; addr < 32;addr = addr + 2)
ram[addr] = 8hAA;
end
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Statement Groups
Sequential Blocks
begin
end
Parallel Block
fork
Join
Name Blocks
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109
Statement Groups
Sequential Blocks
Statements are processed in the order they are
specified
Any delay is relative to the time the previous
staement completed
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110
Sequential Block
Example
initial
begin
x = 1b1;
y = 1b0;
z = 4hf
end
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Statement Groups
Parallel Blocks
Statement are executed concurrently
Order does not matter
Any delay is relative to the time the block was
entered
Suseptable to race conditions. Why?
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Parallel Block
Example
initial
fork
x = 4h5;
y = 4h5;
z = x + y;
end
2/1/02
fork
X=4h5 Y=4h5
y=x+y
join
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Named Blocks
Allow variables variables
to be declared local to the
clock
Are part of the design
hierarchy.
Local variables can be
accessed with hierarchical
name referencing.
Can be disabled
2/1/02
initial
begin : block1
reg x;
x = 1;
end
initial
fork : block2
reg x, y;
#10 x = 1;
#20 y = 1;
join
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114
Nested Blocks
initial
begin
clk_1 = 0; clk_2 = 0; clk_3 = 0;
fork
forever #10 clk_1 = ~clk_1;
forever #20 clk_2 = ~clk_2;
forever #30 clk_3 = ~clk_3;
join
end
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Tasks
Syntax:
task <task name>;
[<tf_declarations>]
[<statement group]
end task
tf_declaration
Invocation:
<task name>
<task name>(arg1, arg2, )
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parameter
input, output, inout
reg
integer, real
time
event
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Functions
tf_declaration
Syntax:
type_range
Invocation:
<func_name> (arg1, arg2, );
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range
integer
real
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module mod2;
reg [3:0] x;
reg [7:0] y;
initial
begin
x = 4d10;
y = square(x);
$display(%d squared is %d,x,y);
End
function [7:0] square;
input [3:0] x;
begin
square = x * x;
end
endfunction
endmodule
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Moore Model
Outputs a function of current state only
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State
Registers
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Next State
Logic
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State
Registers
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Output
Logic
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