MOS Capacitors

Slides adapted from:

N. Weste, D. Harris, CMOS VLSI Design,
Addison-Wesley, 3/e, 2004
Kang, Lablebici CMOS Digital Integrated
Circuits, 3/e
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Shiv
Nadar
University

Channel length modulation

The reverse biased p-n junction

between the drain and the body
forms a depletion region with
length L that increases with Vdb.
The depletion region effectively
shorten the channel length to:
Leff = L L

Assuming the source voltage is close to the body votage

Vdb ~ Vsb. Hence, increasing Vds decrease the effective
channel length.
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Shiv
Nadar
University

Shorter channel length results in higher current

Here, is an empirical
model parameter, and is
called the channel length
modulationm coefficient.

Outline

The Big Picture

MOS Structure
Ideal I-V Charcteristic
MOS Capacitance Models

Shiv
Nadar
University

The Big Picture

So far, we have treated transistors as ideal switches
An ON transistor passes a finite amount of current
Depends on terminal voltages
Derive current-voltage (I-V) relationships
Transistor gate, source, drain all have capacitance
I = C (DV/Dt) Dt = (C/I) DV
Capacitance and current determine speed

MOS Transistor Symbol

MOS Structure
Gate and body form
MOS capacitor
Operating modes
Accumulation
Depletion
Inversion

nMOS Transistor Terminal Voltages

V
Mode of operation depends on Vg, Vd, Vs
+
+
V
V
Vgs = Vg Vs
Vgd = Vg Vd
V
V
+
V
Vds = Vd Vs = Vgs - Vgd
Source and drain are symmetric diffusion terminals
By convention, source is terminal at lower voltage
Hence Vds 0
nMOS body is grounded. First assume source is 0 too.
Three regions of operation
Cutoff
Linear
Saturation
g

gs

gd

ds

NMOS in cutoff operation mode

No channel
Ids = 0

NMOS in linear operation mode

Channel forms
Current flows from D to S,
Ids increases with Vds,Similar to linear resistor

Shiv
Nadar
University

nMOS in Saturation operation mode

Channel pinches off

Ids independent of Vds
We say current saturates
Similar to current source

10

I-V Characteristics (nMOS)

In Linear region, Ids depends on
How much charge is in the channel?
How fast is the charge moving?

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NMOS I-V Summary

first order transistor models

Vds
I ds Vgs Vt
2

Vgs Vt

Vgs Vt
V V V
ds
ds
dsat

Vds Vdsat

cutoff
linear
saturation
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I-V characteristics of nMOS Transistor

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Example
0.6 mm process from AMI Semiconductor

Plot Ids vs. Vds

Vgs = 0, 1, 2, 3, 4, 5
Use W/L = 4/2 l
3.9 8.85 1014 W
W
mCox 350
L
8
L
100 10

2.5

Vgs = 5

2
Ids (mA)

tox = 100
m = 350 cm2/V*s
Vt = 0.7 V

1.5

Vgs = 4

1
Vgs = 3

0.5
0

Vgs = 2
Vgs = 1

Vds

120
m A /V 2

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MOS CAPACITANCE

The current-voltage characteristics investigated here can

be applied for investigating the DC response of MOS
circuits under various operating conditions.

In order to examine the transient (AC) response of

MOSFETs and digital circuits consisting of MOSFETs, on
the other hand, we have to determine the nature and
the amount of parasitic capacitances associated with the
MOS transistor.

In the following, we will develop simple approximations

for the on-chip MOSFET capacitances that can be used
in most hand calculations.
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Capacitances of a MOS Transistor

Any two conductors separated by an insulator
have capacitance
Gate to channel capacitor is very important
Creates channel charge necessary for
operation (intrinsic capacitance)
Source and drain have capacitance to body
(parasitic capacitance)
Across reverse-biased diodes
Called diffusion capacitance because it is
associated with source/drain diffusion

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Top View of MOSFET

17

In this figure, the mask length (drawn

length) of the gate is indicated by LM,
and the actual channel length is
indicated by L.
The extent of both the gate-source
and the gate-drain overlap are LD;
thus, the channel length is given by

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Based on their physical origins, the parasitic device

capacitances can be classified into two major groups:

oxide-related capacitances
--- Overlap Capacitance
--- Gate to Channel Capacitance

junction capacitances

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Overlap Capacitance

It was shown earlier that the gate electrode overlaps both

the source region and the drain region at the edges. The
two overlap capacitances that arise as a result of this
structural arrangement are called CGD (overlap) and CGS
(overlap), respectively.

Assuming that both the source and the drain diffusion

regions have the same width W, the overlap
capacitances can be found as

Note that both of these overlap capacitances do not

depend on the bias conditions, i.e., they are voltageindependent.

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Gate to Channel Capacitance

Since the channel region is connected to the source, the

drain,
and the substrate, we can identify three capacitances between the
gate and these regions, i.e.,Cgs, Cgd and Cgb respectively.

In Cut-off mode:
surface is not inverted. Consequently, there is no conducting
channel that links the surface to the source and to the drain.
Therefore, the gate-to-source and the gate-to-drain capacitances
are both equal to zero:

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Linear Mode
Channel extends across the MOSFET, between the
source and the drain.

This conducting inversion layer on the surface

effectively shields the substrate from the gate electric
field; thus:
Cgb = 0
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the distributed gate-to-channel capacitance as

seen between the gate and the source is
approximated by:

Saturation Mode
When the MOSFET is operating in
saturation mode, the inversion layer on the
surface does not extend to the drain,
Cgd = 0

Since the source is still linked

to the conducting channel, its shielding
effect also forces the gate-to-substrate
capacitance to be zero.

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Finally, the distributed gate-to-channel

capacitance as seen between the
gate and the source can be
approximated by

Total Capacitance

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Diffusion Capacitance
Csb, Cdb
Undesired capacitance (parasitic)
Due to the reverse biased p-n
junctions between source diffusion
and body and drain diffusion and body
Capacitance depends on area and
perimeter

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Lumped representation of the

MOSFET capacitances

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Shiv
Nadar
University

Non-ideal I-V effects

The saturation current increases less than quadratically with
increasing Vgs
Velocity saturation
Mobility degradation
Channel length modulation
Body Effect
Leakage currents
Sub-threshold conduction
Junction leakage
Tunneling
Temperature Dependence
Geometry Dependence
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Shiv
Nadar
University

Velocity saturation and

mobility degradation

At strong lateral fields

resulting from high Vds,
drift velocity rolls off due
to carrier scattering and
eventually saturates

Strong vertical fields

resulting from large Vgs
cause the carriers to
scatter against the
surface and also reduce
the carrier mobility. This
effect is called mobility
degradation

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