Design and Implementation of PID Controller

on FPGA using Velocity Algorithm

Dhirendra Kumar, IIT Roorkee and Barjeev Tyagi, IIT Roorkee

Abstract This paper describes the design of an FPGA

based Digital Proportional-Integral-Derivative (PID)
Controller implemented using Velocity Algorithm on
FPGA. The design uses a parallel multiplier and is two
times faster than controller designed using FPGAs
embedded multiplier. Design also results in reduced power
consumption compared to earlier approach. The plant used
in this regard is Load Disturbance Control in a DC Motor.
System level design tool System Generator using
Matlab/Simulink environment from Xilinx is utilized for this
purpose.
Index Terms PID (Proportional-Integral-Differential)
Controller, FPGA (Field Programmable Gate Array)
technology, Velocity Algorithm, Digital Controller.

I. INTRODUCTION

PID controller is most commonly used algorithm

for controller design and it is most widely used controller

in industry. The controllers used in industry are either PID
controller or its improved version. The basic types of PID
controller are: - Parallel controller, Serial controller,
Mixed controller.
The PID Controller Algorithm utilized for is design
Velocity Algorithm, it is also called Incremental
Algorithm. This Algorithm gives certain significant
advantage over Position Algorithm.
Earlier discrete feedback controller has been used to
implement various applications for ex.- Temp Control
using PWM inverter & Anti windup controller
compensation [1], Robotic control[2], DC Motor
control[3], AC/DC Converter[4], reduction of Vibration in
aircraft /Aerospace structure as well as helicopter
fuselage[5], Variable Speed Drive[9] and FPGAs
Embedded multiplier based PID controller[10].
Dhirendra Kunar is M.Tech from Department of Electrical
Engineering, Indian Institute of Technology, Roorkee- 247667, India (email: dhirendra100@gmail.com).
Barjeev Tyagi is with the Department of Electrical Engineering,
Indian Institute of Technology, Roorkee- 247667, India (e-mail:
btyagfee@iitr.ernet.in).

FPGA is a Digital Integrated circuit containing

Configurable
Logic
Blocks
with
configurable
interconnect between them. FPGA were introduced in
1985 by Xilinx Company, since then now many
companies Actel, Altera, Plessey, AMD, Quick Logic,
Algotronix, Concurrent Logic, & Cross Point Solutions
are producing FPGA.
FPGA gives advantage of faster and stronger
calculation with suitable sampling time requirement.
Multiple controllers can also be implemented in single
FPGA device so it can be utilized for controlling various
parameters of a complex plant.
The circuit to be implemented on FPGA is
implemented by breaking the logic into smaller logics.
These logics are further burnt on a Slice in a Configurable
Logic Block (CLB). Depending upon the FPGA family
and company each CLB contains two slices. The Slices
consists of Logic cells. These Logic cells are
interconnected using programmable interconnect. The
vast resource available with FPGA gives the advantage of
introducing parallelism in design, certain prominent
features of FPGA are:
Less design time.
Reduced Prototype cost
Reprogramability
High speed of operation
Capable of complex functionality
Capability to execute parallel operation
Reduced power consumption.
The organization of this paper is as follows section I
gives the brief idea of the previous work done and
components utilized, Section II presents the Velocity
Algorithm used and the block diagram implemented using
Xilinxs System Generator blockset. Section III gives
summary of device utilization. The PID controller used in
this regard is to be implemented using Spartan3e FPGA.
Section IV describes conclusions and future prospects,
Section V is the references, and finally the graph showing
the responses from the design.

II. DESIGNING OF PID CONTROLLERS MODULES FOR

FPGA ENVIRONMENT
The problem used in this paper is Load Disturbance
control in DC Motor, where PID controller is
implemented on Matlab/Simulink environment using
System Generator from Xilinx. PID controller will act in
order to reduce the effect of disturbance introduced in
system.

m ( k ) m ( k 1)
e ( k ) e ( k 1) 1
= Kc[
+ e( k )
T
T
TI

TD
{ e ( k ) 2 e ( k 1) + e ( k 2)}]
T2

(3)

Rearranging we get

m(k ) m(k 1) = Kc[{e(k ) e(k 1)} +

T
e(k )
TI

T
+ D { e ( k ) 2 e ( k 1) + e ( k 2)}]
T

(4)

Taking z transform of Eq (4)

(1 z1)M (z) = Kc[(1 z1)E(z) +

T
T
E(z) + D (1 2z1 + z2 )E(z)]
Ti
T
(5)

Fig-1 Closed Loop Digital Control System.

Block diagram for general purpose PID feedback

control system is shown in Fig-1, where input Uref is
reference signal, e is error signal between reference
signal and feedback signal y and u is control output.
The feedback system consists of plant model of dc motor
having input for load disturbance Td which introduces
disturbance which is to be controlled by PID controller.
In Velocity Algorithm [12] for implementation of PID
controller to obtain an equation that can be implemented
using computer, it is necessary to replace continuous time
operation like differentiation and integration by discrete
time operations in z domain.
Advantage of velocity algorithm: Wind up protection.
Bump less parameter changes are easy to
implement
The common PID controller equation is:-

Again rearranging the terms in Eq(5) we get

(1 z 1 ) M ( z ) = { K c +

{Kc + 2 Kc

Kc
T
+ K c. D } E ( z )
TI
T

TD 1
T
}z E ( z ) + {Kc D }z 2 E ( z ) (6)
T
T

Rearranging Eq (6) we get.

M (z)
A z 1 B z 2 + C
=
E (z)
1 z 1

(7)

Where

T
T
+ Kc. D ]
TI
T
T
&
B= [ Kc + 2 Kc D ]
T

A= [ Kc + Kc

C=

[ Kc

TD
]
T

State Transition Signal Flow Diagram

of the control law

m(t ) = Kc[e(t ) +

1
de(t )
e(t )dt + TD
] + Mss

TI 0
dt

(1)
Where Mss is steady state output of controller when the
error signal is zero, m(t) is final output and e(t) final error
in continuous time domain.
Differentiating the equation we get

dm(t )
de(t ) 1
d 2 e (t )
= Kc[
+ e(t ) + TD
]
dt
dt
TI
dt 2

(2)
This equation does not contain steady state value output
now discretizing the equation by method of Differential
Two Point Formula Backward Difference method at time
t=KT we get the equation.

Fig-2. STSFD for Velocity Algorithm.

This STSFD gives the basic idea for the implementation

of PID controller in as shown in Fig -3 using some basic
blocks available on software platform.

Fig 3. Block diagram to be implemented on simulation

Multiplier (16 bit 2s complement multiplier)

The input to the multiplier is signed data in 2s
complement form, so the 16 bit signed data is
converted to bits and supplied parallelly for
multiplication and a 16 bit signed output is generated
using the multiplier. The designed multiplier utilizes
.

JTAG Co-Simulation block allows to perform

hardware co-simulation using JTAG and a Parallel
Cable IV or Platform USB. The co-simulation block
interacts with the FPGA hardware platform during a
Matlab simulation. Simulation data written to the
input ports of the block is passed to the hardware by
the block. Conversely, when data is read from the cosimulation block's output ports, the block reads the
appropriate values from the hardware and drives
them on the output ports so they can be interpreted in
Simulink.
III. COMPARISION AND DEVICE UTILIZATION OF
FPGA BASED SYSTEM

Fig 4. Logic for 2s Complement Parallel Multiplier

As shown in Fig.4 Wallace Tree Multiplier[13]

with slight improvement is implemented for
obtaining 16 bit parallel output 2s complement form.
The multiplier A and B are set the multiplier.
Further, for multiplication each bit of input is
multiplied to multiplier according to wallace tree
multiplier implemented. For final stage carry is not
requiredso half adder can be used. The values of A, B
and
C are implemented in 2s complement form and are
to set into the multiplier.
The design implemented requires more
component on FPGA.Although it consumes larger
area on FPGA, but still lesser power consumption
compared to the embedded multiplier based PID
controller design, so it makes a very good tradeoff
between area consumed on FPGA and time taken for
processing using the same kit.
.
A. Hardware co-simulation block
Hardware co-simulation [14] block is a very
prominent feature of system generator. The Xilinx

The design implemented on FPGA has total

equivalent gate count of 3,333. It utilizes 503 slices
which is 10% of total slices count available on FPGA
Spartan 3e. The Optimized Wallace Tree Multiplier
is used for designing 2s Complement 16 bit
Multiplier. It utilizes parallelism in design in order to
reduce the time consumption, so there is a tradeoff
between resources utilized on FPGA and the speed of
design.
The PID controller implemented has maximum
clock frequency of 133.494 MHz i.e. a minimum
time period of 7.491ns, that means time required to
calculate the output is 7.491 ns. It has a power
consumption of 82 mW.
Table 1. shows the comparision of slices utilization
on FPGA, using both the approaches. The previous
approach implements the PID controller using
embedded multilplier and the present approach uses a
parallel multiplier implemented using wallace tree
multiplier.The table shows the number of gates
utilized while implementing the PID controller on
FPGA.

TABLE 1

Figure 5 below shows the operation of responses

obtained from a continuous time PID controller, a
embedded multiplier based PID controller and a
parallel multiplier based PID controller for a unit step
input given to the closed loop system .

COMPARISON OF IMPLEMENTATION ON FPGA

Gates
Utilization
Embedded multiplier
based PID
Parallel multiplier based
PID

Power
Consumption
(mW)

2278

83

3333

82

IV. RESULTS AND PERFORMANCES

A. Design developed on System Generator
The Load Disturbance control of DC Motor model
is developed in Matlab/Simulink environment
[14].The PID controller model developed for FPGA
Spartan3e 3s500efg320-4 from Xilinx is developed
in Matlabs System Generator. The PID controller
implemented on system generator and plant model
Matlab/Simulink are interfaced on Simulink using
System Generators gateway in and gateway out
blocks.
The design on FPGA is developed as follows: The
design is first implemented on Matlab/Simulink using
System Generator toolbox for design and results are
obtained from simulation, the design developed is
transferred on FPGA kit and response is obtained
from simulation as well as from the FPGA kit.
System Generator is a DSP design tool from Xilinx
that enables the use of model-based design
environment Simulink for FPGA design. Xilinx
FPGAs or RTL design methodologies are not
required when using System Generator[17].
Table2. Shows a comparison of response from three
approaches: a continuous time PID controller, an
embedded multiplier based PID controller and a
Parallel multiplier based PID controller. The response
was compared for Rise time, Settling time and the
time to recover from negative and positive
disturbances. The parallel multiplier based PID
controller proved to be better in terms of time
response compared the other two approaches.
TABLE 2
COMPARISON OF TIME RESPONSES OF DIFFERENT CONTROLLER
IMPLEMENTED ON FPGA
Rise
Time(sec)

Settling
Time (sec)

Tnd
(sec)

Tpd
(sec)

Continuous time
PID
Embedded
multiplier based
PID

1.5140

2.56

3.53

3.39

2.3816

4.34

4.54

4.19

Parallel multiplier
based PID

1.22

1.948

2.18

2.41

Figure 6 below shows the output from the FPGA

kit for the PID controller designed using parallel
multiplier, the response from the kit is exactly the
same as obtained from the simulation. Tnd and Tpd
are time to recover when disturbance is introduced
and gets over respectively.
B. Implementation on FPGA Spartan 3e
The System Generator[11] provides hardware cosimulation, making it possible to incorporate a design
running in an FPGA directly into a Simulink
simulation. "Hardware Co-Simulation" block
automatically generates a bitstream and associate it
to a block. When the design is simulated in Simulink,
results for the compiled portion are calculated in
hardware. This allows the compiled portion to be
tested in actual hardware and can speed up simulation
dramatically. The command line tool, XFLOW is
used to implement and configure design for the
selected FPGA platform.
C. CONCLUSIONS
In this paper the Velocity algorithm based digital
PID controller implementation on FPGA is presented.
The FPGAs capability of introducing parallelism is
utilized for multiplication while designing a 16 bit
2s complemented multiplier. It causes a slightly
large no of resources utilization on FPGA but at the
same timeit result in increased speed. The rise
time(TR) and settling time(TS) and time required to
recover from the disturbance(TD) are far better in
case of Parallel multiplier based PID controller
design compared to an Embedded multiplier based
PID controller and even better than continuous time
PID controller. Present design shows a reduced
power consumption.
Since Velocity Algorithm has been used so it takes
care of windup protection and also helps in Bump
less parameter changing.
The same model can be downloaded to various
versions of Xilinx and Altera FPGA chips. This
design can be further extended for fixed point
operations which will make the design more flexible
for real time operations and the responses closer or
even better real time system.

Step Response Comparison

1.5

Embedded multiplier
based PID
Parallel multiplier
based PID
Unit Step Input
Continuous time PID

Y(t)
0.5

10
15
Time (sec)

20

25

30

35

40

45

50

45

50

Fig 5. Comparison of unit response from Continuous time,

Embedded and Parallel Multiplier based PID controller.
Step response from FPGA kit
1.5

Y(t)

0.5

5
10
Time (sec)

15

20

25

30

35

40

Fig 6. Parallel multiplier based PID Controller response

obtained from FPGA kit.

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