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Abstract
This paper describes the implementation of multi-protocol data acquisition system on FPGA. Data acquisition system includes
four different bus protocols and storing element (FIFO). FPGA works as a data acquisition system and transfers data from the
sensors/ADC to the output device. As FPGA allows each module to work independently. Therefore, we can utilize FPGA as a
multi channeled data acquisition system. The four different protocols: Parallel bus protocol, SPI, I2C and One-Wire. All modules
were designed in VHDL& simulated using Xilinx-ISE 12.4and Xilinx Spartan -3E.
Keywords: FPAG, Xilinx, Spartan-3E kit, Parallel bus, SPI, I2C, One-Wire and FIFO.
--------------------------------------------------------------------***-----------------------------------------------------------------1. INTRODUCTION
The data acquisition systems are most widely employed as
measurement systems in many industries. Main part of the
data acquisition system is bus protocols used in it. Buses are
integral part of data transmission in electronic devices.
These buses are implemented in software so the main aim is
to collect data from sensors or ADCS. This paper describes
the implementation of parallel and serial data transfer
protocols along with comparison. Parallel protocol is alone
parallel data transfer protocol and remaining all are serial
data transfer protocols. Each protocol having their own
characteristics and applications. Some can be replaced by
other protocols and some applications needs particular bus
protocol like Display/printer connections needs parallel
lines.
All protocols implanted on FPGA kit and modeled using
VHDL. The digital signals are provided from multichannel
sensors and four different ADC protocols.
2. PROPOSED WORK
The proposed system is shown in Figure 1 & 2. It shows the
connection of the ADCs with Bus protocols. The Bus
protocol includes Parallel, SPI, I2C and One-wire. Each one
having separate ADC connections and the FPGA would
collect data from ADC sensors.
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Volume: 03 Issue: 07 | Jul-2014, Available @ http://www.ijret.org
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Volume: 03 Issue: 07 | Jul-2014, Available @ http://www.ijret.org
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Volume: 03 Issue: 07 | Jul-2014, Available @ http://www.ijret.org
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3.5 FIFO
A FIFO is a special type of buffer. The name FIFO stands
for first in first out and means that the data written into the
buffer first comes out of it first. They often called a stack
memory, and the shared memory. The choice of buffer
architecture depends on the application to be solved. Figure
9 shows generalized FIFO operation.
4. CONCLUSIONS
From the simulation results of the all bus protocol, we can
compare speed and pin count of all protocols. As parallel
bus having highest speed data transmission but alongside it
is having more pins. Similarly One-wire bus with only one
pin/line for communication but it is having limited
applications.
I 2C
having
advantage
of
slave
acknowledgement feature but SPI does not support this
feature.
Fig-9: General FIFO operation.
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Volume: 03 Issue: 07 | Jul-2014, Available @ http://www.ijret.org
393
REFERENCES
[1].
S.Thane,
S.Somkuamanit,
S.Khuntawee.
Implementation of Multi-Protocol, Data Acquisition with
High Speed USB interface, Using FPGA, The International
Multi Conference of Engineers and Computer Scientists
(IMECS)- Vol I, March 17-19, 2010. Hong Kong.
[2]. Frdric Leens, An Introduction to I2C and SPI
protocols. IEEE Instrumentation & Measurement Magazine
February 2009.
[3]. Bollam Eswari, N.Onmagal, K.Preethi, S.G. Sreejeesh,
Implementation of I2C Master Bus Controller on FPGA.
International Conference on Communication and Signal
Processing, April 3-5, 2013, India.
[4]. Bernhard Linke, Overview of 1-Wire Technology and
Its Use, Jun 19, 2008, Maxim Integrated Products, Inc.
[5]. Volnei A.Pedroni, Circuit Design with VHDL,MIT
Press, England.
[6]. Douglas L. Perry, VHDL: Programming by Example
4th Edition.
BIOGRAPHIES
Chetan Umadi completed his Bachelor of
Engineering at K.L.S Vishwanath Rao
Deshpande Rural Institute of Technology,
Haliyal. Karnataka India in 2012.He is
Pursuing Master in Technology at
Dr.Ambedkar Institute of Technology,
Bangalore, India. His areas of interest are Digital design and
Embedded System Design.
Dr. G.V. Jayaramaiah completed his
Ph.D. From IIT-Bombay. He has
published around 19 Papers in
international journals. He is working as
Professor and Head of the department of
ECE at
Dr.Ambedkar Institute of
Technology. Bangalore. India. His areas of interest are
Power Electronics, Renewable Energy and Embedded
Systems.
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Volume: 03 Issue: 07 | Jul-2014, Available @ http://www.ijret.org
394