The SCAN Design in each group is treated separately and has stand alone scan chains for every

Group. The final scan chain connections, and the porting the group level scan_in/scan_out to the
Chip level i/os are done manually early in the RTL.
The number of scan chains is limited by the number of scan-ins and scan-outs that can be
accommodated on the chip. Also by considering requirements and limitations of the chip
testers, the scan chain length is fixed to around 5000. The scan in and scan out are shared
between the functional pins.

The scan insertion and the scan stitching is done separately, per Group basis. Top level
integration, top level scan chain connections, and scan I/O direction gating are done early at
RTL level. Group level netlist reading and linking are done while Top level scan synthesis.

1.1.1 Scan length and number of scan chains

Scan chain length and design scanability dominate the ATPG run time and the length of test
vector as well as the production test time. To make a test time as short as possible, two main
points are extremely helpful. One is to have a full scan design and second is to implement as
many scan chains as possible.
Of course, the number of scan chains is limited by the number of scan in and scan out that we
can be accommodated on the chip. The scan in and scan out can be shared between the
functional pins. Also consider requirements and limitations of your chip testers on deciding
the max-scan length and number of chains. In previous project, the scan chain length is
around 5000 and 34 chains.
After identifying the total number of scan chains, we need to allocate chains to each group.

1.1.2 Scan control signals

Two dedicated pins are used for SCAN.
1. SCAN_ENABLE
SCAN_ENABLE is the signal select between Shift Mode (SE = 1) and Capture
Mode (SE = 0).
In the shift mode, all sequential elements are connected in such a way that
they operate as one or more shift registers. The shift chain is used to control
the circuit and observe the result.
In the capture mode, the values stored in the sequential elements during shift
are propagated from Q/QN pin of the scanable sequential elements via
combinational logic to the D pin of the next scan flop. Normally the Scan
enable goes to each and every sequential scan cells to switch between the
shift and capture mode. And also used at the Clock gating cell to get
controllability for the clock during Scan-Shift.

The port level SCAN_ENABLE pin is gated with SCAN_MODE to generate the internal
scan_enable signal which is fed to all the Scan flops in the design. Hence we can share the
same pin in functional mode.

2. SCAN_MODE
SCAN_MODE is the static signal which is tied to HIGH during SCAN. This signal is mainly used for fixing
DFT violations.