EXPERIMENT-4

J-K FLIP-FLOP
1. J K FLIPFLOP
SCHEMATIC:

TIMING DIAGRAM:
DSTM4:1
DSTM2:1
DSTM1:1
DSTM3:1
U1A:Q
U1A:Qbar

0s

2us

4us

6us

8us

10us
Time

12us

14us

16us

18us

20us

TRUTH TABLE:
Q(Before
Pulse)
0
1
0
1
0
1
0
1

Q(After Pulse)

0
0
1
1
0
0
1
1

1
1
0
0
0
0
1
1

0
0
1
1
0
1
1
0

2. J K FLIPFLOP (J=K=1):

Q Bar(After
Pulse)
1
1
0
0
1
0
0
1

ANS-1:

ANS-2:

CONCLUION:
The red line indicates toggling behaviour

3. D FLIPFLOP:
PRESET=1, CLEAR=1

TIMING DIAGRAM:
PRESET:1
CLEAR:1
DATA:1
CLOCK:1
U2A:Q
U2A:Qbar

1
1
0
1
0
1

0s

2.0us

4.0us
Time

6.0us

TRUTH TABLE:
PRESET

CLEAR

DATA

CLOCK

1
0

0
0

OUTPUT
Qbar
1
1

1
1
1

0
0
0

0
0
0
1
1

0
1
0
1

0
1

1
0
0
1
1
1
0
1
CONCLUSION:
The change it the data is detected by the very first
rising edge of the clock pulse
Output is holding the data value
So it behave as a delay as well as counter

PRESET=0, CLEAR=1

TIMING DIAGRAM:
PRESET:1
CLEAR:1
DATA:1
CLOCK:1
U2A:Q
U2A:Qbar

0
1
1
1
1
0

0s

0.5us

1.0us

1.5us

2.0us

2.5us

3.0us
Time

3.5us

4.0us

4.5us

5.0us

TRUTH TABLE:
PRESET

CLEAR

DATA

CLOCK
Q

1
1
0
0
0
1
0
0
0
1
1
0
1
1
1
0
1
1
CONCLUSION:
The output, Q is always 1

1
1
1
1
1
1
1
1
1

OUTPUT
Qbar
0
0
0
0
0
0
0
0
0

when PRESET is 0.

5.5us

6.0us

PRESET=1, CLEAR=0

TIMING DIAGRAM:
PRESET:1
CLEAR:1
DATA:1
CLOCK:1
U2A:Q
U2A:Qbar

1
0
1
1
0
1

0s

0.5us

1.0us

1.5us

2.0us

2.5us

3.0us
Time

3.5us

4.0us

4.5us

5.0us

5.5us

6.0us

TRUTH TABLE:
PRESET

CLEAR

DATA

CLOCK

1
1
0
0
0
1
0
0
0
1
1
0
1
1
1
0
1
1
CONCLUSION:
The output, Q is always 0

PRESET=0, CLEAR=0

0
0
0
0
0
0
0
0
0

OUTPUT
Qbar
1
1
1
1
1
1
1
1
1

when CLEAR is 0.

TIMING DIAGRAM:
PRESET:1
CLEAR:1
CLOCK:1
DATA:1
U2A:Q
U2A:Qbar

0
0
1
1
1
1

0s

0.5us

1.0us

1.5us

2.0us

2.5us

3.0us
Time

3.5us

4.0us

4.5us

5.0us

5.5us

TRUTH TABLE:
PRESET

CLEAR

DATA

CLOCK
Q

OUTPUT
Qbar
1
1
1
1
1
1
1
1
1

1
1
1
0
0
1
0
1
1
0
0
1
0
1
1
1
0
1
1
1
1
1
0
1
1
1
1
CONCLUSION:
The output, Q and Qbar are contradictory to each
other when both PRESET and CLEAR are 0.

6.0us

4. DISCUSSION:
1. Why called D flip flop
D stands for delay. As the output takes the value of the data at the rising
edge and holds it for several clock cycle it behaves as if a delay
2. Need of capacitor between 7 and 14 pin
3. Reason of red line in Pspice simulation in initial stage
4. What happens if J, K or DATA is in phase with CLOCK
5. Why delay is required
Otherwise

6. IC information
7. Internal construction of D and JK flip flop
8. Applications of D and JK flip flop