07081374

This article has been accepted for publication in a future issue of this journal, but has not been
fully edited. Content may change prior to final publication. Citation information: DOI
10.1109/TIE.2015.2420672, IEEE Transactions on Industrial Electronics
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS
Electro-Thermal PSpice Modeling and Simulation of

Power Modules
Angelo Raciti, Senior Member, IEEE, Davide Cristaldi, Giuseppe Greco, Giovanni Vinci, Gaetano Bazzano
conversion are bearing significant investments in terms of

facilities for implementing and qualifying new IPEM
assembling lines in order to draw profit from an expected rise
in market volumes.
Thanks to the advancements in integration techniques of
power devices, with the reduction of active die-sizes, the
design trend of IPEM recent generation moves toward the
reduction of assembly volumes by maintaining, however, the
same power management capabilities. Since contexts like
automotive often involve very adverse environmental
conditions, where the amount of power to be managed is of the
order of tens of kW and temperatures can exceed 100C, the
design of modules able to efficiently and robustly manage
thermal quantities becomes a necessity in order to guarantee
stability and long lifetime to the systems [3], [4].
As already mentioned, the most critical aspect of IPEM
design concerns the management of the heat generated by the
active devices, usually un-packaged power MOSFETs, or
IGBTs and diodes, directly soldered on the internal direct
bonded copper (DBC) substrate (Fig. 1). However, the
proposed modeling methodology is general and does not
depend on the structure of the power module stack or on the
DBC technology.
AbstractIntegrated Power Electronics Modules (IPEMs)

represent an innovative typology of power electronics assemblies
able to guarantee several advantages such as increasing of power
density, better management of the thermal flows and a significant
reduction of the package sizes. Their characteristics make them
suitable for applications like motor drives or power conditioning.
IPEMs usage in emerging fields like hybrid automotive traction
and electric generation from renewable energy sources is
continuously increasing. In this paper, we describe the
implementation of a devised flow to generate the layer-based
electro-thermal PSpice model of an IPEM and the simulation
flow of the model. The proposed modeling methodology allows
reducing an electro-thermal multi-domain problem to an
electrical single one. The general PSpice-like nature of the
proposed model makes it suitable for a wide range of simulation
frameworks where the integration of heterogeneous multi-physics
models could be a difficult task. The outlining of both electrical
and thermal PSpice layers is discussed, and the implementation
into the final model, by the assistance of custom electronic design
automation (EDA) flow, is presented. Besides, we describe the
validation procedure of the proposed approach and the results
are compared with the ones obtained by a commercial finiteelement-based package used as a benchmark. Two simulation
approaches related to specific conversion systems, and related
issues, are presented and discussed.
Keywords Thermal analysis, layered approach, IPEM,

thermal-impedance, MOSFET modeling, discrete power device,
EDA/CAD methodologies.
I.
INTRODUCTION
Integrated Power Electronics Modules (IPEMs) represent a

new class of power electronics assemblies that recently are
drawing interest in the emerging field of applications on
automotive hybrid traction, for their capability to manage
significant amount of power into relatively limited volumes,
also in harsh environmental conditions [1], [2]. Silicon device
manufacturers producing goods in the field of power
Manuscript received November 11, 2014; revised February 18, 2015;
accepted March 10, 2015.
Copyright (c) 2015 IEEE. Personal use of this material is permitted.
However, permission to use this material for any other purposes must be
obtained from the IEEE by sending a request to pubs-permissions@ieee.org.
A. Raciti and D. Cristaldi are with the Department of Electrical, Electronics
and Computer Engineering, University of Catania, 95125 Catania, Italy (email: araciti@dieei.unict.it, dcristaldi@dieei.unict.it).
G. Greco, G. Vinci and G. Bazzano are with STMicroelectronics IMS
R&D,
95121
Catania,
Italy
(e-mail:
giuseppe.greco@st.com;
giovanni.vinci@st.com; gaetano.bazzano@st.com).
Fig. 1. Top view drawing of an integrated power electronics module (3_D_S,

2_D_S and 1_D_S are the AC terminals, while S and D are the DC
terminals).
The design is performed by considering a package that

hosts solid state devices, DBC, and bond wires. A successful
design should take into account some factors like the amount of
managed power, the electrical operating conditions, the kind of
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used heat-sink and the boundary conditions where the IPEM is
going to operate. A wrong design of the IPEM assembly brings
to heat management issues and generates unsuitable
temperature peaks (hotspots) inside the active devices. In cyclic
operating conditions, high variations of the junction
temperatures significantly affect the devices lifetime [5], [6]
with the consequent lack of robustness and reliability for the
whole power system that contains the module.
The availability of a predictive IPEM model able to take
into account both the electrical and thermal behaviors is
important in order to speed-up the design and reduce the
prototyping costs [7].
Most activities related to IPEMs electro-thermal modeling
focus on transient and steady-state thermal analyses of generic
multi-chip power devices, either adopting Finite Element
Approaches (FEAs) [8], [9] or boundary element based
methods (BEMs) [10]-[12]. Past research activities were
mainly addressed to generic assemblies of packaged discretepower devices since IPEMs were not yet well-recognized as
stand-alone modules. Novel modeling approaches, having the
specific purpose to obtain an electro-thermal model of IPEM,
date back to recent years. In such cases some techniques try to
analyze the IPEM physics with the purpose to model each
domain in a separate way [13].
In the modelling activities, the understanding of the thermal
behavior of the device is essential and the extraction of the
thermal impedance matrix is a quite common strategy. Usually
the matrix is extracted either from experimental measurements
[14], [15] or by refined three-dimensional thermal simulations.
Alternative extraction methods based on Finite Difference
Methods (FDM) are quite diffused in literature [15] and some
of them exploit Model Order Reduction (MOR) methods
together with Generalized Minimized Residual (GMRES)
algorithms for solving heat equations [17]. Among the refined
three-dimensional simulation techniques, the numerical
computation approach through Finite Element Methods
(FEMs) is the most diffused [18]. In both cases, the generated
results consist in reduced models of the whole system and
make use of a convolution/de-convolution method as a basic
strategy of the problem resolution. The main limit of the
described approaches relies on the difficulty of using the
derived models, into the form they are finalized, in common
simulation frameworks as the ones usually used by converter
designers. In several cases the above models require the use of
proprietary software or external solvers that, through links with
the electrical simulation platform, perform the thermal
simulation [19].
The approach proposed in [20] aims at reducing the
complexity of the module thermal model. However, its use is
developed within a direct simulation method that poses many
limitations when the time constants of the systems (electrical
and thermal) are quite different, and for this reason its
usefulness is highly questionable. In fact, the example given in
[20] shows that a huge time of seventy hours of simulation (by
using a PC available at that time) is required in order to

simulate two real minutes of working operations. It is also
remarkable that other simplifying assumptions have been made
in order to reduce the burden of the simulation runs, i.e.: (1) the
electrical parameters of the power devices are assumed
constants with reference to the temperature; (2) the
commutations of the switches have ideal behaviors; (3) a
constant simulation step of 1s is used and such a choice is
quite improper (too big) to obtain accurate trajectories of the
electrical switching events, and too small for the needs of the
thermal analysis; (4) finally, a high cooling capacity that could
be useful to shorten the time necessary to reach the steady-state
of the thermal part, it is ineffective in this respect.
In our case, as described in section VII, only 13 hours are
required for the complete PSpice electro-thermal simulation
without any of the mentioned simplifying assumptions of [20].
Furthermore, by performing separate simulation runs for the
thermal and electrical layers, the PSpice package selects the
proper time steps for the electrical part (in the range of fraction
or a few ns), and a more coarse time step for the thermal
analysis, thus achieving the goal of speed-up the simulation
runs while preventing the loss of accuracy.
A thermal model approach based on the Fourier series is
proposed in [21] with modeling analysis given in [22]. Even if
it represents a good way to face the problem of the coupled
electro-thermal simulations, however the accuracy given by
finite-element simulation tools is not achieved.
More discussion on the-state-of-the-art may be found by
interested readers in [23], where the advantages and
drawbacks of the available software packages and
methodologies are recalled. Besides, in [23] the authors try to
overcome the limitations of the-state-of-the-art about the cosimulation of electrical and thermal systems. However, the
proposal, even if fine, is not a general solution since is devoted
to a unique device, in a short-term behavior of a few of
microseconds according to a short-circuit transient. In the case
of IPEM the problem is the modeling of electrical and thermal
systems featuring large different times to reach the steadystate behaviors; this case is not faced or feasible by the
approach of [23].
The methodology described in the present paper allows
overcoming many limitations encountered by using the stateof-the-art techniques. It is an alternative strategy leading to an
electro-thermal circuit model that may directly work in a
standard PSpice-like platform. The proposed strategy allows
overcoming all possible limitations that proprietary model
solutions may pose to provide simulation models suitable for
heterogeneous simulation platforms. As a consequence of the
present approach, neither external links to mathematical
frameworks nor custom solver engines are required at the level
of final users [24]. Moreover, the part of the IPEM model,
which is related to the thermal modeling, is generated through a
customized EDA flow able to derive an equivalent PSpice-like
netlist [25]. Finally, effects on the power losses due to non-

ideal interconnections (parasitic phenomena) are accounted by
including in the implementation of the electric circuit the
specific lumped parameters.
The validation of the proposed approach is demonstrated by
modeling a prototype IPEM rated 600V 75A which
accommodates six power-MOSFET dies. The paper describes
the layer-based strategy that is adopted for generating both the
electrical active-passive layer and the thermal one, linked
together through a self-heating power MOSFET macro-model.
At present, both the accuracy and effectiveness of the
generated model have been verified by using, as a benchmark,
accurate simulation results (obtained by FEM packages)
without comparison with experimental measurements. This
latter activity is in progress and deserves specific papers to
develop in the future. Finally, simulation issues that are related
to two case-of-studies are discussed in order to highlight both
the limits and the advantages arising from the application of the
proposed approach.
II.
The electrical layer takes into account the effects of passive

connections on the power losses mainly by the parasitic
inductances, while the thermal one reproduces the effect of
heat propagation inside the module according to its boundary
conditions. Moreover, the junction temperatures of the active
devices are related to the power dissipated by the whole circuit
and also considering the parameter variations. The two layers
are then linked together by the self-heating macro model of the
power devices, which communicates its power dissipation to
the thermal layer and receives from it the junction temperature
values to be accounted for by the electrical layer.
The thermal layer is synthesized by using a Foster-type RC
circuit having a group of current-controlled current generators
used in order to represent the cross-heating effects. The RC
parameters are automatically retrieved by using a custom
synthesis flow able to process the FEM simulation results and
to extract the whole PSpice netlist of the thermal-part.
The electrical layer is derived by a FEM analysis which
produces as final result a RLC circuit (netlist) containing all
passive contributes due to the bond wires, the ribbons, the
metal paths and the connectors. As it turns out, such RLC
values slightly change with temperature so the model should
consider the variations of these passive parameters with respect
to the temperature. However, in our temperature range the
inductance variations may be neglected if compared to the
more significant variations, due to the temperature, occurring
into the parameters of the active devices. A strong advantage of
the proposed approach consists in the capability of generating
both layers, and the active macro-model, independently being
them unrelated at the modeling stage.
ELECTRICAL AND THERMAL DOMAINS
A. IPEM Three-phase Bridge Topology

Even if an IPEM may host different kinds of electrical
schematic solutions, the ones devoted to motor drive
applications have a three-phase bridge topology and
accommodate either IGBTs or power MOSFET devices
according to the application specifications. While the IGBT
devices need external anti-parallel diodes, the power
MOSFETs use their intrinsic body diodes [26].
B. Abstraction Layers
In order to simplify the generation process of the whole
model, two abstraction layers that are synthesized as PSpice
netlists have been devised for representing, respectively, the
electrical and thermal behaviors (Fig. 2). This approach allows
reducing a multi-domain electrical-thermal problem to a singledomain electrical-thermal one.
C. Mapping of the Domains

As already mentioned, the approach used aims at reducing
the complexity of a multi-domain problem to a single one.
First of all, the objective of the domain reduction requires the
application of the well-known analogy between the thermal
systems and the electrical ones. In this respect, the junction
and the ambient temperatures (Tj and Ta) have been considered
as node voltages, the thermal impedance Zth(t) as an
electrical one, and the power dissipation Pd(t) as a current
source generator. The relationship that ties these quantities for
a single component is:
T j ( t ) Pd ( t ) Z
th
(t ) T a
(1)
while in case of an IPEM, since the mutual impedance should

be taken into consideration, the following matrix equation
holds:
T j1 (t ) Z th11 (t ) Z th1 p (t ) Pd 1 (t ) Ta
(2)

T jp (t ) Z thp1 (t ) Z thpp (t ) Pdp (t ) Ta

Fig. 2. Layered approach adopted for the IPEM modeling.

Key factor of (1) or (2) is the synthesis of the Zth(t)
parameters that may be done by using an automatic custom
EDA flow as it is described in the following sections.
D. Main Advantages of the Proposed Methodology
In synthesis, our electro-thermal model has the following
advantages and novelties with respect to the state-of-the-art:
1. concurrent approaches, that are mentioned in our section
References [9], [13], [15], [22], [23], propose strategies that do
not generate (for power modules) a final electro-thermal
model split in two distinct layers, and implemented in a pure
PSpice format;
2. the PSpice layers are conceived just to allow an easy
implementation of iterative simulations for power modules, as
described in section VII. Iterative simulations are mandatory
in order to account for the parameter variations of the active
devices with the temperature [23], and to allow electrical and
thermal simulations of systems that have time constants that
differ by several orders of magnitude such as the power
modules. Commercial simulation packages may do easily the
same for single devices, but our methodology is the only way
to face IPEM electro-thermal simulations in reasonable time
without excessive (unsuitable) burden of simulation time and
data to be stored;
3. the Foster or Cauer RC circuits are well known in literature
and they are used in order to model the thermal layer in case
of single device. In our work, an alternative electrical topology
(composed by some Foster RC circuits) has been proposed.
The circuit allows the computation of the cross-heating effects
occurring in power modules;
4. the self-heating model of the active device is a pure spice
macro model, unlike other commercial solutions, and it may
work in whatever PSpice compatible environment.
III.
Fig. 3. Equivalent circuit including part of the Q3D extractor tool output of
an IPEM (only parasitic inductances).
equivalent model. The PSpice netlist is prepared by adopting

as model an RC Foster-type circuit (branch) since it fits
sufficiently well with the thermal propagation phenomenon.
The number of branches is related to the number of active
devices within the module, while the number RC pairs (poles)
TABLE I. EXTRACTED INDUCTANCE VALUES.
Inductance values of the schematic in Fig. 3 (nH)
9.22
L8
7.46
L15
2.31
L2
7.93
L9
7.54
L16
32.00
L3
6.71
L10
5.22
L17
31.70
L4
16.38
L11
4.75
L18
32.63
L5
16.64
L12
5.21
L19
24.38
L6
15.65
L13
2.33
L20
18.72
L7
7.54
L14
2.71
L21
11.98
for each branch is related to the accuracy of the curve fitting.

The branch parameter values mainly depend on the module
geometry, on the used material properties, and also on the
boundary conditions of the heat exchange.
ELECTRICAL LAYER
In order to generate the electrical layer, looking to include

the entire passive contributes due to the metal
interconnections, a 3D FEM simulation has been performed by
using the Ansys Q3D Extractor tool [27]. Since the complete
electrical layer of the IPEM contains many RLC parasitic
parameters, our choice has been to simplify the layer itself
without, however, any significant change on the whole
accuracy or impact on the power losses. Accordingly, even if
the FEM tool is able to generate the whole RLC parasitic
parameters, only the inductances reported in Fig. 3 are taken
into account because they play the major role in the envisaged
range of working frequency of the IPEM. The extracted values
of the parasitic inductances for the case-of-study are given in
TABLE I.
IV.
L1
A. Thermal FEM Simulation of an IPEM

In single powered chips, simplified circuit approaches or
more complicated analytical ones may successfully be used for
estimating the junction temperature behavior [23]. In the case
of multiple power source systems as IPEMs, where cross-heat
propagation amongst dies is significant, FEM analyses
represent the unique precise solution. Here, FEM simulations
concerning the thermal analysis are performed by using the
commercial package COMSOL [28]. Firstly, the geometries
are defined and the material properties and boundary
conditions are properly settled-up. These first two steps are
directly derived from the 3D electrical FEM setup, and the
boundary conditions are established according to the cooling
conditions of the real system. Since the setup of the boundary
conditions is fundamental in order to get accurate results in
FEM simulations, in the case under investigation we brought
back the real case cooling condition to an analytic form that
has been associated to a heat transfer coefficient of h=1000
THERMAL LAYER
The generation of the thermal layer is done by using the

results of a series of FEM thermal simulations as source input
data for synthesizing, through an automated topology-building
and curve-fitting process, the PSpice electro-thermal

W/(m2K) by supposing a forced air-convection cooling
mechanism. The top and side surfaces of the IPEM are
considered adiabatic [29]. By using convection cooling, the
exchange of thermal power Q between the fins of the heat-sink
and the air is:
(3)
Q hA ( T s T f )
where Tjl(t) is the junction temperature of the device l when

the die m is heated, Ta is the ambient temperature and Pdm is
the power dissipation into the die m. The ratio Tj(t) over Pd is
called thermal impedance and it is a time-dependent quantity.
Despite its name, it does not correspond to the concept of the
electrical impedance of the equivalent electrical network, but it
represents the time variation of the temperature per watt of a
heated element.
Once the Zth curves are retrieved, an automated fitting
process is used to determine all the RC coefficients of the
envisaged equivalent PSpice circuits. Since at this stage we are
not interested in retrieving the temperatures on all the IPEM
stack points but only at the junction nodes, a Foster-type
electrical equivalent network that consists of four RC parallel
pairs connected in series (Fig. 5) is used to represent the
thermal impedance. Through this electrical network it is
possible to model the thermal behavior only at the junction
nodes, but there is no correlation between the RC pairs and the
physical layers of the module. Equation (6) is used as a model
of the Foster-type circuit of Fig. 5.
where A is the surface that is involved in the heat exchange, Ts

is its surface temperature and Tf is the fluid temperature.
Moreover, thermal conduction is represented by the heat
conduction equation:
T
c
k 2T q
(4)
t
where, for each material, c is the specific heat capacity, is the
density, k is the thermal conductivity (it is assumed to be not
temperature dependent in our problem), T is the field
temperature and q is the heat generation.
Several FEM simulations have been progressively
performed by applying a set of input power excitations to the
dies in order to generate heat within the IPEM and, hence, to
calculate the thermal response on each active device (Fig. 4).
The input signals are applied for a time-frame of 80s. Such a
time lasts enough to allow the electro-thermal system to reach
the steady state behavior, in accordance with the geometry and
the boundary conditions applied, and in particular with special
reference to the applied heat transfer coefficient h that
corresponds to a quite strong cooling system acting on the heatsink.
Z th (t ) Ri (1 e
t
Ri C i
(6)
i 1
The circuit in Fig. 5, and the analytical representation (6),

considers a number of poles equal to four to represent the
transient under investigation. This equation is chosen as the
objective function within the fitting procedure used for
retrieving the RC coefficient values, and it is better discussed
in section VI.
Fig. 5. Foster-type network configuration in the electro-thermal analogy (PI,

TV, RthR, CthC).
C. Model Generation of the Thermal Layer

With reference to Fig. 6, which represent the model of a
power module containing six dies, the PSpice network of the
thermal layer has been generated by assuming that the junction
temperature of a generic die may be calculated as the sum of
contributions due to the self-heating temperature, the ambient
one (Ta), and the coupling effects due to the heat generation in
other dies. The contribution due to a different die, e.g. die
number 2 on die number 1, is evaluated by the flow of the
current Id2, that in the thermal equivalence is the power Pd2,
through a current-controlled current-source (cccs) (Fig. 6).
The Id2 effect on the die number 1, T12, is accounted for by the
specific 4-th order Foster-type network Zth,12(t) that is supplied
by the current-controlled current-source. Each cccs reads the
current on the main branch and force it, with an unitary
amplification factor, on mutual-heating branches. At the end,
Fig. 4. Physical drawing of the IPEM in the frame of COMSOL package after a
power excitation on die 1.
B. Curve Fitting of the Thermal Impedances

The thermal simulation runs, which are described in the
previous sub-heading A, produce a set of curves representing
the thermal transients of the device junctions of the six dies for
the considered frame-time. Thermal impedances, for self and
mutual heating, are directly derived by using (5):
Z thJA,lm (t )
T jl (t ) Ta
Pdm
(5)
Fig. 6. Block schematic of the thermal model of an IPEM.
the final temperature (equivalent voltage) on die 1 is given by

several current contributes flowing on RC branches: selfheating contribute (Id1 on Zth11), mutual-heating contribute
(Id12, Id13 Id16 on Zth12, Zth13.. Zth16) and ambient temperature
contribute Ta. All these contributions are then summed by an
adder which provided the Tj1 value expressed in terms of
voltage:
Tj1 = T11+ T12+ T13+ T14+ T15+ T16+ Ta
V.
(7)
THERMAL LAYER SYNTHESIS THROUGH A DEDICATED

EDA FLOW
Modeling the thermal layer is a quite long process because

it implies both the implementation of the electro-thermal
equivalent PSpice circuit and the need of fitting several curves
produced by FEM simulations.
A. Synthesis Process
Fig. 7. Outline of the whole modeling flow based on TLSynth.
In order to speed-up this procedure, and thus reduce

transcription errors in compiling the final netlist, the process is
computerized by implementing an EDA synthesis flow able to
generate the final PSpice thermal-layer. In this way, a low
impact of data transfer from different software platforms is
obtained. The EDA tool, which is written in PERL language
and is named TLSynth (Thermal-Layer Synthesizer), is able to
take as an input the waveforms that are stored in a computer
directory and interfaces itself with the MATLAB framework.
The choice of PERL as programming language is due to its
multi-platform compatibility with different Operating
Systems.
An outline of the whole EDA modeling flow is shown in
Fig. 7. The flow starts with the generation of FEM simulations
performed by the use of the COMSOL package. Once the Zij
data are extracted, the results are stored in a file system

directory whose path has to be set inside the TLSynth
Graphical User Interface shown in Fig. 8. Hence, a destination
file path is specified and the user must set both the number of
active devices and the number of Foster poles that will be
considered into the final network. By clicking the start button,
the tool is able to interface itself with the MATLAB
framework, and its optimization tool is exploited in order to
calculate the RC coefficients of the final PSpice netlist.
It is important to highlight that the accuracy of the final
model depends on the fine quality of the fitting procedure. To
this aim a check by TLSynth is done after each MATLAB call
by evaluating the RSQUARE factor calculated by the
optimization procedure. The synthesis process generates a
Fig. 10. Thermal model sub-circuit having six input current ports (equivalent
power), an input voltage port (T ambient) and six output voltages ports
(junction temperature).
The assumption in this case is that the dies 1-3-5 are

simultaneously powered while the dies 2-4-6 are not working.
Fig. 8. Details of the TLSynth Graphical User Interface.
thermal sub-circuit model having n input current ports

(equivalent power), an input voltage port (Ta ambient) and n
output voltages ports (junction temperature).
For the sake of a better understanding, a very simple
example is shown in Fig. 9. The synthesized schematic refers
to the case of two active power devices.
Fig. 11. Comparison between the junction temperatures on dies 1 and 4

simulated with COMSOL and the ones retrieved by the synthetized electrothermal model by assuming that dies 1-3-5 are simultaneously powered and
dies 2-4-6 are not working.
VI.
LAYERS INTEGRATION THROUGH A SELF-HEATING

POWER MOSFET MODEL
As already mentioned in the previous sections, the electrical

layer and the thermal layer communicate through a self-heating
power MOSFET macro model. Instead of following a pure
physical approach, such a model implementation is based on a
behavioral modeling strategy that is commonly used for
modeling single discrete power devices [30], [31]. The
technique has been extended to the case of more power devices
that are thermally interacting.
Fig. 9. Thermal layer schematic in the case of two active power devices.
B. Model Validation
In order to verify the accuracy and effectiveness of such a
process to obtain a simplified thermal model, a test case has
been setup as a workbench on a PSpice simulation
environment. First of all a circuit schematic is created by
importing the set of generated thermal-layer netlist, as shown
in Fig. 10. Comparisons between the FEM data deriving from
COMSOL simulations and PSpice simulated results are done
for a generic power step combination input.
As a result, the comparison shows a good matching
between the FEM and the TLSynth model waveforms has. Fig.
11 shows the fine agreement between the junction
temperatures on dies 1 and 4 being the simulations performed
by COMSOL and by the synthesized electro-thermal model.
A. Electro-Thermal Model of a Single Discrete Power Device

Single discrete power devices may be modeled by adopting
an implementation approach that consists in linking some
behavioral blocks representing device parameters (Fig. 12a)
with a junction temperature variable (T_JUNCTION) whose
value is retrieved by a feedback loop with a RC thermal
impedance network usually included in the macro-model (Fig.
12b). This approach does not take into account cross-heating
M1
a)
b)
Fig. 12. Self-heating power MOSFET macro model: a) model core, b) RC equivalent thermal-impedance network.
effect phenomena since no other heating sources are considered

beside the die. This self-heating modeling strategy results to be
consistent with the expected results.
VII. SIMULATION APPROACHES AND SIMULATION RESULTS

Since electrical time constants are lower than the thermal
ones in case of IPEMs, a preliminary evaluation between the
dynamic behaviors of the thermal and the electrical layers
should be done before deciding what kind of simulation
approach is better to adopt. Even if several kinds of
methodologies may be outlined to perform the electro-thermal
simulation, usually, according to the different values of the
time constants characterizing the two layers, a direct or an
iterative method may be the choice for the simulation strategy
to be adopted.
B. Electro-Thermal Model of Several Discrete Power Devices

Working within an IPEM
When several close heat-generating dies have to be
modeled, cross-heating effects must be considered and the
described single-source approach is not sufficient for
addressing the multi-die problem since the presented thermalimpedance network is only able to take into account selfheating effect. An extension of this model is implemented by
substituting the RC thermal-impedance network (Fig. 12b)
with the thermal layer described in this work through which the
six-die macro-models thermally interact with each other.
A. Direct and Iterative Approaches

A direct method may be adopted if the time constants
characterizing the thermal and electrical sub-systems are quite
comparable [32]. Direct method refers to an approach where
the two layers are strictly connected through a real-time feedback. A change of the electrical quantities instantly implies the
temperature adjustments of the temperature dependent
quantities, and so forth. The IPEM case represents a typical
example where the use of this approach, even if technically
possible, it is not advisable because the behavior of the thermal
sub-system is estimated in the range of minutes (that may go up
to tents of minutes) while the electrical part reaches the fully
steady-state operating conditions in the order of hundreds of
milliseconds.
Whenever the time constants of the two layers are quite
different then the iterative method represents a mandatory
alternative to the direct one, since in this case the simulation
burden would result onerous to be performed in terms of both
time and hardware resource requirements to collect the huge
amount of data. Iterative method, whose flow is shown in Fig.
13, implies a segregation of the electrical and thermal
C. Model Core
Since the active devices within the IPEM under
investigation are power MOSFETs, a PSpice macro-model core
is implemented starting from a standard basic level-3 MOSFET
model (M1). The equations implemented in the macro model
are conceived so that the junction temperature results as a
direct effect of power dissipation. The developed macro-model
core is able to correlate some blocks describing the variations
of basic parameters like Vth, Rds, on or BVdss with the temperature
nodes retrieved through the thermal layer T-junction nodes.
The adopted behavioral approach has been preferred to a
pure physical one because it brings advantages to the final
PSpice simulations by reducing the computation time and often
also by reducing the number of issues that are related to the
convergence of the simulation runs, especially when the system
features several instances as in the case of IPEM systems.
Fig. 13. Layer Based Electro-Thermal Simulation Approach for Integrated Power Electronic Modules.
simulations. In other words, the two analyses are performed in

separate ways and, iteratively, power losses and temperatures
values are exchanged between the layers [23] until the
maximum difference of the junction temperature (
, ),
related to the simulation step n, is below a prefixed threshold
(convergence condition). Power losses may be retrieved either
by using multiplier blocks located on the electrical layer, where
instantaneous voltages and currents across the discrete power
devices are detected and processed, or by using pre-compiled
look-up tables containing the power losses values as function
of different load conditions, operating parameters,
temperatures, etc. [32], [33]. Even if the iterative method
appears less compact than the direct one, and may pose some
issues about the convergence, it often guarantees a viable use
of the hardware resources and a reduction of the whole
simulation time.
frequency, Ts=1/fs. In this case it is immediate to calculate

PAVG because p(t) is the same in each period, as shown in Fig.
14.
On the contrary, in the case of inverter applications (Fig. 15),
retrieving PAVG is not a simple immediate process. This
happens because, within a period T of the fundamental, each
switching cycle (turn-on, conduction, turn-off) occurs at
different values of current (see the blue circle on ITA+, Fig. 15).
Consequently, the average power losses that occur at the x
switching cycle, PAVG,x, is different from the one that occur at
the y switching cycle, PAVG,y. In conclusion, the active power
dissipated during a period T may be obtained by averaging the
powers calculated for each of the switching cycles.
The iterative simulation results referred to the mentioned
inverter case are given in TABLE II where power losses and
junction temperature values, for each die during each
simulation step, are included. The last column of the table
reports the quantity
. calculated as difference between
the simulated junction temperature peak at step n and step n-1.
B. Iterative Method Simulation Results

In the iterative method, the values of the average power
losses (PAVG) are retrieved from the electrical layer, and are
provided as equivalent current sources to the thermal layer in
order to get the temperatures on the junction nodes. The use of
the average power values makes the simulation approach
certainly faster but it does not allow observing possible
temperature peaks that may occur, during the thermal
transient, near to the heat source position.
The calculation of the power losses needs different
approaches in relation to the kind of power converter to be
analyzed. For example, in the case of a DC-DC converters that
is operating at a constant power load, it is possible to outline a
repetitive waveform for the power losses into the switching
device having a period given by the inverse of the switching
Fig. 14. Repetitive instantaneous power losses for each period Ts in the
switching device.
In the case of study, the iteration procedure is stopped after

four simulation steps since the convergence criterion, defined
as:
, ,,
,,
< 1
(8)
Fig. 15. Inverter leg with a sinusoidal modulated current at low frequency and high switching frequency. Power losses into the devices have to be calculated
accounting for the variable current (turn on, turn off and on-state conditions) and for variable duty cycles.
easily used in whatever kind of PSpice-like simulation

framework. This approach overcomes many limitations of most
concurrent approaches where the co-simulation between the
two domains is performed through links between the electrical
simulation environment and external mathematical solvers.
A custom EDA flow has been developed and used to
generate the final thermal PSpice circuit through an automated
processing of FEM data. Moreover, we have done the
comparison between the FEM simulations and the results of the
new model verifying the good matching between the
simulation data. Finally, we presented a simulation strategy and
related flow with the aim to simulate power modules. Such
systems have a large difference between the time-constants of
the electric and thermal domains, thus they require an iterative
approach in order to get a good trade-off between simulation
times and accuracies.
Future validation activities by comparison of simulated
results and test measurements are still in progress, and, being
the implications of this work quite extensive, the results will be
presented in follow-ups of the present work.
TABLE II. POWER LOSSES AND JUNCTION TEMPERATURES

DURING SIMULATION STEPS.
Die
Simulation step
#1
#2
#3
#4
#5
#6
[C]
a (electrical) 123.3 123.3 123.3 123.3 123.3 123.3

Pd [W]
#1
b (thermal) 82.4 86.4 83.4 81.8 85.2 81.8
Tj [C]
[on die#2]
a (electrical) 139.1 140.3 139.3 139.0 139.9 139.0

Pd [W]
b (thermal) 89.8 94.8 91.1 89.0 93.2 89.1
Tj [C]
[on die#2]
a (electrical) 141.2 142.5 141.5 140.9 142.0 141.0

Pd [W]
b (thermal) 90.8 95.9 92.1 89.9 94.2 90.1
Tj [C]
[on die#2]
a (electrical) 141.4 142.9 141.7 141.1 142.3 141.3

Pd [W]
#4
b (thermal) 90.9 96.0 92.2 90.0 94.4 90.2
Tj [C]
[on die#5]
#2
#3
61.4
8.4
1.1
0.2
is met. It is worth to mention that a very complex system

which had not chance to be simulated in reasonable time with
a direct method approach, has instead been simulated, with the
some computational resources, by an iterative strategy in less
than three hours.
ACKNOWLEDGMENTS
This research is supported by the European Commission's
Information and Communication Technologies Program,
under SMAC project contract No. 288827, call FP7-ICT2011-7.
VIII. CONCLUSIONS
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Angelo Raciti (M'93-SM98) received the Laurea

degree (summa cum laude) in electrical engineering
from the University of Catania, Catania, Italy, in
1975.
From 1976 to 1981, he was an Engineer and a
Manager with Intar Spa, Genoa, Italy, where he was
involved in the development of advanced equipment
for industrial and ship applications, with special
responsibility in power electronics design. In 1981,
he joined the Department of Electrical Electronic
and Computer Engineering (DIEEI), University of
Catania, where he is currently a Full Professor and teaches courses in Power
Electronics and Semiconductor Power Devices. His teaching and research
interests include electrical machines, semiconductor power devices, power
electronics, and electrical drives. He founded the Applied Research Industrial
Electronics Laboratory, DIEEI University of Catania, which carries out
studies on power electronics and power devices in the framework of funded
European and national research projects. He is the author of more than 200
technical papers.
Prof. Raciti is a Senior Member of the Italian Association of Electrical and
Electronics Engineer (AEIT). He also serves as a Member of several
Committee of IEEE Societies, and member of the Steering and Technical
Committees of international conferences.
Davide Cristaldi received the M.S. (Laurea) degree
in Electronics Engineering from the University of
Catania, Catania (Italy) in 2009.
He works as research fellow at the University of
Catania since 2012. His research activities regard
power electronics and modeling. The main topics
concern electro-thermal, thermo-mechanical analysis
and model generation, by means of circuit
simulators and FEMs software, of power devices
(IGBTs, MOSFETs, diodes) and integrated power
electronics modules; electro-thermal analysis of
converters and devices in normal and faulted working conditions.
Mr. Cristaldi is reviewer of some IEEE-related conference and journal
papers.
11

Giuseppe Greco was born in Taormina, Italy, in
1971. He graduated in Electronics Engineering at the
University of Catania, Italy, in 1998.
In 1999, he joined the R&D - CAD and Design
Solutions Group in STMicroelectronics, Catania,
Italy. Since 2002 he is responsible of the IC Analog
Back-End Team and in 2010 he has been elected
Member of STMicroelectronics Technical Staff. His
main activities concerns both design support and
development of design kits, EDA tools and design
flows. Other interests are the development of custom
software and methodologies, aimed at analyzing thermal effect of discrete
power devices, technology porting of designs and electromagnetic analysis of
layout structures.
Mr. Greco is author and coauthor of patents, several papers published in
international journals and specialized newspapers. He has also participated to
international conferences and at present he is involved as researcher in several
funded projects.
Giovanni Vinci graduated in Computer Science at

the University of Catania, Italy, in 1998.
In 1999, he joined STMicroelectronics, Catania,
Italy, in the R&D - CAM and Automation Group as
CAM Engineer. In 2002 he was responsible for
Automation Application Architecture Activity and in
2005 became responsible for the Automation
Architecture & Support Team. In 1997 he moved to
R&D - CAD and Design Solution Group in the Data
Management, Software Maintenance and grid Team.
Since 2011 he is working in the IC Analog Back-End Team as CAD expert of
Electromagnetic Simulations Tools & Methodologies. His main activities
concern the modeling and analysis through simulations of passive structures
for RF and power electronics applications.
Mr. Vinci is coauthor of several papers published in international
conference proceedings.
Gaetano Bazzano received the degree in electronics

engineering from the University of Catania, Catania,
Italy, in 1998.
From 1999 to 2000, he was with A.T.I.B.
Electronics, Brescia, Italy, where he was responsible
for the research and optimization of high frequency
battery charger of the forklift design. Since 2000,
he has been with the Power Transistor Division,
STMicroelectronics, Catania, Italy, where he has
been involved in the design of several ICs. His
current research interests include characterization
and physics-based modeling of active and passive devices for switching
applications.
Mr. Bazzano has been the author and coauthor of several articles published
in international journals and specialized newspapers. He has also been invited
to international conferences in order to present results of his research.
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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS

Electro-Thermal PSpice Modeling and Simulation of

conversion are bearing significant investments in terms of

AbstractIntegrated Power Electronics Modules (IPEMs)

Keywords Thermal analysis, layered approach, IPEM,

Integrated Power Electronics Modules (IPEMs) represent a

Fig. 1. Top view drawing of an integrated power electronics module (3_D_S,

The design is performed by considering a package that

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS

using a PC available at that time) is required in order to

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS

The electrical layer takes into account the effects of passive

ELECTRICAL AND THERMAL DOMAINS

A. IPEM Three-phase Bridge Topology

C. Mapping of the Domains

while in case of an IPEM, since the mutual impedance should

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS

equivalent model. The PSpice netlist is prepared by adopting

for each branch is related to the accuracy of the curve fitting.

In order to generate the electrical layer, looking to include

A. Thermal FEM Simulation of an IPEM

The generation of the thermal layer is done by using the

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS

where Tjl(t) is the junction temperature of the device l when

where A is the surface that is involved in the heat exchange, Ts

The circuit in Fig. 5, and the analytical representation (6),

Fig. 5. Foster-type network configuration in the electro-thermal analogy (PI,

C. Model Generation of the Thermal Layer

B. Curve Fitting of the Thermal Impedances

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS

Fig. 6. Block schematic of the thermal model of an IPEM.

the final temperature (equivalent voltage) on die 1 is given by

THERMAL LAYER SYNTHESIS THROUGH A DEDICATED

Modeling the thermal layer is a quite long process because

Fig. 7. Outline of the whole modeling flow based on TLSynth.

In order to speed-up this procedure, and thus reduce

data are extracted, the results are stored in a file system

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS

The assumption in this case is that the dies 1-3-5 are

Fig. 8. Details of the TLSynth Graphical User Interface.

thermal sub-circuit model having n input current ports

Fig. 11. Comparison between the junction temperatures on dies 1 and 4

LAYERS INTEGRATION THROUGH A SELF-HEATING

As already mentioned in the previous sections, the electrical

A. Electro-Thermal Model of a Single Discrete Power Device

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effect phenomena since no other heating sources are considered

VII. SIMULATION APPROACHES AND SIMULATION RESULTS

B. Electro-Thermal Model of Several Discrete Power Devices

A. Direct and Iterative Approaches

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simulations. In other words, the two analyses are performed in

frequency, Ts=1/fs. In this case it is immediate to calculate

B. Iterative Method Simulation Results

In the case of study, the iteration procedure is stopped after

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS

easily used in whatever kind of PSpice-like simulation

TABLE II. POWER LOSSES AND JUNCTION TEMPERATURES

a (electrical) 123.3 123.3 123.3 123.3 123.3 123.3

a (electrical) 139.1 140.3 139.3 139.0 139.9 139.0

a (electrical) 141.2 142.5 141.5 140.9 142.0 141.0

a (electrical) 141.4 142.9 141.7 141.1 142.3 141.3

is met. It is worth to mention that a very complex system