Analysis of a New Fifth-Order Boost Converter

Mummadi Veerachary
Dept. of Electrical Engineering, IIT Delhi, New Delhi, India
E-mail: mvchary@ee.iitd.ac.in
Abstract In this paper a new boost fifth-order point of load dcdc converter is proposed. A digital controller is then designed to
ensure load voltage regulation against expected disturbances.
The proposed converter is capable of giving a higher voltage
gain in comparison to other fourth and fifth-order boost
topologies reported in literature. Through steady-state analysis
various design expressions for the energy storage elements are
obtained. Discrete-time models of the converter are derived,
which are then used in digital controller design. A 25 Watt, 12 to
48 V, 100 kHz prototype converter is considered for simulation
and experimentation. Simulations and measurements are in
close agreement and thus verified the effectiveness of the
proposed converter.
keywords: Power Electronics, DC-DC Converters, High Voltage
Gain, Digital Controller.

I. INTRODUCTION
The need of power conversion at high frequency in dc-dc
distribution is spreading in almost all areas. Increasing the
power densities of the point of load converters is the
challenging task in the area of switch-mode power
conversion. The possible options are: (i) avoiding the use of
transformers wherever isolation is not required, (ii)
minimizing the size of the magnetic elements and (iii)
mitigating the electromagnetic interference (EMI) impact. It
is well-known that high frequency switching results in light
weight units of a smaller size with high power densities.
Variety of power conversion topologies has been reported in
the literature to meet verity of load needs, and these are
classified as: (i) buck, (ii) boost, and (iii) buck-boost and their
derivative topologies. These converters have applications in
several different areas such as: (i) powering compact lowpower integrated circuits, (ii) power supplies for automotive
electronics, (iii) telecommunication systems, space vehicles,
defence equipment, and (iv) internet/ WAN services, etc.
It is well documented that boosting dc-dc converters, and
their derivative circuits have a wide range of applications in
front-end power processing systems. However, the
conventional boost dc-dc converter operates in an extreme
duty ratio of operation to realize larger voltage gains.
Moreover, this voltage gain is achieved at the cost of reduced
efficiency of the converter at heavy loads. Quadratic, coupled
inductor based boost converters have been reported in the
literature [1]-[5] to overcome some of these limitations.
However, device current/ voltage stress is still limiting factor.
Variety of higher-order topologies were evolved to realize
higher-gains together with improved circuit performance. The
basis for these evolutions is suitable mapping and merging
different circuit combinations into a single circuit. Although
these derived circuits may be meeting voltage gain
requirement, but it is at the expense of lower efficiency,

which is on account of a greater number of switching devices.

Better steady-state gain, together with improved dynamic
performance is the main concern.
A fourth-order boost converter for load voltage regulation
purposes has been reported in ref[6], and a fifth-order boost
converter, and a robust digital controller design has also been
presented [7]-[10]. Although, these topologies are capable of
meeting the load voltage requirement, their boosting
capability in the low duty ratio range is limited, whilst the
high duty ratio operation yields lower efficiency. The above
mentioned topologies are belonged to higher-order family but
yields lower voltage gains. To alleviate some of these shortcomings a new fifth-order boost converter (NFBC) is
proposed in this paper. The discrete-time model formulation
methodology reported in ref[11]-[12] is employed for
analysis of the closed-loop converter system.

L1 , r1

L2 , r2

C1 , rc1

C2 , rc 2
C3 , rc3

(a) Proposed new fifth-order boost converter

L1 , r1

L2 , r2

C1 , rc1

C2 , rc 2
C3 , rc3

(b) Circuit diagram for mode-1 operation

L1 , r1

L2 , r2

C1 , rc1

C2 , rc 2
C3 , rc3

(c) Circuit diagram for mode-2 operation

978-1-4799-1823-2/15/$31.00 2015 IEEE

A. Steady-state Analysis
A steady-state time-domain analysis performed here to
know the dynamic and steady-state performance of the
proposed NFBC. Voltage boosting expression of the
converter is obtained, application of volt-sec balance to the
inductive elements, and the corresponding relationships are:
Switch-ON period
Switch-OFF period
vL = Vg
vL = (Vg + vc12 )

vC1 = vc 2

vC = 2vc1

Applying volt-sec to the inductor - L:

(Vg )D + (Vg + vc1 )(1-D)= 0

(1)

=> vc1 = Vg (1-D)

(d) Steady-state waveforms
Fig. 1. Circuit diagrams of proposed Fifth-Order Boost Converter.

II.

MODELING AND ANALYSIS OF THE NEW FIFTH-ORDER

BOOST CONVERTER

A new fifth-order boost converter (NFBC) proposed in this

paper is shown in Fig. 1. In comparison to the conventional
boost converter, it has three additional diodes (D1, D2 and
D3), two capacitances (C2 and C4) and one additional
inductor. Although the number of energy storage components
in the proposed converter is the same as in the fifth-order
converter reported in ref [8], these two circuits are entirely
different both from the performance and structure point of
view. On account of the structural difference, this circuit
exhibits important features such as: (i) higher voltage gain
than the other comparable fifth-order topologies, (ii) capable
of giving a higher voltage gain at moderate at the duty ratio,
and (iii) simple gate driving requirement on account of
ground reference single-switch. A detailed comparison of the
various stress factors of the proposed converter with the fifthorder boost converters [7] and NFOBC [8], is compiled for
identical source and loading conditions and listed in Table-I.
Time-domain analysis has been carried out for the converters
mentioned above and then various analytical expressions,
ripple current, capacitor voltage stress, etc., are derived and
listed in Table II.
While boosting from low voltage source to high voltage
load the current drawn from the source side is high.
Therefore, the inductor current is a continuous and hence
continuous current mode (CCM) of operation is discussed
here. In mode-1 S, D1, D2 and D3 conducts, while the diode
D4 conducts in mode-2, and the respective circuits are shown
in Figs. 1b and 1c. In the first mode the energy storage
elements L1, L2, C1, C2 connected in parallel across the dc
source while they are in series in the next mode of operation.
A mathematical analysis of NFBC is established in this
section under the following assumptions: (a) switching
devices are ideal, (b) the converter time constant is very high
in comparison to the switching time period, and (c) the total
delay in the control loop is small.

Using capacitor steady-state charging equation together eqn.

(1) results in the following voltage gain expression:
v0 ( 3 - D )
(2)
=
Vg (1- D )
The energy storage elements design equations are established
through a simple time-domain steady-state analysis, along
similar lines reported in ref[6]-[7], and the corresponding
equations are tabulated in Table III.
TABLE -I. COMPARISON OF NFBC COMPONENT STRESS OVER THE FOURTH
AND FIFTH-ORDER BOOST CONVERTERS

Quantity

NFBC

Voltage
Gain

NFOBC

(3 D)
(1 D)

(2 D)
(1 D)

SPVS
SPCS
DPCS

Low
Little high
Little high

ISCR
LSCPCS

Little high
Almost
identical

High
High
Almost
identical
Negligible
Almost
identical

Fifth-Order
Boost Conv.
(1+ D)
(1 D)
High
Medium
High
Medium
Almost
identical

TABLE -II. ANALYTICAL RIPPLE EXPRESSION OF NFBC, NFOBC AND

FIFTH-ORDER BOOST CONVERTERS

Quantity
Voltage
Gain
ISCR

SPVS
CVS

NFBC

(2 D)
(1 D)

Fifth-Order
Boost Conv.
(1+ D)
(1 D)

2Vg D

(Vg vc2 v0)D

Vg D

Lf s

L1 fs

L1 f s

(3 D)
(1 D)


NFOBC

Vg

Vg

Vg

(1 D)

(1 D)

(1 D)

Vg
(1 D)

V0
(2 D)

V0
(1+ D)

SPVS: Switch peak voltage stress, SPCS: Switch peak

current stress, DPCS: Diode peak current stress, ISCR:
Input source current ripple, LSCPCS: Load side capacitor
peak current stress, CVS: Capacitor voltage stress.

TABLE III. DESIGN EQUATIONS OF NFBC

vg

L1 > (Vg vc3 v0 ) D ( f s i1 )

iload

L2 > Vg D ( f s i2 )
C1 > [(2 D) Vg ] [(1 D) Rf s vc1 ]

v ref

C3 > [(1 D) v0 D] [8 L2 (2 D ) f vc 3 ]

v 0

C2 > [(2 D) Vg ] [ Rf s vc 2 ]
B. Discrete-Time Model of the Converter
The NFBC operating modes are shown in Fig. 1, and for
each mode of operation the state-space model is given by:

[ x] = Aj [ x] + Bj [u]
[ y] = E j [ x]

TABLE IV. Z-DOMAIN SMALL-SIGNAL MODEL EQUATIONS

(3)

t j < t < t( j +1)

(re + ra )
(r1 + re + ra )

L1
L1

(re + ra )
(r + r + r )
2 e a

L
L2
2

rc 2
rc 2
[ A1 ] = r C
r34C1
34 1

rc1
rc1

r
C
r
34
2
34 C2

1
1

a
C
a
C2

2
0

rc 2
r34 L1

rc1
r34 L1

rc 2
r34 L2

rc1
r34 L2

1
r34C1

1
r34C1

1
r34C2

1
r34C2

(rar 1)
L1

(1 rar )
L2

0 ;

aRC2

T
0 ] ; E1 = [1/ a 1/ a 0 0 (1-1/aR)]
E 2 = [ ra ra 0 0 (1-rar )]

a = ( R + rc3 ) / R, re1 = [rc1rc2 (rc1 + rc 2 )], ra = rc 3 a

( r1 + rc 2 + ra )

L1

( rc 2 + ra )

L2

0
[ A1 ] =

C2

aC 2

( rc 2 + ra )
L1

Transfer Function
Control -to- Output

where [Aj] is the state matrix, [Bj] the input matrix, [Ej] the
output matrix, [x] the state vector, [y] the output vector, and
[u] is the forcing function vector.

B1 = B 2 = [1 L1

Fig. 2. Block diagram of digital controlled NFBC.

1
L1

1
L2

1
L2

1
C1

1
C1

1
C2

1
C2

1
aC 2

( r2 + rc1 + rc 2 + ra )
L2

( rar 1)
L1

(1 rar ) (4)
L2

0 ;

aRC 2

Formula
v 0 ( z ) d ( z ) = E ( z - ) -1

Audiosusceptibility

v 0 ( z ) v g ( z ) = E ( z - ) - 1 + F

Output Impedance

v 0 ( z )

Input Admittance

ii n ( z ) v g ( z ) = P [ ( z I - ) - 1 ]

i0 ( z ) = [ E ( z I - ) - 1 + J ]

III. DIGITAL CONTROLLER DESIGN

Digital controller design methods were reported in
literature [5]-[13], which are based on s-domain as well as the
z-domain. Discrete-time models are more accurate than the
models obtained from s -to- z-transformation. In view of
better model accuracy here a z-domain based design is
employed. A block-diagram of the closed-loop controlled
NFBC is shown in Fig. 2. Here, loopgain is formulated
consisting of control-to-output and controller transfer
functions and then used in Matlab [13] for design purpose.
Through built-in SISOTOOL [13] the digital controller polezero locations are fixed in order to ensure closed-loop system
stability. The final resulting controller, detailed step-by-step
design methodology is discussed [8], ensures the desired
relative stability margins to the closed-loop converter system,
which are: gain margin (GM)> 6 dB, phase margin (PM) is
[45 ~ 75] and sufficient bandwidth.
TABLE V. NFBC PARAMETERS

Parameter

Value

The discrete-time modelling, as reported in refs [11] and

[13] has been used here to establish various small-signal ztransfer functions and the corresponding model is:

Vg

12 V

Vo

48 V

x NTs = x (N -1)Ts +d (N -1)Ts

L1/r1

100 H/ 0.01

L2/r2

100 H/ 0.012

C1/rc1

47 F/ 0.40

C2/rc2

47 F/ 0.42

(5)

where = e A1 ( DTs td )12 ; = e A1 ( DTs td )2 , 1 = eAt1 d ,

2 = eA2 D2Ts , = [( A1 - A2 ) X + ( B1 - B2 )Vg ]. Various smallsignal z-transfer functions can easily be obtained from this
model and the transfer functions expressions [7] used are
listed in Table IV.

C3/rc3

96 F/ 0.1

75

fs

100 kHz

feature the following simulation test condition results are

shown in Figs. 6 and 7 for step load perturbation in (a) source
voltage (Vg : 18 12 18 V), and (b) load resistance (R:
150 75 150 ). Although the load voltage exhibits
overshoot and undershoot during dynamic conditions but
ensures regulation.

Fig. 3. Steady-state boosting feature of NFBC.

Fig. 5. Startup response of NFBC.

Fig. 4. Simulated steady-state waveforms.

IV. RESULTS AND DISCUSSIONS

To validate the design methodology, simulation studies
have been made in PSIM [14] by considering a 30 W, 12 to
48 V NFBC. Initially, the steady-state boosting features are
verified at different duty ratio's and the variation shown in
Fig. 3 is in agreement with the voltage gain expression given
by eqn. 2. The boosting feature of this converter is also
compared with other fifth-order topologies mentioned above
in Table I. This comparison clearly indicates that the
additional boosting of about 1.5 times the NFOBC topology
reported in ref[8]. Furthermore, this converter exhibits better
voltage boosting feature together with a lower duty ratio of
operation. Simulated steady-state waveforms of the converter
for nominal operating condition is shown in Fig. 4.
Simulation result of start-up response of this converter is also
shown in Fig. 5. From the state-space and discrete-time
models developed in Section II, a digital controller is
designed. As discussed in Section III a loopgain transfer
function is formulated using control-to-output transfer
function and a controller, two-pole two-zero configuration,
A SISOTOOL of Matlab is used to place the poles of the
closed-loop converter system, and the final controller polezeros are: zero's:(-0.4733, 0.9561); poles: (-1.0, -0.5839);
Gain: 0.4323. Closed-loop converter system stability has
been tested in Matlab. As the relative stability margins are
within the safer limits, the closed-loop system said to be
stable and also ensures load voltage regulation against various
perturbations such as source and load side disturbances. To
confirm the controller design, established in Section III,
simulation studies are conducted and load voltage regulation
is monitored. To demonstrate controller voltage regulation

Fig. 6. Dynamic response of load voltage against step change in source

voltage (Vg : 18 12 18 V).

Fig. 7. Simulated dynamic response of the load voltage against load

disturbances (R: 150 75 150 ).

Ch-1: V0; Ch-3: ig; Ch-: i0

(a) Measured waveforms

response characteristics in close agreement with the simulated

result shown in Fig. 7. The experimental observations
included here are in close agreement with the simulated
results. The reasons for the slight discrepancy between the
simulation and experimental observations are: (ii) accuracy of
the data acquisition system, (ii) unaccountable delays present
in the actual test circuit are unable to include in the
simulation platform, (iii) mismatch in the non-idealities of the
measurement set-up and the simulation circuit, and (iv)
accuracy of differential equations solvers available in the
PSIM simulator, etc.
V. CONCLUSION
Ch-1: V0; Ch-3: iL1; Ch-: i0
(b) Measured waveforms
Fig. 8. Steady-state waveforms of NFBC.

A new fifth-order boost dc-dc converter was proposed, and

then mathematical models were formulated. A steady-state
analysis revealed that it is exhibiting higher voltage boosting
capability than other comparable topologies reported in
literature. The load voltage regulation characteristics features
were measured through experiments. Simulation and
measurements were in close agreement each other and thus
validating the proposed converter boosting features.
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Ch-1: V0; Ch-3: ig; Ch-: i0

Fig. 9. Experimentally measured dynamic response of the load voltage
against load disturbance.

To confirm the theoretical analysis, design and simulation

studies, a 30 W The laboratory prototype, NFBC parameters
are tabulated in Table V, was built and then tested for its
steady-state and dynamic performance. The dsPIC30F6010
micro-controller [15] is used in experiment for realization of
the digital controller. The devices used in the experiment
converter are: MUR1560, IRFP250N, and IR2110. The
NFBC regulation feature is measured in experiment, and for
demonstration, the measured steady-state waveforms are
plotted in Fig. 8. The measured source current waveform
(Fig. 8) is slightly different from the simulated one (Fig. 4).
This discrepancy is mainly due to the fact that the simulation
platform uses ideal inductance, while in the actual test circuit
inductance operating flux is different.
The prototype
converter efficiency is measured, and it is 85.7% at nominal
operating condition. Slightly lower efficiency in the prototype
converter is on account of more source current ripple and
associated iron losses taking place within the inductor
magnetic cores. The digital controller parameters listed above
are used in experimentation and for verification, the dynamic
response characteristics have been recorded against step load
disturbances and plotted in Fig. 9. It is seen that the load
voltage regulates to 48 V in about 10 msec. These dynamic

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