Forming-free HfO2 Bipolar RRAM Device with Improved Endurance and High

Speed Operation
Yu-Sheng Chen1, Tai-Yuan Wu1,*, Pei-Jer Tzeng1, Pang-Shiu Chen2, Heng-Yuan Lee1,3,
Cha-Hsin Lin1, Frederick Chen1, and Ming-Jinn Tsai1
1

Electronics and Optoelectronics Research Laboratory, Industrial Technology Research Institute Chutung, Hsinchu 310, Taiwan,
2
Department of Materials Science and Engineering, MingShin University of Science & Technology,
3
Institute of Electronics Engineering, National Tsing Hua University, Hsinchu 300, Taiwan
* Phone: 886-3-5913750, Fax: 886-3-5917690, E-mail: DoveWu@itri.org.tw

Introduction
Binary oxide based resistive random access memory (RRAM)
is an attractive candidate for replacing Flash memory [1], owing
to its simple structure and CMOS technology compatibility.
However, many different issues should be overcome to fit the
requirements of mass production. One of those is the necessity of
a forming process to initialize the resistive memory.
It has been reported that for several binary oxides such as
CuO and NiO, appropriate oxidation process can eliminate
forming [2-4]. But all of these devices suffered unstable resistance
switching or insufficient endurance. Forming is a burden for
circuit design and testing. In this work, we report the bipolar
resistive switching memory using HfO2 film with a TiN/Ti
bi-layer electrode. A robust endurance (> 106 cycles) and long data
retention (>10 years at 200C) of this memory device was
achieved. The memory also shows fast operation speed (~10 ns),
low operation power and capability of multi-level operation.
Device Fabrication
The memory device, consisting of a TiN/Ti/HfO2/TiN stacked
multilayer structure, was fabricated on an 8 inch wafer. The HfO2
film was deposited by atomic layer deposition (ALD) with a
thickness of 3 or 10 nm. Other films were deposited by sputtering
systems. Standard lithography and dry etching processes were
taken to pattern the memory cells with sizes ranging from 0.36 to
0.96 m in diameter. Finally, an AlCu layer was deposited and
patterned on the top of the device to form the metal pad. The
microstructure of the memory device was investigated by
cross-sectional transmission electron microscopy (XTEM) and the
electrical performances were characterized by an HP4156A
semiconductor parameter analyzer and HP81110 pulse generator.
Results and Discussion
Figure 1 shows the XTEM image of the TiN/Ti/HfO2/TiN
stacked layer. The structure of HfO2 layer with a thickness of 3
nm seemed to be amorphous. The interface between the HfO2
layer and the Ti layer became obscure; presumably due to
inter-diffusion between Ti and HfO2 layer [6].
In our previous study [5], a specific forming voltage was
applied to as-fabricated devices. With the thickness of HfO2 film
more than 5 nm, the memory cell needs this step to initiate the
bipolar resistance switch. In this work, however, the initial
resistance of the device with 3-nm-thick HfO2 was much lower (~
103 ) than that with 10 nm (Fig. 2). Therefore no forming step is
necessary to initiate the resistive switching. Figure 3 shows the
bipolar resistance switching of the memory device with cell size
of 0.36 m. The SET and RESET voltage of the initial state are
the same as the operation state. The VSET and VRESET for several
devices were measured and the accumulated data is shown in Fig.
4. The distribution shows good uniformity and the memory device
can operate with low power (within 1.2V). The resistance

978-1-4244-2785-7/09/$25.00 2009 IEEE

distribution of the high resistance state (HRS) and the low

resistance state (LRS) are presented in Fig. 5. The fluctuation of
LRS was tighter than that of HRS, and the resistance ratio of
HRS/LRS ranged from 20 to 50. To study the resistance switching
mechanism, the typical SET and RESET I-V curves are plotted in
double-logarithmic axis (Fig. 6). The slope of the curve increased
suddenly during the SET process, which is related to a space
charge limited current (SCLC) conduction. This result is
consistent with our previous study [5-6]. The resistance switching
is attributed to trapping and de-trapping of oxygen vacancies in
the HfO2 film, which are thought to be created by the oxidation of
Ti gettering layer. In Fig. 7, the electrical properties of the
memory devices with different cell sizes are shown. Only the HRS
in device increases as the cell size decreases. Other properties are
insensitive to the device size, displaying good scalability.
The switching endurance of the forming-free RRAM device is
studied with pulse width of 500 s, and 106 switching cycles was
obtained (Fig. 8). The data retention of the memory cells are
tested at 200 oC and the results are shown in Fig. 9. Both
resistance states in the device remain stable at high temperature
and 10-year lifetime can be expected. The device also shows the
reversible multi-level operation by controlling the SET current
compliance under DC voltage sweep (Fig. 10). The RESET
current can also be controlled by changing the SET current
compliance. The lowest current for bipolar resistive switching is ~
20 A. Finally, the operation speed of forming-free device is also
tested with pulse mode as shown in Fig. 11. Resistance switching
is possible with 10-ns pulse width and 3-V amplitude. A high
speed operation (10 ns) of RRAM device without forming process
is demonstrated. The VSET and VRESET with pulse mode are larger
than those by DC sweep (~1.5 V). This result may be due to the
RC-delay during the measurement.
Conclusions
A forming-free resistive memory of TiN/Ti/HfO2/TiN with a
thin HfO2 film is demonstrated. The as-fabricated device can be
operated without additional forming step to initiate the operation.
This device with bipolar operation mode shows high speed (~ 10
ns), robust endurance (> 106 times), good data retention (10-year
lifetime), enough resistance ratio, and low power consumption.
The simple structure and capability of multi-level operation
demonstrate RRAM as a high-density memory in the near future.

References
[1] I.G. Baek et al., IEDM Tech. Dig., p587, 2004.
[2] H. B. Lv et al., Elec. Dev. Lett., vol. 29, 1, p47, 2008.
[3] H. B. Lv et al., NVMTS, p52, 2008.
[4] L. Courtade et al., NVMTS, p1, 2007
[5] H. Y. Lee et al., IEDM Tech. Dig., 2008 to be published
[6] H. Y. Lee et al., VLSI-TSA, p146, 2007

37

-3

AlCu
10
-ln(1-F)

Ti
HfOx

Current (A)

10 nm
3 nm

TiN

10

-1

10

Fig. 1 XTEM image of TiN/Ti/HfO2/TiN

memory device.

0.0

-0.4

-0.8

-1.2

Fig. 3 Bipolar resistance switching

characteristic of TiN/Ti/HfO2/TiN device.

-4

10k

RLow

1k

0.8

RHigh
RLow

1k 0
1
2
3
4
5
6
10 10 10 10 10 10 10
Number of switch cycle

VRESET

-0.8

-3

10

-4

Current (A)

ISET=500 A
0
0.0

10

-5

10

-6

10

-7

10
0.2

0.4

0.6

I=500uA
I=200uA
I=100uA
I=50uA
I=20uA

0.8
2

Cell size (m )

1.0

Fig. 7 Cell size dependence of various

resistance switching parameters in
memory device.

-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5

Applied voltage (V)

Fig. 10 The multi-level characteristic by

controlling the SET current compliance.

38

Current (A)

IV

-5

10

IV

SET
RESET

-6

10

-7

10

Fig. 8 Switch endurance of 106 cycles in

TiN/Ti/HfO2/TiN forming-free memory
device by 500s pulse.

VSET

0.0

10
10
Resistance ()

Fig. 5 HRS and LRS distribution of

TiN/Ti/HfO2/TiN forming-free memory
device.

Resistance (ohm)

RHigh

10k

Rlow

-2

10 3
10

0.4
0.8
1.2
1.6
Operation voltage (V)

100k

Rhigh

0.1
1
Applied voltage (V)

Fig. 6 I-V fitting of HRS and LRS in

TiN/Ti/HfO2/TiN device to SCLC current
transport.

Resistance (ohm)

0.0

-1

10

10

10k

1k

RHigh
RLow

100

10

200 C
5

10
10
10
Time (sec)

10

Fig. 9 Data retention of HRS and LRS at

200oC. This result predict 10-year lifetime
of stored bit.
VRESET pulse (V) VSET pulse (V)

-ln(1-F)

-ln(1-F)

Vset
Vreset

-1

IRESET,Max (100 A)

10
-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5
Applied voltage (V)

10

Fig. 4 SET and RESET voltage

distribution of the TiN/Ti/HfO2/TiN
memory.

Resistance (Ohm)

10

-2

Voltage (V)

-3

10

initial
switch

10

10

10

10
10
10
10
Resistance ()

Fig. 2 Initial resistance comparison

between HfO2 thickness of 3 nm and 10
nm of the TiN/Ti/HfO2/TiN device.

-1.6

-5

10

-6

-2

10 2
10

TiN

-4

10

3
2

Input
Response

SET
(3V / 10nS)

Input
Response

RESET
(3V / 10nS)

1
0
0

-1
-2
-3
-200

200
400
Time (nSec)

600

Fig. 11 Test of operation speed with 10-ns

pulse width of TiN/Ti/HfO2/TiN device.