08 Microprocessor PDF

Microprocessors
B, C, D, E, H & L Registers are six 8bit

general purpose Registers.
Stack pointer is a 16bit stack RAM
pointer Register which holds address of
TOP of stack. SP Register is a up/down
counter whose contents will be updated
automatically by machine after PUSH,
CALL, RST, POP, RET instructions. It is
to be initialized with required address by
programmer.
01. Architecture of 8085

01.
Sol:
Accumulator is a 8 bit Data Register in

8085 P.
ALU of 8085 is Accumulatorbased ALU
i.e., Accumulator behaves as one of the
source operands and destination operand
for result storage in most of arithmetic &
logical operations.
Accumulator of 8085 is also used in
load/store, input/output operations.
Instruction Register is a 8bit program
invisible Register. During Instruction
Fetch cycle, op code byte fetched from
program memory is stored in this
instruction Register. This instruction
Register is not programmable and cannot
be accessed by the user.
Program counter is a 16bit ROM pointer

Register which holds Address of Next ROM
location (Which may contain either Next
instruction op code or current instruction
operand). Program counter is a up counter
whose contents will be incremented by 1,
automatically by machine. It will be
initialized with 0000H by machine, upon
reset.
02.
Sol: Programming model
A
Flag Register
B
C
D
E
H
L
Stack pointer (SP)
Program counter (P.C)
Accumulator is a 8bit Register involved in
most of the operations performed by
8085 like
Arithmetic,
Logical,
Load/store,
input/output operations.
Flag Register is a 8bit Register which
consists of 5 conditional flags (CY, P,
AC, Z, S) whose status will be updated
by ALU after Arithmetic and logical
operations.
ACE Engineering Academy
02. Pin Details & Interrupts of 8085

Level - 1
01.
Sol:
Microprocessors are equipped with a

number of pins for communication with
external world. This is known as system
Bus.
The number of pins used for a system Bus
is limited by both technological &
economical considerations. During the
time period when 8 bit 8085
microprocessor
was
designed
&
developed, the cost effective optimum
pin number was 40. To utilize this limited
no. of pins effectively, system buses
have been designed in a number of ways
leading to diverse bus structure in 8085
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: 282 :
All the Bus lines in 8085 can be classified

into 3 Groups
(i) Address Bus
(ii) Data Bus
(iii) Control Bus
(i). Address Bus:
As memory and I/O devices are external
to the microprocessor, it is equipped with
the mechanism for selecting a unique
memory location or an I/O device for
communication. The Address Bus
provides this unique memory Address of
I/O device Address.
8085 P has 16 Address output lines.
8085 sends 16bit Address in 1st clock
cycle of any external Access operation to
select one out of so many external
elements (either memory locations or IO
devices).
8085P can generate a total no. of 216
unique Addresses i.e., 65,536 Addresses.
8085P can access a memory of max.
Size 64 kB.
The Address space of 8085 P is 0000H
to FFFFH.
To facilitate external devices (like a DMA
controller) to gain control of the address
bus, the address bus of microprocessor is
usually provided with unidirectional
tristate buffers.
(ii). Data Bus:
This Bus is used to transfer data between
microprocessor and external memory or
I/O.
Data transfer in both directions takes
place through the same pins known as
data bus. Any information like instruction
or data is communicated with external
world through these lines.
The width of the data bus is normally
equal to the data or word size of ALU.
The data bus is usually provided with
bidirectional tristate buffers, so that an
Microprocessors
external device can gain control of it , if

necessary.
The following are micro operations
performed by 8085 related to information
transfer over its Data Bus.
8085 receives 8 bit opcode via 8bit
Data Bus during opcode fetch cycle
(from ROM)
8085 receives 8bit operand via 8bit
Data Bus during operand read cycle
(from ROM)
8085 receives 8bit data via 8bit Data
Bus during memory read cycle (from
RAM)
8085 sends 8bit data via 8bit Data Bus
during memory write cycle (to RAM)
8085 receives (inputs) 8 bit data via 8
bit Data Bus during IO read cycle
(from input device)
8085 sends (outputs) 8 bit data via 8
bit Data Bus during IO write cycle (to
output device)
(iii). Control Bus:
This Bus consists of Group of control
lines for receiving & generating various
signals for coordination & control of
various operations involving external
elements (memory locations & devices).
These control lines can be divided into 2
types, namely memory & I/O control
lines
( RD , WR , IO / M , Ready, ALE, S0, S1)
and CPU & bus control lines (resetout,
interrupts, HOLD, HLDA)
02.
Sol: Refer IES-2015 Conventional solutions.
03.Ans: (a)
Sol:
(i) READY:
This is an active-high control input pin
: 283 :
This input pin is provided in 8085 to

make it to deal with slow peripherals &
slow memories. The slow devices use
this input line to gain extra time for
communication
of
data
with
microprocessor.
If READY input is lowered (i.e., made 0)
by external device, then 8085P enters
into WAIT state.
If READY input is raised (i.e., made 1)
by external device, then 8085 p comes
out WAIT state & enters into next
operation.
(ii) ALE:
ALE stands for Address Latch Enable
which is an active high output pin.
When 8085 generates 16 bit Address in
T1, then it makes ALE output as activehigh.
This control signal is used to enable
Address Latch.
(iii) HOLD:
This control input pin is provided to
request P for Direct memory Access.
The external device can use this control
input pin to request P for getting control
of the system bus.
If HOLD input is raised by external
device (requesting for DMA), then
8085P tristates the system bus lines,
generates acknowledgment signal via
HLDA output and then enters into IDLE
state.
If HOLD input is lowered by external
device (at the end of DMA), then 8085
P comes out of IDLE state.
IES Postal Coaching Solutions
(iv) TRAP:
TRAP (also known as RST 4.5) is a
Hardware,
Non-maskable,
vectored
interrupt
This interrupt cannot be disabled by
programmer it is always said to be in
enabled condition.
This interrupt is both +ve edge triggered
and active high level triggered.
Instructions like EI, DI & SIM dont
effect TRAP.
The vector Address is 0024H.
04.
05. Ans: (c)
06.
Sol:Refer IES-2015 Conventional solutions.
07. Ans: (c)
08.
Sol:
Interrupt is an event that demands

attention of microprocessor.
If occurrence of interrupt event is
recognized by microprocessor, then it
breaks execution sequence of main
program and branches to a separate sub
program known as Interrupt service
Routine (ISR). After execution of ISR,
microprocessor returns back to main
program.
8085 P has total 13 interrupts, whose
availability and nature are as given
below.
8085p has 5 hardware interrupts
(external interrupts) which are available
in the form of hardware interrupt input
pins.
: 284 :
8085 microprocessor has 8 software

interrupts existing in the form of RST
instructions, as specified below.
Microprocessors
8085 microprocessor has 12 Vectored

interrupts which exist in the form of
RSTX. The fixed vector address for any
vectored interrupt is (8X)16.
RST 0
RST 1
RST 2
RST 3
RST 4
RST 5
RST 6
RST 7
Vectored
interrupt
RST 0
RST 1
RST 2
RST 3
RST 4
RST 4.5
RST 5
RST 5.5
RST 6
RST 6.5
RST 7
RST 7.5
TRAP or RST 4.5 (High Priority)
or
RST 7.5
RST 6.5
Vectored
Address
0000H
0008H
0010H
0018 H
0020 H
0024 H
0028 H
002C H
0030 H
0034 H
0038 H
003C H
RST 5.5
INTR
(Low priority )
means +ve edge sensitive input

means active high level sensitive
input
8085 microprocessor has 12 maskable
interrupts (RST0 to RST7, INTR, RST
7.5, RST 6.5, RST 5.5) and 1 Non
maskable interrupt (TRAP or RST 4.5).
All the 12 maksable interrupts can be
globally enabled by programmer using EI
instruction & can be globally disabled by
programmer using DI instruction. The 3
Hardware, maskable, vectored interrupts
(RST 7.5, RST 6.5, RST 5.5) can be
selectively masked by
programmer
using SIM instruction. But, the non
maskable interrupt (TRAP) is not
affected by EI, DI or SIM instructions.
8085p has only one Non-vectored

interrupt namely INTR (Interrupt
Request). For servicing such non
vectored interrupt, external hardware is
required to supply vector address.
Serial I/O of 8085:
Two Hardware pin are provided in 8085
p to facilitate serial data transfer namely
SOD output pin & SID input pin.
SOD stands for serial output Data
SID stands for serial input Data
For execution of SIM instruction, the
data bit in MSB of accumulator is
outputted via SOD output.
For execution of RIM instruction, the
data bit at SID input will be received into
MSB of Accumulator.
09. Ans. (c)
: 285 :
02.
Level - 2
01.
Sol:
8085 P has 16 Address lines and 8 Data

lines i.e., total 24 pins (16A+8D) are
required for these provisions. To save
pins, lower order 8 Address lines (A0 to
A7) are time-multiplexed with 8 Data
lines (D0 to D7) and made available as
AD0 to AD7.
Therefore, only 16 pins (8 A/D+8A) are
needed instead of 24 pins (16A+8D).
AD0 to AD7 is a time shared Bus.
During T1, lower order Address (A0 to
A7) is supplied via this Bus. In
subsequent
T-states, this Bus is used
as Data Bus.
In T1, whenever 8085 generates Address,
it makes ALE output as high. This high
ALE signal is used to enable address
latch which is used for de multiplexing
the multiplexed Address/Data bus.
03.
04.
Sol: The Hardware interrupts of 8085 P can be
classified into the following 3 types:

(1) Hardware,
maskable
vectored
interrupts:
There are 3 interrupts in 8085 which are
hardware maskable & vectored interrupts
namely RST 7.5, RST 6.5 & RST 5.5.
These 3 interrupts can be globally
enabled/disabled using EI instruction/DI
instruction.
These 3 interrupts can be selectively &
locally enabled/disabled using SIM
instruction.
(2)
Hardware maskable Non vectored

interrupt:
There is one interrupt in 8085 which is
hardware maskable & non vectored
interrupt namely INTR (Interrupt
Request).
For servicing this non vectored interrupt
Request, external hardware (namely
8259PIC) is required to supply vector
Address.
This
interrupt
can
be
globally
enabled/disabled using EI instruction/DI
instruction. But, not affected by SIM
instruction.
(3)
Hardware non maskable vectored

interrupt
There is one interrupt in 8085 which is
hardware, non maskable & vectored
interrupt namely TRAP or RST 4.5
TRAP is not affected by EI, DI & SIM
instructions.
+5V
VCC
R
ALE
8085
74LS373 A0 to A7
AL
RESET IN
fcrystal
X1 AD0 to AD7
X2
GND
D0 to D7
A8 to A15
A8 to A15
READY input pin is provided to deal with

slow peripherals. If READY input is
lowered, then 8085P enters into wait
state. If READY input is raised, then
8085P comes out of wait state, and
continues with next operation.
: 286 :
TRAP is assigned with High priority & is

used in emergency situations like power
failure.
Microprocessors
03. Interfacing with 8085

Level - 1
05.
Sol: When there is an interrupt request on INTR
pin, then 8085 checks:

(i) Whether any interrupt is being processed
(ii) Whether interrupt system is disabled
(iii) Whether any interrupt is pending on
RST 7.5, RST 6.5, RST 5.5 and TRAP lines.
If all the above are not true then 8085
accepts the interrupt request and executes
interrupt.
Acknowledgement machine cycle ( ) as
given below:
8085 samples INTR during last but one
clock period of each instructions
execution.
8085 makes S0 S1 and IO/ M as high,
which can be treated as interrupt Ack.
8085 makes INTA output as low. The
external hardware must use INTA both
as device select signal and as a strobe
signal
The external hardware may respond to
INTA signal by placing RST code
(1byte) on the data bus.
The instruction code is decoded is
subsequent clock cycles and control
branches to ISR addressed by the RST
instruction in the next machine cycle.
Note: If the instruction code is for the CALL
Address instruction (3 byte), then the interrupt
Ack extends to 2 more machine cycles. Here
external hardware places 2 bytes of address on
data bus in synchronization with low INTA .
06.
01.
Sol:
In memory mapped I/O technique, I/O

devices are mapped as memory locations.
I/O device are assigned with 16 bit
Addresses.
A portion of memory address space is
allocated for I/O addresses.
Memory
FFFFH
I/O
Memory
0000H
Same address cannot be used for both

memory locations and I/O device, since a
part of memory address space is used by
I/O devices.
All the memory reference instructions can
be used in the case of I/O devices also
i.e., instruction like MOV, ADD, SUB,
STA, LDA etc can be used for I/O
devices. This is one of the most important
advantages of memory mapped I/O
technique. This facilitates the arithmetic
& logical operations to be performed
directly on I/O data.
Control signals generated for memory
Access IO / M 0 are same as control
signals for I/O access IO / M 0 . The
same memory read & Write control
signals are used for I/O devices also (i.e.,
MEMWR & MEMRD )
A part of the memory Address space is
used by I/O devices. As such, the
: 287 :
maximum memory size will be less than

the address space of P.
It can be either 64 KB memory OR 64K
I/O
03.
Sol:
The information about how many bytes
are there in the instruction is included in
the 1st byte of instruction.
ALE stands for address Latch Enable.
During T1(i.e., 1st clock cycle), when
8085 generates 16 bit Address (Lower
order 8bit Address Via AD0 to AD7 &
Higher order 8bit Address via A8 to
A15), it also asserts ALE output as 1.
The ALE control signal is to be used by
designer to enable 8bit Address Latch to
separate lower order Address from the
multiplexed Address/Data Bus. i.e., the
function of ALE is to de multiplex the
Address/Data Bus.
In the subsequent T-states of Instruction
cycle, ALE output is asserted as 0
04.
(i) n
Level - 2
01.
02.
Sol:
02. Ans. (b)
Sol:
1 KB
8 chips
1024 1
(ii) n
16 KB
128 chips
1024 1
The time required for P to complete an

external access operation is known as
machine cycle.
A machine cycle is a cycle of clock
cycles i.e., a sequence of clock cycles
as run by machine.
Machine cycle can be a fetch machine
cycle or Execute machine cycle.
Various machine cycles of 8085 are:
1.
2.
3.
4.
5.
6.
Opcode fetch machine cycle

Operand Read machine cycle
Memory write machine cycle
Memory Read Machine cycle
I/O write Machine cycle
I/O Read Machine cycle
ROM related
RAM related
I/O related
1. Opcode Fetch machine cycle:

During this opcode fetch machine cycle,
the opcode of the instruction to be
executed is fetched from program
memory & decoded to know the
operation to be performed. The following
4 micro operations are performed by
8085 in 4 T-states.
OP1: 8085 sends 16 bit address of ROM
location (available in program counter) via
address bus to program memory, for
selecting memory location.
OP2: 8085 generates memory Read
control signals:
IO / M 0, WR 1, RD 0
OP3: 8085 receives the opcode via data
bus from program memory and stores in
Instruction Register.
: 288 :
OP4: 8085 decodes contents of Instruction

Register and produces machine level
information (timing information and control
information) which are to be used for
completing operation.
2. Operand Read Machine cycle:
During this operand Read machine cycle,
the operand of instruction (either L.O
operand or H.O operand) is read from
program memory. 8085 performs the
following 3 micro operations in 3 Tstates.
OP1: 8085 sends 16bit Address of ROM
location (available in program counter) via
address bus to program memory, for
selecting memory location.
OP2: 8085 generates memory Read control
signals
IO / M 0, RD 0, WR 1
OP3: 8085 receives operand via data bus
from program memory
3. Memory write Machine cycle:
During this memory write machine cycle,
8085 writes a data byte into 8bit RAM
location. 8085 Performs the following 3
micro operations in 3 T-states.
OP1: 8085 sends 16 bit Address of RAM
location (available either in instruction or in
pointer Register) via Address Bus to Data
Memory, for selecting memory location.
OP2: 8085 sends 8bit data via data bus to
memory.
0P3: 8085 generates memory write control
signals
IO / M 0, WR 0, RD 1
Microprocessors
4. Memory Read Machine cycle:

During this memory Read machine cycle,
8085 receives a data byte from 8 bit
RAM location. 8085 performs the
following 3 micro operations in 3Tstates:
OP1: 8085 generates 16 bit Address of
RAM location (Address available either in
instruction or in pointer
register)
via
address bus to Data memory for selecting
memory location.
OP2: 8085 generates memory Read control
signals:
IO / M 0, RD 0, WR 1
OP3: 8085 receives data byte via data bus
from data memory.
5. I/O write machine cycle:
During this I/O write machine cycle, 8085
writes a data byte to o/p device connected
to output port of 8255 chip. 8085
performs the following 3 micro
operations in 3T-states:
OP1: 8085 generates 8 bit address of output
port (Address available in instruction) via
address bus (8 bit output port address via A
D0 to AD7 and its duplicate via A8 to A15)
to 8255IC for selecting output port.
OP2:8085 sends data byte (in Accumulator
outputs) via Data Bus to 8255IC
OP3: 8085 generates I0 write control
signals.
IO / M 1, WR 0, RD 1
6. I/O Read Machine cycle:
During this I0Read machine cycle, 8085
receives a data byte from input device
connected to input port of 8255 chip.
: 289 :
8085
performs
the
3microperaty in 3T-states:
following
OP1: 8085 generates 8 bit Address of

input/port
(Address
available
in
instruction) Via Address available in
instruction) via Address Bus (8 bit input
port Address Via AD0 to AD7 and its
duplicate Via A8 to A15) to 8255IC for
selecting input port.
OP2: 8085 generates I0Read control
signals.
IO / M 1, RD 0, WR 1
OP3: 8085 receives data byte into

Accumulator via Data Bus from 8255IC
(Note: The other machine cycles are:
Interrupt acknowledgement machine
cycle, Bus Idle machine cycle, Hold
acknowledgement machine cycle, Halt
machine cycle)
03.
04.
05.
Sol:
Refer IES-2015 Conventional solutions.
06.
04. Instruction Set of 8085

Level - 1
01.
Sol:
A 8 bit microprocessors processing

capacity is 8bit. As such it can fetch and
decode 8bit opcode.
With opcode length of 8bits, there can be
total 256 opcodes i.e., 256 instructions.
02.
Sol:(a) ACI 20H--- Immediate Addressing mode

(b) CMA --------- Implicit Addressing mode
(c) STA 2500H-----Direct Addressing mode
(d) LXI H, 2005H---Immediate Addressing
mode
(e) XCHG--------Register Addressing
mode
(f) MOV E, L ----- Register Addressing
mode
03.
Sol:
XRA A:
The contents of Accumulator is XORed
with same and result is stored in
Accumulator. The addressing mode is
Register Addressing mode. Carry flag
and Auxillary carry flag will be cleared
and remaining flags affected based on
result.
DAA:
The content of accumulator is adjusted
into valid decimal range by 8085 after
Addition. 8085 performs following steps
for execution of DAA instruction.
If (LN>9 OR AC=1), then 6 is added to LN
If (HN>9 OR CY=1), then 6 is added to HN
(LN stands for Lower Nibble of
Accumulator and HN stands for Higher
Nibble of Accumulator)
: 290 :
Microprocessors
The Addressing mode is Implicit

Addressing mode. All the flags will be
affected accordingly.
then parity flag is set to 1. Otherwise,

reset to 0. i.e., for even parity, P is set
and for odd parity, P is reset.
DCR M:
The content of 8 bit memory location is
subtracted from the contents of
Accumulator and the result will be stored
in Accumulator. The Addressing mode is
Register Indirect Addressing mode. All
the flags will be affected accordingly.
Auxiliary carry Flag:

After an Arithmetic/Logical operation, if
there is a carry generated from D3 to D4
then AC is set to 1. Otherwise reset to
0.AC is only used by machine for internal
BCD arithmetic operation (like DAA
instruction execution).
ADD B:
The content of accumulator is added with
the contents of B register and the result
will be stored in Accumulator. The
Addressing mode is Register Addressing
mode. All the flags will be affected
accordingly.
Zero Flag:
the result contains all 0s then zero flag is
set to 1. Otherwise, reset to 0.
Sign Flag:
After an Arithmetic/Logical operation,
the MSB of result is always copied into
sign flag. If MSB of result is 1, then sign
flag is set to 1.If MSB of result is 0, then
sign flag is reset to 0.
04.
05.
Sol:
06.
The flag Register of Intel 8085 consists of 5

conditional flags whose status will be
updated after Arithmetic and Logical
Operations performed by ALU. The purpose
of the flags is to indicate the nature of result.
The 8bit flag register format & their
working is given below.
Sol:
S Z X AC X P X CY
07.
Carry flag:
After an Arithmetic/ Logical operation, If
there is carry generated from MSB of
result then carry flag is set to 1.
For the execution of MOV D, B

instruction, the contents of B register is
copied into D Register. This is an internal
8bit data transfer operation that doesnt
involve ALU.
As such, either Z-flag or other
conditional flags are not affected
Ans: (B)
08.
09. Ans: (B)
Parity flag:
total number of 1s in the result is even
: 291 :
Level - 2
4. Direct Addressing mode:

In direct addressing mode, one of the
operands involved in operation is
memory location and 16bit address of
memory location is given in instruction
(or 8bit port address of I/O port)
Value at address is the operand involved
in operation.
Ex:
STA 2000H
LHLD 1234H
OUT F8H
IN
F9H
01.
Sol:
Mode of specifying address of operand

involved in the operation is known as
addressing mode.
8085 microprocessors I.S.A supports 5
addressing modes namely register
addressing mode, implicit addressing
mode, Immediate addressing mode, direct
addressing mode & indirect addressing
mode.
1. Register addressing mode:
In register addressing mode, operands
involved in operation is/are register. This
addressing mode is also known as
register direct addressing mode.
Ex:
MOV A, B
ADD H
XRA A
2. Implicit Addressing mode:
In implicit addressing mode, operand
involved in operation is not specified
explicitly in instruction. As such, p
implicitly assumes accumulator is the
operand i.e., it is implied that
accumulator is the operand.
Ex: DAA
CMA
RAL
RLC
RAR
RRC
3. Immediate addressing mode:
In immediate addressing mode, the
operand involved in operating is given in
the instruction itself which is either 8bit
number or 16bit number. i.e, value given
in the instruction is operand involved in
operation.
Ex: MVI A, 88H; (A)
88H
LXI SP,
2500H; (SP) 2500H
JMP 1000H; (PC) 1000H
5. Indirect addressing mode:

In Indirect addressing mode, one of the
operands involved in operation is
memory location and 16bit address of
memory location is made available in
register pointer (like HL pair, BC pair,
DE pair, Stack Pointer)
Also known as register indirect addressing
mode.
Ex:
MOV A, M
PUSH PSW
STAX B
RET
02.
Sol: Initial values: (A) = 95 H, CY = 1

(i)
RAL:
Before RAL
CY
1
10010101
After RAL
CY
1
00101011
(A) = 2BH, CY = 1
: 292 :
(ii)
RRC:
Before RRC:
Microprocessors
; (A) = 11 H, CY = 0
03.
Sol:
CY
1
(p)
10010101
(q)
After RRC:
(r)
CY
1
11001010
XRA A
SUB A
ORA A
ANA A
DAD H
LXI H, 0020H
04.
Sol:
(A) = CAH, CY = 1
(iii) XRI A5H:
(A) = 95 H 1 0 0 1 0 1 0 1
A5 H 1 0 1 0 0 1 0 1
(A) = 30 H 0 0 1 1 0 0 0 0
; CY = 0
(iv) CPI A9H
:
(A) = 95 H A9H
;95H A9H CY = 1, S = 1, Z
=0
;(A) = 95 H, CY = 1 ( ve result)
(v) ORI C9H
(A) = 95 H 1 0 0 1 0 1 0 1
C9 H 1 1 0 0 1 0 0 1
(A) =DDH 1 1 0 1 1 1 0 1
; (A) = DDH, CY = 0
(vi) ANI 33 H ;
(A) = 95 H 1 0 0 1 0 1 0 1
33 H 0 0 1 1 0 0 1 1
(A) = 11 H 0 0 0 1 0 0 0 1
1. PUSH instruction
Syntax: PUSH r16
Operation: Contents of 16 bit register given
in instruction is moved into stack memory
(as given below) and stack pointer contents
decremented by 2.
((SP) 1) (rH)
((SP) 2) (rL)
(SP) is decremented by 2
Ex:
PUSH B
PUSH PSW
PUSH D
PUSH H
2. POP instruction
Syntax: POP r16
Operation: Contents of 2 memory locations
from Top of stack is retrieved into specified
16 bit register and stack pointer contents
will be incremented by 2
(rL) ((SP))
(rH) ((SP) + 1)
(SP) is incremented by 2
Ex:
POP PSW
POP D
POP
H
POP B
: 293 :
3. XTHL instruction
Syntax: XTHL
Operation: Contents of 2 memory locations
from Top of stack exchanged with contents
of HL pair. The contents of stack pointer
will be unchanged.
Ex: XTHL
06.
07.
08.
05.
09.
Sol: CALL instruction is a branch control

instruction which can be used to transfer
program control from main program to
subroutine.
Syntax: CALL Addr16
Operation:
((SP) 1) (PCH)
((SP) 2) (PCL)
(SP) is decremented by 2
RET instruction is used to transfer program
control back to main program from end of
subroutine.
Syntax: RET
Operation:
(PCL) ((SP))
(PCH) ((SP) + 1)
(SP) is incremented by 2
Sol: SIM (Set Interrupt Mask) instruction and

RIM (Read Interrupt Mask) instruction are
multipurpose instructions.
SIM instruction:
SIM is used for setting local masks on
interrupts and also for sending a data bit
via SOD output pin.
The programmer has to initialize
accumulator with 8 bit number and then
for execution of SIM instruction, 8085 p
treats the contents of accumulator as
shown below.
Main program
MAIN: 1st instruction of
MP
SOD
User defined
Service Routine
Addr16 : 1st instruction
Of USR
MP to USR
CALL Addr16
HLT
USR to MP
RET
R7.5 MSE M7.5 M6.5 M5.5
Reset
7.5FF
Serial
Output
Data
Next instruction
SDE
Serial
Data
Enable
Local mask
status bits for
3HW, M, V.Is
Mask
Set Enable
If M5.5 bit is set to 1 by programmer, then

p disables RST 5.5 interrupt locally.
If M6.5 bit is set to 1 by programmer, then
p disables RST 6.5 interrupt locally.
If M 7.5 bit is set to 1 by programmer,
then p disables RST 7.5 interrupt
locally.
If MSE bit is set to 1 by programmer, then
only local mask definitions are valid.
: 294 :
If R7.5 bit is set to 1 by programmer, then

p clears (Resets) RST 7.5 flip-flop.
If SDE bit is set to 1 by programmer, then
p sends data bit in MSB of accumulator
out via SOD output pin.
If RST 5.5 interrupt is in pending state,

then p sets I5.5 bit.
The data bit at SID input pin is received
into MSB of accumulator.
RIM instruction
RIM is used for reading status of local
masks, global mask, pending interrupts and
also for receiving data bit at SID input pin.
For execution of RIM instruction, 8085 p
loads accumulator with 8bit number as
shown below (which is to be interpreted by
programmer)
SID I7.5 I5.6 I5.5 IE M7.5 M6.5 M5.5
Pending
Status Bits for
3 HW, M, V.Is
Serial
Input
Data
05. Programming with 8085

Level - 1
01.
02.
Sol:
Local mask
status bits for
3HW, M, V.Is
ORG 0000H
JMP MAIN
ORG 2501H
NUM
DB
96H
ORG 2100H
Global mask
status bit
MAIN:
LDA 2501H
CMA
If RST 5.5 interrupt is locally

then p sets M5.5 bit.
If all 12 maskable interrupts
globally enabled condition, then
IE bit.
Microprocessors
masked
01H
STA
2502H
HLT
masked
masked
ADI
03.
Sol:
are in
p sets
: 295 :
04.
Sol: ; Two 8 bit Hex numbers are stored in
;
;
;
;
;
;
;
;
memory locations 2000H & 2001H respectively.

16 bit Result will be stored in 2002H & 2003H
High byte of result in 2002H
Low byte of result in 2003H
First no. in DE pair, second no. in ACC.
logic: A bit of Accumulator will be checked (starting from LSB). If the bit is 0, nothing is
added to HL pair contents. If the bit is 1, DE pair contents is added to HL pair, i.e., DE pair
contents will be doubled. This will be continued till all the 8 bits of Accumulator checked.
ORG 0000H
JMP MAIN
ORG 0100H
MAIN: LXI H,
2000H
MOV E, M
MVI D, 00H
; (DE) = 1st number
LDA 2001H
; (A) = 2nd number
MVI C, 08H
; (C) = 8 i.e., no. of shift & Adds to be performed.
LXI
H, 0000H
AGAIN: RRC
; isolate LS bit of Accumulator by rotating it into carry flag
JNC SKIP
; if CY = 0, Jump to SKIP
DAD D
; if CY = 1, increment HL by contents of DE
SKIP: XCHG
DAD H
DCR
C
JNZ
AGAIN
; When the loop ends, HL pair contains the result i.e., product
MOV A, H
STA
2002H
MOV A, L
STA
2003H
HLT
When large integers are involved in multiplication, repeated addition technique is not suitable.
Make use of place value of digits in the multiplier and adopt shift and add method.
05.
Sol:
ORG 0000H
JMP
MAIN
ORG 0100H
MAIN: XRA A
MOV C,A
LDA
4200H
MOV B,A
END:
LDA
ADD
JNC
INR
STA
MOV
STA
HLT
4201H
B
END
C
4202H
A,C
4203H
: 296 :
START
Load accumulator with the
contents of 4200H
07.
08.
Sol:
Memory location 2050 holds data byte F7H.
This data is to be transferred to
accumulator
Using MOV instruction:
LXI H,2050H
; (HL) 2050H
MOV A,M ; (A) (HL) = F7H
Using LDAX instruction:
LXI B,2050H
; (BC) 2050H
LDAX B
; (A)(BC) = F7H
Using LDA instruction:
LDA 2050H
; (A) (2050H)
Out of above 3 op codes, LDA is more
efficient because less no. of T-states are
required.
Copy the contents of

accumulator into register B
Load accumulator with the
contents of 4201H
Add contents of register B
with the contents of
accumulator
Any
carry
?
NO
YES
Increment contents
of register C
Microprocessors
09.
Sol:
ORG 0000H
JMP MAIN
ORG 2600H
TABL dB
Store results in
A & C in the locations
4202H & 4203H
00,01,04,09,16,25,36,69,64,81
MAIN:
STOP
06.
Sol:
MOV M,r; the contents of 8 bit
register is copied into a RAM
location whose 16bit address is
available in HL pair.
INR r ;
the contents of 8 bit
register is incremented by 1.
RLC ; Rotate
contents
of
accumulator to left by 1 bit,
without including CY.
CMA ; complements contents of
accumulator
DELAY:
LOOP:
ORG 0100H
LXI H, 2600H
IN
F8H;
MOV L,A
MOV A,M
OUT F9H
CALL DELAY
JMP MAIN
MVI A, FFH
DCR A
JNZ LOOP
RET
HLT
10. Ans: (c)
: 297 :
Level - 2
02.
Sol:
01.
LXI B,2100H ; (BC)2100H

LXI D,0200H ; (DE)0200H
Sol:
ORG
JMP
0000H
LXI SP,2700H
; (SP)2700H
MAIN
PUSH B
; (TOS)(BC)
ORG 1000H
= 2100H
SUM EQU 2510H
(SP) = 26FEH
CARY EQU 2511M
PUSH D
; (TOS)(DE)
MAIN:XRA A
= 0200H
MOV B,A
MVI
C,04H
LXI
H, 2500H
(SP) = 26FCH
LXI H,0100H ; (HL)0100H
; (TOS)(HL)
LOOP: ADD M
JNC
NEXT
INR
NEXT:INX
; (TOS)=0100H,
(HL)=0200H
DAD D
DCR C
JNZ
LOOP
STA
SUM
; (HL)(HL)+(DE)
(HL)0200H+0200H
(HL)=0400H
HLT
; (HL) = 0400H,
MOV A,B
STA
CARY
(DE)=0200H
HLT
03.
Sol:
: 298 :
Microprocessors
04.
Sol:
ORG
0000H
JMP
MAIN
CNTR
EQU 100AH
CARY
EQU 2002H
ORG
0100H
MAIN: LXI
H,0000H
MVI
A,05H
STA
CNTR
LXI
B,1000H
LOOP: LDAX
LI:
B
MOV
E, A
2002H
2001H
INX
2000H
LBRSLT
LDAX
MOV
D,A
100AH
CNTR
INX
DAD
JNC
L1
LDA
CARY
INR
STA
CARY
LDA
CNTR
DCR
STA
CNTR
JNZ
LOOP
SHLD
2000H
1009H
CARRY
HBRSLT
24 bit
result
5th no.
4th no.
3rd no.
2nd no.
1001H
1000H
1st no.
HLD
END
: 299 :
05.
Sol:
06.
07.
08.
09.
START
Sol:
(A)(2000)=X
(B)(2001)=Y
10.
11.
(A)-(B)
Sol:
ORG 0000H
JMP
MAIN
ORG 0100H
NO
YES
Any
carry
zero
result
?
YES
STOP
NO
(B)(B)-1
(A)(A)-2
MAIN: LDA 4000H

MVI
C,08H
LOOP: RLC
JNC
SKIP
INR
SKIP:
JNZ
DCR C
LOOP
MOV A,B
ORG 0000H
JMP MAIN
X EQU
2000H
Y EQU
2001H
ORG 0100H
MAIN:
LDA Y
MOV B,A
LDA X
RPT: CMP B
JZ
STOP
JC
NEG
SUI 02H
JMP RPT
NEG: DCR B
JMP RPT
STOP:
HLT
RAR
JC
EVEN
MVI
A,DDH
STA
4000H
HLT
EVEN: MVI
STA
STOP:
A,EEH
4000H
HLT
: 300 :
Microprocessors
06. 8086 Microprocessor

Refer IES-2015 Booklet for all the Level-1
and Level-2 questions and their solutions.

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Microprocessors

B, C, D, E, H & L Registers are six 8bit

01. Architecture of 8085

Accumulator is a 8 bit Data Register in

Program counter is a 16bit ROM pointer

02. Pin Details & Interrupts of 8085

Microprocessors are equipped with a

All the Bus lines in 8085 can be classified

external device can gain control of it , if

This input pin is provided in 8085 to

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Interrupt is an event that demands

8085 microprocessor has 8 software

8085 microprocessor has 12 Vectored

TRAP or RST 4.5 (High Priority)

means +ve edge sensitive input

8085p has only one Non-vectored

8085 P has 16 Address lines and 8 Data

Sol: The Hardware interrupts of 8085 P can be

classified into the following 3 types:

Hardware maskable Non vectored

Hardware non maskable vectored

READY input pin is provided to deal with

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TRAP is assigned with High priority & is

03. Interfacing with 8085

pin, then 8085 checks:

In memory mapped I/O technique, I/O

Same address cannot be used for both

maximum memory size will be less than

02. Ans. (b)

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The time required for P to complete an

Opcode fetch machine cycle

1. Opcode Fetch machine cycle:

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OP4: 8085 decodes contents of Instruction

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4. Memory Read Machine cycle:

OP1: 8085 generates 8 bit Address of

OP3: 8085 receives data byte into

Refer IES-2015 Conventional solutions.

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04. Instruction Set of 8085

A 8 bit microprocessors processing

Sol:(a) ACI 20H--- Immediate Addressing mode

The Addressing mode is Implicit

then parity flag is set to 1. Otherwise,

Auxiliary carry Flag:

The flag Register of Intel 8085 consists of 5

For the execution of MOV D, B

4. Direct Addressing mode:

Mode of specifying address of operand

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5. Indirect addressing mode:

Sol: Initial values: (A) = 95 H, CY = 1

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Sol: CALL instruction is a branch control

Sol: SIM (Set Interrupt Mask) instruction and