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Dear Colleagues,
I am delighted to welcome
you to Austin, Texas, home of
the 53rd Design Automation
Conference. Austin also
happens to be my home for the
past 20 years. In that time, I
have watched the city, known to
many as Silicon Hills, grow into a
technology powerhouse. Austin
is famous for being weird, but
with the arrival of the 53rd Design Automation Conference,
it is now nerdy as well. Over the past year we have
introduced the Keep Austin Nerdy theme for the 53rd
DAC and hope to continue this trend for years to come.
Charles J. Alpert
TABLE OF CONTENTS
General Chairs Welcome 3
Wednesday Keynote 53
Conference Sponsors 5
Wednesday Sessions 54
Important Information 6
Networking Receptions 7
Keynotes 8
Thursday Keynote 71
SKY Talks 10
Thursday Sessions 72
In Memory 12
Colocated Conferences 88
Workshops 18
Additional Meetings 92
Monday Keynote 22
Monday Sessions 23
Monday Tutorials 29
Tuesday Sessions 37
Index 126
CONFERENCE SPONSORS
ACM/SIGDA
ACM is the worlds largest computing society and brings together computing educators,
researchers and professionals to inspire dialogue, share resources and address the fields
challenge. The ACM Special Interest Group on Design Automation has a long history of supporting
conferences and the EDA profession. In addition to sponsoring DAC, SIGDA sponsors ICCAD,
DATE, and ASP-DAC, plus approximately 15 other symposia and workshops. SIGDA provides a
broad array of additional resources to our members, to students and professors, and to the EDA
profession in general. SIGDA organizes the University Research Demo and Ph.D. Forum at DAC,
and the CADathlon at ICCAD, and also funds various scholarships and awards. Other benefits provided to SIGDA members include
the SIGDAs E-Newsletter containing information on upcoming conferences and funding opportunities, SIGDA News highlighting most
relevant events in EDA and semiconductor industry, and the What is...? column that brings to the attention of EDA professionals the
most recent topics of interest in design automation.
special interest group on
design automation
CONFERENCE INFORMATION
BIRDS-OF-A-FEATHER
MEETINGS
EXHIBIT HOURS
LOCATION: EXHIBIT HALLS 1-4
Monday, June 6
10:00am - 6:00pm
Tuesday, June 7
10:00am - 6:00pm
Wednesday, June 8
10:00am - 6:00pm
REGISTRATION HOURS
LOCATION: AUSTIN CONVENTION
CENTER ATRIUM
Friday, June 3 - Sunday, June 5
8:00am 6:00pm
7:00am 7:00pm
ONLINE PROCEEDINGS
STAY CONNECTED
WIRELESS INTERNET
Austin Convention Center has complimentary wireless
internet service throughout the facility.
RECEPTION
Sunday, June 5
5:30 - 7:00pm | 4th Floor Foyer
Tuesday, June 7
6:00 - 7:00pm | Trinity St. Foyer
Investors in InnovationTM
RECEPTION
RECEPTION
Monday, June 6
6:00 - 7:00pm | Trinity St. Foyer
Wednesday, June 8
6:00 - 7:00pm | Trinity St. Foyer
Investors in InnovationTM
Thank You to
Our Sponsor:
DAC SILICON/TECHNOLOGY
ART SHOW
Monday, June 6
6:00 - 7:00pm | Trinity St. Foyer
RECEPTION
Thursday, June 9
5:30 - 6:30pm | 4th Floor Foyer
KEYNOTE PRESENTATIONS
KEYNOTE: REVOLUTION AHEAD
WHAT IT TAKES TO ENABLE SECURELY
CONNECTED, SELF-DRIVING CARS
Lars Reger - Chief Technology Officer of Automotive Business Unit,
NXP Semiconductors, Hamburg, Germany
Monday, June 6 | | 9:15 - 10:00am | | Ballroom A
Few industries are as primed for radical change in the years ahead as the worldwide automotive market. Advanced driver
assistance system (ADAS) features are increasingly common in entry-level/affordable new car models, and todays high-end
vehicles commonly receive over-the-air software updates and feature semi-autonomous driving functionality.
Meanwhile, Silicon Valley start-ups and established auto OEMs alike are rushing to deliver the first true self-driving cars.
See page 22 for more details.
SKY TALKS
SKY TALK: WIRELESS IMPLANTABLE
MICROSYSTEMS: MINIMALLY INVASIVE
INTERFACES TO THE BRAIN
Rikky Muller - Univ. of California, Berkeley & Cortera Neurotechnologies,
Berkeley, CA
Monday, June 6 | | 1:00 - 1:30pm | | DAC Pavilion - Booth 1839
Smart and connected medical implants are the next frontier in the Internet of Things (IoT) and are set to revolutionize
healthcare. Advancing our ability to interface technology with biological environments will enable patients to be monitored and
receive treatment at home, and in the long term, have chronically implanted electronic devices seamlessly integrate with their
everyday lives. As an example, clinically viable and minimally invasive neural interfaces stand to transform disease care for
patients of neurological conditions.
See page 24 for more details.
10
11
IN MEMORY
ERNEST S. KUH | 1928 - 2015
Since June 2015, the design
automation community has
mourned a pioneering scholar,
educator, visionary and mentor.
In Prof. Kuhs honor, CEDA has renamed its IEEE CEDA Early Career Award to IEEE CEDA Ernest S. Kuh Early Career Award.
12
IN MEMORY
STEVEN P. LEVITAN | 1950 - 2016
With a heavy heart, we say
goodbye to Steven P. Levitan,
a kind and inspiring colleague,
a fabulous mentor, a distinctive
educator and researcher, and a
longtime DAC volunteer leader.
13
IN MEMORY
EDWARD J. MCCLUSKEY | 1929-2016
Ed McCluskey, Professor Emeritus
of Electrical Engineering and
Computer Science at Stanford,
was a giant who shaped the design
and testing of digital systems for
over half a century. He sustained
a relentless pace of fundamental
contributions for efficient and
robust design, high-quality testing,
and reliable operation of digital
systems. Ed was also a pioneer
in establishing and fostering computer engineering as a
profession.
Ed and his students developed many key concepts in faulttolerant computing. One example is diverse replication,
logic circuitry implementing alternative structures to check
the main structure, or watchdog processor checking the
main program by executing a related, but simpler, version.
Software diverse redundancy concepts in the ARGOS
mission demonstrated feasibility of commercial off-the-shelf
microprocessors in space applications. Eds fault-tolerance
and testing concepts are even more essential for safety in
future applications such as self-driving cars.
Ed was one of the worlds leading educators. His
textbooks on logic design defined the discipline. Computer
Engineering and the IEEE Computer Society owe their
current status to Ed in a major way. He was first president
of the IEEE Computer Society. At Princeton, Ed established
the Computer Engineering curriculum, and founded the
university computer center in the early 1960s. At Stanford,
he founded the Digital Systems Lab (renamed Computer
Systems Lab) that uniquely cultivated collaboration between
EE and CS. Ed McCluskey was a pioneer in the computer
engineering community, said Stanford President John
Hennessy. He recruited me to Stanford to join the laboratory
in 1977. In addition to shaping the development of digital
systems, he was a great educator, producing an incredible
group of [75] PhD graduates, many of whom have gone on
to become industry leaders. He founded the Center for
Reliable Computing (CRC) at Stanford. CRC played a major
role in advancing the fields of computer reliability and testing
from ad hoc pursuits to frontline academic and industrial
research.
IN MEMORY
MARIE R. PISTILLI | 1933 - 2015
While her critical contribution was in helping the EDA
industry through its early years of rapid and chaotic growth,
perhaps her proudest contribution was in her efforts to
gain recognition for the contributions of women in EDA.
Along with a dedicated group of committee members, she
worked to bring recognition to the many technical and
industrial contributions of women in the evolution of design
automation. While doing so she also worked to establish
connections between women in all stages of their careers.
In honor of her efforts the DAC executive Committee
established the Marie R. Pistilli Women in EDA Achievement
Award, which is awarded at DAC annually since 2001 to an
individual who has a made a significant contribution to the
advancement of women in the field of EDA. She remained
active in these efforts until her death in November, 2015.
15
IN MEMORY
GARY SMITH | 1941 - 2015
This year we lost a visionary in the
field of design automation. Smith
was the best-known industry
analyst in EDA, a leading design
technologist and foremost EDA
strategist. He defined market
segments, tracked market share,
offered market growth projections,
consulted with major EDA providers
and their customers, published
detailed research reports, and
served as a tireless advocate for more efficient ways of
designing chips that may have a billion transistors or
more. A blog post called Smith the single most important
prognosticator in EDA.
Smith was the founder and chief analyst at Gary Smith EDA
(GSEDA) since 2006. Prior to GSEDA, Smith was chief
analyst at Dataquest (later known as Gartner Dataquest)
beginning in 1994.
16
Roland Weber - Concept Engineering GmbH: Two blocks, 128 pins per
side, inverted connection
Sherie Taylor - Intel Corp.: Merrifield Wafer; Skylake Die; Skylake Wafer
Tania Ferla - Univ. Federal do Rio Grande do Sul: Lithographic Simulation
Kernels
ART SHOW
RECEPTION
WORKSHOPS
W1
ORGANIZERS:
W2
SPEAKERS:
Nikil Dutt - Univ. of California, Irvine, CA
Wayne Luk - Imperial College London, United Kingdom
Jonathan Eastep - Intel Corp., Portland, OR
Jian Li - Huawei Technologies Co., Ltd., Austin, TX
Gianluca Durelli - Politecnico di Milano, Italy
Diana Goehringer - Univ. Bochum, Germany
Matteo Ferroni - Politecnico di Milano, Italy
ORGANIZERS:
SPEAKERS:
P.R. Kumar - Texas A&M Univ., College Station, TX
Subhasish Mitra - Stanford Univ., Stanford, CA
Rajesh Gupta - Univ. of California at San Diego, La Jolla, CA
Sachin Sapatenkar - Univ. of Minnesota, Minneapolis, MN
Sharon Hu - Univ. of Notre Dame, IN
David Z. Pan - Univ. of Texas at Austin, TX
Xin Li - Carnegie Mellon Univ., Pittsburgh, PA
Shiyan Hu - Michigan Technological Univ., Houghton, MI
Bei Yu - Chinese Univ. of Hong Kong, China
Chengbin Ma - Shanghai Jiao Tong Univ., Shanghai, China
18
SUNDAY, JUNE 5
W3
ORGANIZERS:
Main topics:
SPEAKERS:
Eugenio Villar - Univ. de Cantabria, Santander, Spain
Kim Grttner - OFFIS Institute for Information Technology,
Oldenburg, Germany
Daniel Lorenz - OFFIS Institute for Information Technology,
Oldenburg, Germany
Ralph Weissnegger - CISC Semiconductor GmbH, Graz, Austria
Laurent Maillet-Contoz - STMicroelectronics, Grenoble, France
Franco Fummi - EDALab s.r.l., Verona, Italy
Emmanuel Vaumorin - Magillem Design Services, Paris, France
Roland Jancke - Fraunhofer IIS, Dresden, Germany
Michael Pronath - MunEDA GmbH, Munich, Germany
Gilson Wirth - Univ. Federal do Rio Grande do Sul, Rio Grande, Brazil
W4
ORGANIZER:
Program Committee:
Farinaz Koushanfar - Univ. of California at San Diego, La Jolla, CA
Peng Li - Texas A&M Univ., College Station, TX
Subhasish Mitra - Stanford Univ., Stanford, CA
David Z. Pan - Univ. of Texas at Austin, TX
Rasit O. Topaloglu - IBM Corp., Hopewell Junction, NY
SPEAKERS:
Pradip Bose - IBM Research, Yorktown Heights, NY
Sandip Ray - Intel Corp., Hillsboro, OR
Martin Saint-Laurent - Qualcomm, Inc., Austin, TX
Edgar Sanchez-Sinencio - Texas A&M Univ., College Station, TX
Hamed Soroush - Real-Time Innovations, Sunnyvale, CA
Vamsi Talla - Univ. of Washington, Seattle, WA
Mohit Tiwari - Univ. of Texas at Austin, TX
Yuan Xie - Univ. of California, Santa Barbara, CA
19
SUNDAY, JUNE 5
W5
ORGANIZERS:
LPIRC 2016 has three tracks. The first two tracks (1) offloading and (2) nonoffloading are the same as in LPIRC 2015. The test images are sent through
a network. In the third, new track, the test images are shown on a computer
screen and the contestants must use cameras to obtain the input images.
The first LPIRC was held at the 2015 Design Automation Conference on
June 7, 2015 in San Francisco, California. Thirty-four people registered
as ten teams from four different countries. In total, twenty solutions were
presented.
A special session at the International Conference on Computer-Aided Design
2015 was devoted to the introduction and description of the first LPIRC.
The top two winners of the first LPIRC presented their solutions.
WELCOME TO AUSTIN!
Austin is the capital of Texas, home of the University of
Texas at Austin and gateway to the beautiful Hill Country.
As the Live Music Capital of the World, the city has a
soundtrack all its own.
More than 250 live music venues flourish with rock, indie,
pop and Tejano. Top notch restaurants with legendary
barbeque and farm-to-table cuisine whet your appetite.
Find out more at austintexas.org.
20
MONDAY, JUNE 6
OPENING SESSION & AWARDS PRESENTATION
Time: 8:45am - 9:15am | | Room: Ballroom A | | Topic Area: General Interest
Join us as we set the stage for the 53rd DAC! DACs Executive Committee will highlight the conferences events, and the award presentations will
recognize success and excellence for individuals in the industry.
Dr. Rhines is being recognized for growing the EDA and integrated circuit
(IC) design industries through his efforts as a leading voice of EDA and for
pioneering the evolution of IC design to system-on-chip (SoC) design.
ACM FELLOW
IEEE FELLOW
ACM FELLOW
IEEE FELLOW
ACM FELLOW
IEEE FELLOW
IEEE FELLOW
Shupeng Sun, Xin Li, Hongzhou Liu, Kangsheng Luo, and Ben Gu
This annual award, named for Marie R. Pistilli, the former organizer of DAC,
recognizes individuals who have visibly helped advance women in Electronic
Design.
Sponsored by the IEEE Council on EDA and the ACM Special Interest Group
on Design Automation.
For pioneering contributions to statistical static timing analysis.
C. Visweswariah, K. Ravindran, K. Kalafala, S. G. Walker, S. Narayan, FirstOrder Incremental Block-Based Statistical Timing Analysis. Proc. of the 41st
Design Automation Conference, pp. 331 336, June 2004.
21
MONDAY, JUNE 6
22
MONDAY, JUNE 6
DESIGN TRACK: CUSTOM HARDWARE FOR ALGORITHMIC TRADING
1
CHAIR:
CHAIR:
23
MONDAY, JUNE 6
3
CHAIR:
SPEAKER:
Rikky Muller - Univ. of California, Berkeley & Cortera Neurotechnologies,
Berkeley, CA
CHAIR:
4.2 Challenges for Next Generation Fog and IoT Computing (2:00)
Mark Douglas - NXP Semiconductors, Austin, TX
4.3 Accelerating and securing Cloud workloads using general
purpose acceleration engines (2:30)
Srini Addepalli - Intel Corp., Santa Clara, CA
Thank You to Our Sponsor:
24
MONDAY, JUNE 6
5
CHAIR:
5.1 End to End Self Heating Analysis Methodology and Toolset for
High Performance Microprocessor Designs (1:30)
Nagu Dhanwada - IBM Corp., Poughkeepsie, NY
Leon Sigal - IBM Research, Yorktown Heights, NY
William Dungan - IBM Corp., Poughkeepsie, NY
Michael Scheuermann - IBM Research, Yorktown Heights, NY
Arun Joseph - IBM Systems and Technology Group, Bangalore, India
Arjen Mets - IBM Corp., Yorktown Heights, NY
Sungjae Lee - IBM Corp., Albany, NY
Karl Moody - IBM Corp., Essex Junction, VT
Shashidhar Reddy - IBM Corp., Bangalore, India
Kartik Acharya - IBM Systems and Technology Group, Sandy Springs, GA
Erich C. Schanzenbach - IBM Corp., Poughkeepsie, NY
Andrew Bianchi - IBM Corp., Austin, TX
Richard Wachnik - IBM Corp., Poughkeepsie, NY
James Warnock - IBM Corp., Yorktown Heights, NY
Derrick Smith - IBM Corp., Austin, TX
5.5 Novel power grid structures for a wire bonded chip (2:30)
Marc DeWilde - Texas Instruments, Inc., Plano, TX
Jason Hoff - Texas Instruments, Inc., Woodruff, WI
5.6 Experimental Characterization of Workload-induced
Logic States on Chip Leakage Power of a Server Class
Microprocessor (2:45)
Arun Joseph, Rahul Rao, Anand Haridass - IBM Systems and Technology
Group, Bangalore, India
Spandana Rachamalla - IBM Corp., Bangalore, India
Diyanesh B. - IBM Systems and Technology Group, Bangalore, India
Q&A Poster Session
Monday, June 6 5:00 - 6:00pm - Exhibit Floor
Thank You to Our Sponsor:
IP TRACK: MIPI ALLIANCE AND IP: A PERSPECTIVE FOR THE MOBILE AND
MOBILE-INFLUENCED MARKETS
Time: 1:30pm - 3:00pm | | Room: Ballroom G | | Event Type: Embedded Tutorial | | Track: IP, Design
Topic Area: General Interest, Business
CHAIR:
ORGANIZER:
Peter Lefkin - MIPI Alliance, Flemington, NJ
This tutorial will provide attendees with:
SPEAKERS:
25
MONDAY, JUNE 6
7
This tutorial will teach a new approach for using modern MPUs more
effectively in C/C++ code. This approach is based on component-level and
object-level data protection. Concrete code examples for the Kinetis MPU
and the ARMv7-M MPU will be presented.
SPEAKER:
German Rivera - NXP Semiconductors, Austin, TX
Thank You to Our Sponsor:
CHAIR:
ORGANIZER:
Yiyu Shi - Univ. of Notre Dame, IN
8.2 A 2.2 GHz SRAM with High Temperature Variation Immunity for
Deep Learning Application under 28nm (4:00)
Chun Chen Liu, Yen-Hsiang Wang, YiLei Li, Chien-Heng Wong,
Tien Pei Chou - Univ. of California, Los Angeles, CA
Young-Kai Chen - Bell Labs, Murray Hill, NJ
M.-C. Frank Chang - Univ. of California, Los Angeles, CA
The Internet of Things (IoT) has become a major driving force behind
technology innovations spanning multiple disciplines. By connecting multiple
IP addressable physical objects embedded with electronics, software,
sensors and connectivity, it achieves smart, reliable and secure services.
It connects many different concepts and applications at different scales,
including but not limited to batteries, wearable devices, cameras and
surveillance, education, logistics, transportation, building, autos and power
grids. This session includes three talks from leading research groups in
academia and industry, showcasing various cutting-edge silicon designs
that push IoT forward. The first talk features an interesting single layer 3D
touch sensing system. The second talk shows a creative 28 nm high speed
range SRAM design for large-scale machine learning in hardware, enabling
compact smart devices. The last talk addresses the topic of energy issue of
the IoT. Here is an interesting idea about how to use the natural signal as the
energy of event trigger in the application of environment monitoring. That will
be an answer to eliminate idle loop power consumption of IoT devices.
CHAIR:
9.2 Analog Driven Power Estimation for Mixed Signal IPs (3:45)
Shovan Maity, Rupak Ghayal, Santosh Nene, Babu Ramki S.
- Intel Corp., Bangalore, India
26
MONDAY, JUNE 6
10
MODERATOR:
PANELISTS:
ORGANIZER:
Farzad Zarrinfar - Mentor Graphics Corp., Fremont, CA
In this panel, implementation techniques and tradeoffs for designing ultra
low-power SOCs, ASSPs, and ASICs will be discussed. These techniques
are critical for battery-powered devices, and other devices that are
sensitive to thermal management as well as reduction of packaging cost. IP
suppliers and EDA vendors now offer low-power IPs as well as advanced
high-level design methodology and emulation to estimate, optimize and
synthesize from C/C++/SystemC to RTL. Topics such as FinFET and FDSOI
processes for low voltage applications will be compared with planar CMOS.
Optimization of these advance techniques for various applications such as
portable gaming, IOT, automotive, sensor hub, 5G/LTE wireless, networking,
portable multimedia, wearable computing will be discussed. Low power
techniques are paramount for gaining and keeping market share.
As the limited time available in the Design/IP Track session program was exceeded by the
quantity of great submitted content, we present the following posters in the Design/IP Track
Poster Session held Monday, June 6 from 5:00 to 6:00pm on the Exhibit Floor.
11.8 Full-Featured Debug Cross Triggering
Eric Rentschler - Mentor Graphics Corp., Steamboat Springs, CO
11.9 Hierarchical Power and IR Drop Analysis for Mega-Size MixedSignal Design
Ralph Chen, Allen Gu, Kitty Chen - Semiconductor Manufacturing
International Corp., Shanghai, China
Xinggang Liu, Xiaoli Chen, Xiaolu Liu, Qianyi Zhang - Cadence Design
Systems, Inc., Shanghai, China
MONDAY, JUNE 6
DESIGN/IP TRACK POSTER SESSION
11.36 Design, Verification and Emulation of an Island-Based
Network Processor
Ron Swartzentruber - Netronome, Boxborough, MA
11.13 System level Signal Integrity effects from shared supply for
DRAM and NAND devices
Cornelia R. Golovanov - Seagate Technology, LLC, Allentown, PA
Pritesh Pawaskar - Seagate Technology, LLC, Pune, India
Chris Ortiz - ANSYS, Inc. & Apache Design, Inc., A Subsidiary of ANSYS,
Inc., San Jose, CA
28
MONDAY TUTORIALS
T1
ORGANIZERS:
The first part of the tutorial will talk about automotive E/E architectures. On
computation side, typical ECUs and the real-time operating systems will be
covered. On networking side, various communication bus protocols such as
Ethernet and CAN will be discussed. Based on this, it will be illustrated how
the performance of automotive E/E architecture is evaluated (using formal
analysis and simulation) in the current state of practice. Finally, current
research challenges will be illustrated with a number of examples.
The second part of the tutorial will talk about various control/architectures
co-design procedure to perform various trade-off analysis between resource
usage and control performance. In particular, we will illustrate how a richer
sampling scheme can be exploited to enable trade-off between the resource
and performance with various automotive use-cases.
In particular, the timing constraints derived from the control design need
to be translated into platform constraints to be satisfied by the controlrelated tasks and messages. In practice, the controller and its embedded
implementation design are often performed in isolation. As pointed out
by some of the recent research results, such design isolation often results
in large resource over-dimensioning which is critical for cost-sensitive
automotive domain.
The third part of the tutorial will talk about control and battery management
system (BMS) co-design in an Electric Vehicle (EV). To be particular, we will
focus on the battery lifetime and efficiency as the design constraints in view
of an industrial use-case of EV climate control. This part will discuss how the
abstraction and complexity of the modeling are important and how it may
affect the control functionality in terms of performance, computation, and
memory resource requirements.
SPEAKERS:
Arne Hamann - Robert Bosch GmbH, Renningen, Germany
Dip Goswami - Eindhoven Univ. of Technology, Eindhoven, The Netherlands
Mohammad Al Faruque - Univ. of California, Irvine, CA
MONDAY TUTORIALS
TUTORIAL 2: LINUX PORTING, BRING UP AND DRIVER DEVELOPMENT
T2
ORGANIZER:
The final section (Imperas) will discuss the development of a robust test
environment using the virtual platform technology. The virtual platform
provides a complementary approach to porting and bring up on hardware.
The benefits of controllability, observability and repeatability for virtual
platform use will be covered. Specific OS-aware tools will also be
highlighted, plus other tools such as non-intrusive memory monitors and the
use of software assertions and code and functional coverage techniques for
the operating system and drivers.
SPEAKERS:
Zubair Lutfullah Kakakhel - Imagination Technologies Ltd., Leeds, United
Kingdom
Henry Von Bank - Posedge Software, Inc., Rogers, MN
Simon Davidmann - Imperas Software Ltd., Thame, United Kingdom
This tutorial will be presented in three sections. In the first section (by
Imagination Technologies), the various components of bringing up Linux
on a new platform will be covered. These include the Bootrom, U-boot
bootloader, Linux Kernel and Linux Buildroot. A walk-through of bringing
up Linux on new hardware will be presented. The walk-through will also
introduce the various tools used to assist in completing board bring-up
easily.
T3
The EDA industry has kept up with the pace and some companies have
recently launched major tool changes that offer higher capacity, turn-aroundtime and many advanced features that are needed for finfet and multipatterning process generations. In this tutorial, we will discuss how physical
design has evolved so far to meet the demand, and our vision for addressing
the needs of designers in the years to come.
MONDAY TUTORIALS
T4
ORGANIZER:
SPEAKERS:
Mon-Ren Chene - S2C, Inc., San Jose, CA
Bruno Bratti - Wave Computing, Campbell, CA
Allen Sha - M31 Technology Corp., Santa Clara, CA
T5
ORGANIZER:
The past decade has seen a great deal of attention and effort focussed
on circuits, architectures and methodologies for energy-efficient and
low power computing across a broad range of applications from ultralow power devices to high-end servers. As designers continue to seek
and evaluate low power technologies to enable the next generation
of computing, the traditionally unheralded problem of voltage margin
minimization has emerged to become one of the most significant
sources of inefficiency and dissipation. Real-world integrated systems
are margined, or guard-banded to address many sources of noise and
variability including process, temperature, aging, and supply voltage noise
and offsets.
SPEAKERS:
Visvesh Sathe - Univ. of Washington, Seattle, WA
Shidhartha Das - ARM Ltd., Cambridge, United Kingdom
31
MONDAY TUTORIALS
TUTORIAL 6: ADVANCES IN POST SILICON DIAGNOSIS TECHNOLOGIES IN
NANO-SCALE ERA
T6
ORGANIZER:
behavior and logical analysis of failures are being incorporated with layout
analysis for finer pruning of diagnosis candidates. Hybrid approach of using
logical simulation in conjunction with circuit simulation resulted in better
isolation of front end and backend defects.
Over the last several years, many innovations have been made and novel
solutions are emerging for better and faster defect isolation. With the
advent of new transistor devices, lithography, and fabrication processes,
the demand for improving the defect isolation and faster yield learning will
continue to grow in coming years.
T7
SPEAKERS:
Shawn Blanton - Carnegie Mellon Univ., Pittsburgh, PA
Enamul Amyeen - Intel Corp., Hillsboro, OR
Srikanth Venkataraman - Intel Corp., Hillsboro, OR
ORGANIZER:
In this context, memory corruption attacks play a vital role. They have
been persisting more than three decades and constitute a pre-dominant
attack vector on diverse computing platforms. Further, they are increasingly
launched against mobile and embedded devices.
While traditional attacks required the attacker to inject malicious code into
the memory space of an application, modern attacks only reuse existing
code. For instance, return-oriented programming combines small code
pieces to generate malicious programs based on benign program code.
Consequently, these attacks are highly challenging to detect, and apply
to Harvard-based architectures because no malicious code needs to be
injected. Traditional exploit mitigation defenses such as data execution
prevention and memory randomization cannot stop these attacks.
SPEAKERS:
Lucas Davi - Technische Univ. Darmstadt, Germany
Ahmad-Reza Sadeghi - Technische Univ. Darmstadt, Germany
MONDAY TUTORIALS
TUTORIAL 8: HOW PORTABLE STIMULUS ADDRESSES KEY VERIFICATION,
TEST REUSE, AND PORTABILITY CHALLENGES
T8
ORGANIZERS:
This tutorial will examine unique portable stimulus challenges such as linking
verification to diagnostics and software, portability to every platform, and
resource management.
The tutorial will outline a set of common usage examples that emphasize
specific verification, reuse, and portability challenges. Verification challenges
include randomization of both data and control flow. Reuse challenges
include migrating tests from IP level to SoC. Portability challenges include
growing tests to improve coverage when running on faster platforms and
executing at the full platform speed. Finally, the tutorial will show how
portable stimulus can address the usage examples.
Portability of reusable test cases has long been a goal for semiconductor
verification and validation teams. No one wants to reinvent the wheel
by having to rewrite similar tests again and again. The widely accepted
Accellera Universal Verification Methodology (UVM) standard enabled reuse
of testbench components and constrained-random tests at the IP and block
level, but limitations in terms of reuse at subsystem and full-chip level,
and lack of portability across execution platforms, required a fresh look at
addressing the portable stimulus and test challenge.
SPEAKERS:
Faris Khudakjie - Intel Corp., Hudson, MA
Adnan Hamid - Breker Verification Systems, Inc., San Jose, CA
Tom Fitzpatrick - Mentor Graphics Corp., Wilsonville, OR
Steve Chappell - Synopsys, Inc., Mountain View, CA
Sharon Rosenberg - Cadence Design Systems, Inc., San Jose, CA
MONDAY TUTORIALS
TUTORIAL 9: ENERGY-EFFICIENT PROTOCOLS FOR THE INTERNET OF
THINGS
T9
ORGANIZER:
The Internet of Things has become the Internet of Everything and the
Internet of All Things. It is predicted that by the end of 2020, the number
of smart objects globally connected will reach 212 billions. Machine-tomachine (M2M) internet traffic is expected to reach up to 45% of all internet
traffic. By its universal and all-inclusive nature, IoT growth over the past 5
years has been enabled by the development, design, and implementation of
a heterogeneous set of data communication architectures.
In its simplest and most direct form, the IoT communication stack is
comprised of three layers: the sensor/actuator layer, the network layer, and
the service layer.
5. IoT networking:
a. Routing protocols for low-power and lossy networks: RPL.
b. Physical layer: IEEE 802.15.4, 6LowPAN, BlueTooth Low Energy,
ZigBee, EPCglobal, Z-wave, IEEE 802.11 (WiFi), Ethernet, MoCA, etc.
c. Physical link metrics: energy-efficiency, data rate, footprint, M2M
synchronization, clock-data recovery, etc.
d. Emerging technologies: 5G, LoRA, sub-GHz, PIC, etc.
e. IoT networking metrics: range, data rate, power, reliability, cost
For each of these layers, many, sometimes too many, protocols and
standards have been proposed and implemented with some being derived
from existing networking and data communication protocols, including those
of the Internet of People, while others are novel and meant to address the
specific technical issues of the M2M internet.
The objective of this tutorial is to help the DAC audience make sense of the
alphabet soup of platforms, protocols, standards, services, and architectures
currently in use or under development for IoT.
The tutorial will take a holistic view of IoT with the goal of providing the
attendees with the essential information needed to configure an IoT service,
comprising a physical layer, a communication layer, and a software layer.
Such configuration will of course depend on the IoT use case itself and
several real-world use cases will be presented.
SPEAKERS:
Ibrahim (Abe) Elfadel - Masdar Institute of Science and Technology,
Abu Dhabi, United Arab Emirates
Kwok Wu - NXP Semiconductors, Austin, TX
MONDAY TUTORIALS
T10
ORGANIZER:
SPEAKERS:
WELCOME TO AUSTIN!
Austin is the capital of Texas, home of the University of
Texas at Austin and gateway to the beautiful Hill Country.
Shop in the one-of-a-kind boutiques that line South
Congress and the 2nd Street district, or head out to hill
country to relax in a world class destination spa.
TUESDAY, JUNE 7
VISIONARY TALK: LEARNING FROM LIFE:
BIOLOGICALLY INSPIRED ELECTRONIC DESIGN
TUESDAY, JUNE 7
12
CHAIR:
CO-CHAIR:
Andreas Herkersdorf - Technische Univ. Mnchen, Germany
This session gives new perspectives on processor systems. The first paper
demonstrates that power and performance of one processor model can be
inferred from performance counters of another. The second paper partitions
shared cache resources in an integrated CPU-GPU system by observing
that while some applications may not benefit from additional cache
resources, allocating too few resources can degrade the performance of
other concurrent applications. The third presentation proposes an improved
memory-queue management for real-time applications. The final work
introduces a debugging aid based on co-simulation.
13
CHAIR:
CO-CHAIR:
Zhuo Feng - Michigan Technological Univ., Houghton, MI
37
TUESDAY, JUNE 7
PREVENTING AND EXPLOITING ERRORS
14
CHAIR:
CO-CHAIR:
Miroslav Velev - Aries Design Automation, LLC, Chicago, IL
The four papers in the session present exciting recent work on fault
tolerance and approximate computing. The first paper proposes a method
for exploiting reliability-aware design to suppress aging. The second paper
describes techniques for using statistical fault injection in order to evaluate
the impact of timing errors on application performance with a case study for
an OpenRISC core. The third paper presents an energy-efficient approximate
serial encoding for sensor data, inspired by the T0 encoding technique for
parallel buses. The fourth paper studies the use of clock overgating for
designing approximate circuits.
15
CHAIRS:
ORGANIZERS:
Yuan Xie - Univ. of California, Santa Barbara, CA
Jishen Zhao - Univ. of California, Santa Cruz, CA
38
TUESDAY, JUNE 7
16
CHAIR:
The session will first overview the needs of heterogeneous systems and
present a computer-vision application. The second talk addresses the
growth of FPGA-based acceleration in heterogeneous data centers and
the resulting programming challenges. The last talk proposes a new
class of computing platforms to simplify the design and programming of
heterogeneous SoCs for embedded applications.
ORGANIZER:
Luca Carloni - Columbia Univ., New York, NY
For most classes of computing systems the distinction between low-power
and high-performance design is outdated: from smartphones to cloud
servers, systems-on-chip must deliver both. At the tail end of Dennards
scaling, this is becoming an increasingly tall order. Meanwhile, the limits
of application parallelism prevents computer architects from scaling up
performance by simply integrating more homogeneous processor cores.
Instead, the quest for energy-efficient performance requires the integration
of a variety of computing engines, including different kinds of processors
and many specialized-hardware accelerators, leading to the rise of
heterogeneous architectures.
17
CHAIR:
CO-CHAIR:
39
TUESDAY, JUNE 7
18
CHAIR:
18.5 Fabric: Mobile SOC Chip Level Aging Design Methodology for
Advanced FinFET Technologies (11:30)
Yiwei Fu, Yongsheng Sun, Jianping Guo, Canhui Zhan, Jun Xia
- HiSilicon, Shenzhen, China
Junhui Zhao, Teong Ming Cheah - ANSYS, Inc., Shenzhen, China
19
CHAIR:
40
TUESDAY, JUNE 7
20
MODERATOR:
PANELISTS:
ORGANIZER:
Heather Monigan - Intel Corp., Chandler, AZ
In this panel, the panel participants are asked to contemplate and comment
on the year-over-year trend of smaller commercial IP companies being
gobble up by larger, more established companies. The Commercial IP
Ecosystem is growing, and projected to sustain growth, yet the pool seems
smaller, year over year. Is this current trend a hindrance or catalyst for
innovation? What challenges would IP companies expect when swimming
in these waters? What conditions may repopulate the pool? Who ultimately
prospers: the investors or end customers?
21
SPEAKER:
Krste Asanovic - Univ. of California, Berkeley & SiFive, Inc., Berkeley, CA
CHAIR:
CO-CHAIR:
David Z. Pan - Univ. of Texas at Austin, TX
This session covers the state-of-the-art in neuromorphic computing,
machine learning and image processing implementations in hardware using
both conventional CMOS and emerging technologies.
TUESDAY, JUNE 7
22
CHAIR:
CO-CHAIR:
Harry Foster - Mentor Graphics Corp., Plano, TX
CHAIR:
CO-CHAIR:
Huafeng Yu - Toyota InfoTechnology Center, Mountain View, CA
Modern automotive systems need to meet the challenges of autonomous
driving by precise localization, effective detection and identification of the
road and the surrounding objects, as well as deterministic and predictable
timing.
The four papers in this session provide innovative solutions for the problem
of efficient sensor processing; predictable and reliable transmission of data
over Ethernet; caching policies that allow for probabilistic timing analysis;
and secure and accurate localization.
* Indicates Best Paper Candidate
42
TUESDAY, JUNE 7
24
CHAIRS:
ORGANIZER:
25
CHAIR:
25.1 Additively Manufactured Wireless Self-Powered (EnergyHarvesting) Platforms for Communication, Sensing and Radar
Applications (1:30)
Manos M. Tentzeris - Georgia Institute of Technology, Atlanta, GA
ORGANIZER:
Rob Aitken - ARM, Inc., San Jose, CA
CHAIR:
ORGANIZER:
Ramesh Karri - New York Univ., Brooklyn, NY
43
TUESDAY, JUNE 7
27
CHAIR:
The speakers in this session are industry leaders from foundry, library and
design arenas. They will address the prevalent and emerging problems in
electrical sign-off, and the solution strategies being developed and deployed
within their purview.
28
CHAIR:
SPEAKERS:
ORGANIZER:
Rick OConnor - RISC-V Foundation, Berkeley, CA
This session consists of a brief RISC-V Overview followed by four tutorial
presentations covering the following:
1. RISC-V Overview
2. RISC-V Tool chain & OS environment
3. RISC-V Security Enhancements using Bluespec
4. RISC-V Rocket Core using Xilinx FPGAs
44
TUESDAY, JUNE 7
29
CHAIR:
CO-CHAIR:
Paul Gratz - Texas A&M Univ., College Station, TX
This session is composed of six presentations exploring new applications
and technologies for Networks-on-Chip. Innovative architectures, memory
solutions and data compression, as well as new networks based on photonic
technology are discussed. The presented solutions consider key metrics
such as energy-efficiency, process variation, cross-talk, data congestion and
latency.
29.5 Achieving Lightweight Multicast in Asynchronous Networkson-Chip Using Local Speculation (4:30)
Kshitij Bhardwaj, Steven M. Nowick - Columbia Univ., New York, NY
29.6 PICO: Mitigating Heterodyne Crosstalk Due to Process
Variations and Intermodulation Effects in Photonic NoCs (4:45)
Sai Vineel Reddy Chittamuru, Ishan Thakkar, Sudeep Pasricha Colorado State Univ., Fort Collins, CO
30
CHAIR:
CO-CHAIR:
Saurabh Sinha - ARM, Inc., Austin, TX
While there seem to be many unsurmountable challenges in the More-Moore
age, there is also a growing number of solutions to meet the demands of
circuit design and manufacturing. This session covers many probable
DFM and reliability analysis techniques with provable outcomes, from
multi-patterning and directed self-assembly, to dielectric breakdown,
electromigration and soft errors due to cosmic rays.
45
TUESDAY, JUNE 7
31
CHAIR:
Oliver Bringmann - Eberhard Karls Univ. Tubingen, Germany
CO-CHAIR:
Jian-Jia Chen - Technische Univ. Dortmund, Germany
Reliability and performance are critical concerns for modern embedded
system software. This session presents novel compiler and run-time
techniques for improved device reliability, protection from soft errors, onchip thermal management, and reduced aging. The session also introduces
approaches for maximizing system performance by advanced compilation
and dynamic scheduling methods for automatic code parallelization,
optimized multi-threading, effective timing speculation, and improved energy
savings in mobile devices.
* Indicates Best Paper Candidate
31.1 ageOpt-RMT: Compiler-Driven Variation-Aware Aging
Optimization for Redundant Multithreading (3:30)
Florian Kriebel - Karlsruhe Institute of Technology, Karlsruhe, Germany
Semeen Rehman - Technische Univ. Dresden, Germany
Muhammad Shafique, Jrg Henkel - Karlsruhe Institute of Technology,
Karlsruhe, Germany
31.2 Improving Mobile Gaming Performance through Cooperative
CPU-GPU Thermal Management* (3:45)
Alok Prakash - National Univ. of Singapore, Singapore
Hussam Amrouch, Muhammad Shafique - Karlsruhe Institute of Technology,
Karlsruhe, Germany
Tulika Mitra - National Univ. of Singapore, Singapore
Jrg Henkel - Karlsruhe Institute of Technology, Karlsruhe, Germany
32
MODERATOR:
Edward Sperling - Semiconductor Engineering, San Jose, CA
ORGANIZER:
Laura Parker - Mentor Graphics Corp., Portland, OR
It is an exciting time in packaging, with new approaches emerging
continuously. The driving force is to support consumer, mobile applications
that require thinner, higher density packages without sacrificing the
performance of the IC. The emergence of the Internet of Things (IoT) will only
increase the pressure for continued innovation in packaging.
33
Today there is a wide range of packaging including: Wafer Level Chip Scale,
Wafer Level Fan Out, Panel Level Fan Out, Chip Last Fan Out, Flip Chip,
interposer 2.5D, 3D and the list goes on and on. So will one win out or can
the ecosystem continue to support an ever broadening range of styles and
custom approaches? This panel will present views on this pressing issue
from the designer perspective, packaging, tools, and foundry.
PANELISTS:
John Hunt - ASE Inc., Tempe, AZ
David Z. Pan - Univ. of Texas at Austin, TX
Max Min - Samsung Electronics Co., Ltd., Milpitas, CA
MODERATOR:
Shawn Blanton - Carnegie Mellon Univ., Pittsburgh, PA
ORGANIZER:
Rob Aitken - ARM, Inc., San Jose, CA
Design-for-testability (DFT) has progressed over the last 25 years from an
expensive adder to be included only if quality demanded it to a mandatory
feature of every design. High quality tools are available from EDA vendors
and there is a substantial and diverse body of research behind them. Still,
when most people think of DFT, they think of scan chains, and scan-based
DFT seems to be a done deal.
Given that, what is the future of the DFT business? There are many
challenges that get lumped together as part of test (yield, performance/
power characterization/optimization, debug/diagnosis/validation, analog
measurement, DFM compliance, etc.), so DFT is more than just building
scan chains, but is that where the future lies? The panel looks at the issues
and explores how we might expect the DFT business to evolve going
forward.
PANELISTS:
Jeff Rearick - Advanced Micro Devices, Inc., Fort Collins, CO
Joe Sawicki - Mentor Graphics Corp., Wilsonville, OR
Anne Gattiker - IBM Research, Austin, TX
David Park - Optimal Plus Inc., San Jose, CA
TUESDAY, JUNE 7
34
CHAIR:
ORGANIZER:
Rolf Ernst - Technische Univ. Braunschweig, Germany
Next-generation vehicular networks are anticipated to comprise a single
high-bandwidth communication backbone, which is used by both
critical and non-critical traffic. These networks require advanced safety
mechanisms, such as isolation between different criticality levels and
fail-operational network behavior to provide a reliable communication
infrastructure, e.g. for highly automated and autonomous driving.
In the future, vehicular networks will even extend beyond the individual
vehicle. In vehicle-to-vehicle and vehicle-to-infrastructure scenarios, cars
become part of a larger network. Connected vehicles have strict security
requirements to guarantee authenticity, integrity, and confidentiality of the
data entering and leaving the vehicle.
35
MODERATOR:
PANELISTS:
Alex Starr - Advanced Micro Devices, Inc., Boxborough, MA
Frank Schirmeister - Cadence Design Systems, Inc., San Jose, CA
Ronny Morad - IBM Research - Haifa, Israel
Stephen Bailey - Mentor Graphics Corp., Longmont, CO
Dave Kelf - OneSpin Solutions GmbH, San Jose, CA
47
TUESDAY, JUNE 7
36
CHAIR:
ORGANIZER:
37
CHAIR:
48
TUESDAY, JUNE 7
During the poster presentation, you will interact directly with poster presenters in a
small group setting.
As the limited time available in the Design/IP Track session program was exceeded by the
quantity of great submitted content, we present the following posters in the Design/IP Track
Poster Session held Tuesday, June 7 from 5:00 to 6:00pm on the Exhibit Floor.
38.13 Power and Test Time reduction through Codec Sharing and
Core Wrapping
Shiv K. Vats - STMicroelectronics, Greater Noida, India
Rahul Anand - Synopsys, Inc. & Synopsys India Pvt. Ltd., Hyderabad, India
Marco Casarsa - STMicroelectronics S.R.L., Agrate Brianza, Italy
Salvatore Talluto - Synopsys Italia S.R.L., Agrate Brianza, Italy
Harish Kumar - STMicroelectronics, Greater Noida, India
49
TUESDAY, JUNE 7
DESIGN/IP TRACK POSTER SESSION
38.40 Planning and Empowering Hierarchical Testing of ASICs
Kavitha Shankar, Hardik Bhagat - GLOBALFOUNDRIES, Bangalore, India
Kelly A. Ockunzzi - GLOBALFOUNDRIES, Essex Junction, VT
Richard Grupp - GLOBALFOUNDRIES, Burlington, VT
TUESDAY, JUNE 7
WORK-IN-PROGRESS POSTER SESSION
100.23 Bi-objective Optimization of Performance and Energy for
Applications Mapping on CGRAs
Jiangyuan J. Gu, Shouyi Yin, Leibo L. Liu, Shaojun S. Wei - Tsinghua
Univ., Beijing, China
TUESDAY, JUNE 7
WORK-IN-PROGRESS POSTER SESSION
100.46 The Design and Implementation of a 4Kb STT-MRAM with
Innovative 200nm Nano-ring Shaped MTJs
Zheng Li, Xiuyuan Bi - Univ. of Pittsburgh, PA
Jianying Qin, Peng Guo, Wenjie Kong, Wenshan Zhan, Xiufeng Han Chinese Academy of Sciences, Beijing, China
Hong Zhang, Lingling Wang, Hanming Wu - Semiconductor Manufacturing
International Corp., Shanghai, China
Hai Li, Yiran Chen - Univ. of Pittsburgh, PA
52
WEDNESDAY, JUNE 8
KEYNOTE: THE CHALLENGE TO DEVELOP
TRULY GREAT PRODUCTS
Mark Papermaster - Advanced Micro Devices, Inc., Sunnyvale, CA
T
ime: 9:00am - 10:00am | | Room: Ballroom A | | Track: Design, EDA
Topic Area: General Interest
Biography: Mark Papermaster is chief technology officer
and senior vice president at AMD, responsible for corporate
technical direction, and AMD intellectual property (IP) and
system-on-chip (SOC) product research and development.
His more than 30 years of engineering experience includes
significant leadership roles managing the development of
a wide range of products, from mobile devices to highperformance servers. Before joining AMD in October 2011,
Papermaster was the leader of Ciscos Silicon Engineering
Group, the organization responsible for silicon strategy,
architecture, and development for the companys switching
and routing businesses.
53
WEDNESDAY, JUNE 8
39
CHAIR:
CO-CHAIR:
Janet Meiling Roveda - Univ. of Arizona, Tucson, AZ
40
CHAIR:
40.1 Efficient Probing Schemes for Fine-Pitch Pads of InFO WaferLevel Chip-Scale Package (10:30)
Yu-Chieh Huang, Bing-Yang Lin, Cheng-Wen Wu - National Tsing Hua
Univ., Hsinchu, Taiwan
Mincent Lee, Hao Chen, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, Taiwan
54
WEDNESDAY, JUNE 8
41
CHAIR:
CO-CHAIR:
Hyung Gyu Lee - Daegu Univ., Republic of Korea
Continued scaling and developments in memory devices impose significant
challenges on using these devices in practice. This session tackles some
of the most prominent limitations faced in the field today, in terms of
performance, reliability and power, contributing real-world solutions for
real-world challenges. The topics include reducing power through lossy
encoding, improving lifetime and performance of NAND storage, prefetching
in coarse-grain reconfigurable architectures, and partitioning memory for
better bandwidth utilization in GPUs.
42
CHAIR:
ORGANIZER:
55
WEDNESDAY, JUNE 8
43
CHAIR:
ORGANIZER:
44
CHAIR:
56
WEDNESDAY, JUNE 8
45
CHAIR:
46
CHAIR:
57
WEDNESDAY, JUNE 8
47
MODERATOR:
PANELISTS:
ORGANIZER:
Priyank Shukla - Cadence Design Systems, Inc., San Jose, CA
Open source code transformed software development, and spawned makers
with low-cost hardware modules, mostly running on proprietary chips. Large
systems are moving toward open source - still, mostly on proprietary chips.
Open source processor core IP is now causing a stir. Is open an inevitable
future for chips, a change the industry needs? Does co-optimizing open
source software and hardware IP have benefits, pre-silicon? Or is open
source IP a distraction, a model that will not work on a large scale? What
lessons from other open efforts may help decide? Our panel will share their
experience, observations, and predictions.
48
SPEAKER:
Bryan Payne - Netflix, Los Gatos, CA
CHAIR:
Franco Fummi - Univ. of Verona, Italy
CO-CHAIR:
Massimo Poncino - Politecnico di Torino, Italy
The session presents novel solutions to enable more accurate modeling and
analysis of power and reliability aspects of a design. The presentations range
from surveying techniques for reliability and soft-errors, to modeling shortterm aging effects and STT-RAM devices, and extensions to architectural
simulators to model power-supply noise.
* Indicates Best Paper Candidate
48.1 CLEAR: Cross-Layer Exploration for Architecting Resilience
- Combining Hardware and Software Techniques to Tolerate Soft
Errors in Processor Cores (1:30)
Eric Cheng - Stanford Univ. Stanford, CA
Shahrzad Mirkhani - Stanford Univ. & Univ. of Texas at Austin, Stanford, CA
Lukasz Szafaryn - Univ. of Virginia, Charlottesville, VA
Chen-Yong Cher - IBM T.J. Watson Research Center, Yorktown Heights, NY
Hyungmin Cho - Stanford Univ., Stanford, CA
Kevin Skadron, Mircea R. Stan - Univ. of Virginia, Charlottesville, VA
Klas Lilja - Robust Chip Inc., Pleasanton, CA
Jacob Abraham - Univ. of Texas at Austin, TX
Pradip Bose - IBM T.J. Watson Research Center, Yorktown Heights, NY
Subhasish Mitra - Stanford Univ., Stanford, CA
WEDNESDAY, JUNE 8
DR. GARBLE AND MR. LEAKAGE IN THE MYSTERY OF SECURE CPUs
49
CHAIR:
CO-CHAIR:
Daniel Holcomb - Univ. of Massachusetts, Amherst, MA
This session highlights the urgency of addressing information leakage from
processors. It presents leakage prevention techniques such as garbled
processor architectures, cache partitioning and cryptographic control flow
integrity.
50
CHAIR:
CO-CHAIR:
Chen-Yong Cher - IBM T.J. Watson Research Center,
Yorktown Heights, NY
Dennard scaling has stopped, but Moores law must march on! Several
technology alternatives are competing to take the crown as successor to
traditional CMOS, but each brings a host of new circuit design challenges.
This session presents four such alternatives along with their risks and
circuit solutions: near threshold FinFETs, monolithic 3D integration, voltage
stacking, and ultra-thin body FD-SOI.
59
WEDNESDAY, JUNE 8
51
MODERATOR:
PANELISTS:
ORGANIZER:
William Joyner - Semiconductor Research Corp., Durham, NC
Though cybersecurity has focused on software vulnerability, recent attacks
on the bare metal have brought increased attention to protecting the
hardware itself: from counterfeiters, from malicious companies/governments,
from disgruntled engineers, and from a host of other sources. Research
efforts to characterize and address hardware attacks are now beginning to
bear fruit.
CHAIR:
ORGANIZERS:
Michael Huebner - Ruhr Univ. Bochum, Germany
Dirk Ziegenbein - Robert Bosch GmbH, Renningen, Germany
53
CHAIR:
60
WEDNESDAY, JUNE 8
54
CHAIR:
ORGANIZER:
Harry Chen - MediaTek, Inc., Hsinchu, Taiwan
From the smartphones of today to the highly connected and smart IoT world
of tomorrow, wireless mobility and energy efficiency have risen to become
essential and dominant requirements. To deliver products and services that
offer fulfilling user experiences, ever deeper collaboration among ecosystem
players is called for. This is occurring while the underlying semiconductor
technology continues to advance and evolve in greater complexity from
devices to packaging to systems. An open platform of capabilities across
the system stack holds the potential to allow creation of optimized solutions
in the most cost-effective and flexible manner.We propose a special session
of three invited talks by ecosystem players to explore aspects of such a
collaborative design environment with focus on energy efficiency.
The players come from different layers of the system stack.
55
CHAIR:
ORGANIZER:
Richard Wawrzyniak - Semico Research Corp., Phoenix, AZ
SPEAKERS:
The session will consider the following aspects of the emerging the IP
Subsystem market.
Drivers and market forces that have combined to prompt the creation of
the IP Subsystem concept
Evolution of the IP Subsystem market
Benefits of IP Subsystems
Cons of IP Subsystems
IP Subsystem Vendor Landscape
Categories of IP Subsystems
Examples of IP Subsystems
Impacts on complex SoC silicon and software design costs and design
time
Solving real world problems with IP Subsystems
Where does the IP Subsystem concept go from here and how do we get
there?
61
WEDNESDAY, JUNE 8
56
CHAIR:
CO-CHAIR:
Wen-Hao Liu - Cadence Design Systems, Inc., Austin, TX
From floorplanning to routing, traditional physical design methodologies
are being challenged with increasingly complex and diverse constraints
brought about by the constant drum of feature scaling. This session focuses
on digital and analog design closure in the nanometer regime. The session
starts with a new floorplanning representation for analog layout designs,
and then moves to timing-driven placement via flip-flop and clock buffer
movement. Clock power for high-performance designs is then minimized
via flip-flop clustering and placement. This is followed by legalization and
detailed placement for advanced nodes handling multi-row height cells
and minimum implant area constraints. The session concludes with a layer
assignment algorithm for timing optimization.
57
CHAIR:
CO-CHAIR:
Seetharam Narasimhan - Intel Corp., Hillsboro, OR
Globalization of the semiconductor supply chain introduces vulnerabilities
in hardware designs such as hardware Trojans, IP piracy, and cloning.
Concurrently, there has been a rise in the ingenuity of attackers to exploit
them. This session is an assortment of attacks and defenses. The attacks
include Trojan-infected power management units, reverse engineering and
EM-based fault injection. The defenses range from high-level synthesis
for protection against Trojans, automated vulnerability analysis of finite
state machines, preventing reverse engineering in STT-CMOS designs,
PLL-based countermeasures against fault injection, and remote device
attestation.
57.1 Catching the Flu: Emerging threats from a Third Party Power
Management Unit (3:30)
Rajesh JayashankaraShridevi, Chidhambaranathan Rajamanikkam,
Sanghamitra Roy, Koushik Chakraborty - Utah State Univ., Logan, UT
62
WEDNESDAY, JUNE 8
58
CHAIR:
CO-CHAIR:
Fadi Kurdahi - Univ. of California, Irvine, CA
This session discusses hardware designs for CPS systems in terms of
optimizing the memory hierarchy and compute capabilities. The first three
papers investigate adaptations of the memory hierarchy using emerging
technologies and controlling the path to memory. The second set of papers
aims to improve compute efficiency, targeting mobile computer vision,
correcting approximate adders, and approximate bitcoin mining.
MODERATOR:
Keeping track of the various IPs created at the different business units and
locations has been equally challenging. In addition, new languages such
IP-XACT (IEEE 1685) were developed by a consortium of semiconductor
companies, but failed to make major headway among the designer
community (although IP providers have started using this as a means for
distributing IPs). This panel aims to see whether we oversold IP reuse.
PANELISTS:
Lisa Minwell - eSilicon Corp., Austin TX
Rwik Sengupta - Samsung Semiconductor, Inc., Austin, TX
Ranit Adhikary - ClioSoft, Inc., Fremont, CA
John Koeter - Synopsys, Inc., Austin, TX
63
WEDNESDAY, JUNE 8
60
MODERATOR:
ORGANIZER:
Rob Aitken - ARM, Inc., San Jose, CA
PANELISTS:
61
CHAIRS:
ORGANIZERS:
Muhammad Shafique - Karlsruhe Institute of Technology, Karlsruhe,
Germany
Jrg Henkel - Karlsruhe Institute of Technology, Karlsruhe, Germany
64
SUNDAY
3:00pm
4:00pm
5:00pm
S
P
Exhibit Floor
Hardware
Advances in Post Silicon Diagnosis Custom
Technologies
in for Algorithmic TradingAdvances in Post Silicon Diagnosis Technologies in
Nano-Scale Era - Part 2
8:00am
9:00am
SUNDAY
T1
T2
T3
T4
T5
MONDAY
1
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7 00pm
T10
Booth 1839
Taming the Dark Horse: Voltage-Margin
Minimization for Modern Real-World Energy-Efficient
Computing
Taming t
tion for M
Computi
T3
Overcoming Challenges of
FPGAPavilion
Prototyping
DAC
5 00pm
Overcom
T6
6Panels
00pm
Inflection
Future
T8
Linux Po
Developm
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Model-B
Cyber Ph
T7
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Ballroom F
Linux Porting, Bring Up and Driver
A
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2:00pm
17AB
7:00pm
T5
7:00pm
11:00
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MONDAY
17AB
10:00am
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TUESDAY
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T8
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19
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17
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24
25
Embedded
Tutorials
Reviewed
9:00am
10:00am
9:00am
10:00am
Presentations
26
29
30
27
18
8:00am
Designing with RISC-V
8:00am
Embedded Software for Reliability and Performance
The Challenge to Develop
31
20
Automotive System
11:00
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H
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19
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Awards
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Presentation
15G
Planar to FinFET
and Exploiting Errors
Ch ng D ng MPreventing
Effective Use of a Memory Protection Unit (MPU) in
17AB
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C/C++ CODE Op n S u 2:00pm Winning the Memory Challenge:
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3:00pm
10
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WEDNESDAY, JUNE 8
DESIGN TRACK: ITS A POWER GAME
62
CHAIR:
62.3 Successive evolution: Tips and tricks for UPF based Low
Power verification (4:00)
Deepmala Sachan, Thameem Syed S. - Intel Corp., Bangalore, India
62.4 Efficient Techniques for Per Clock Gating Domain Contributor
based Power Abstraction of IP Blocks for Hierarchical Power
Analysis (4:15)
Arun Joseph - IBM Systems and Technology Group, Bangalore, India
Nagu Dhanwada - IBM Corp., Poughkeepsie, NY
Spandana Rachamalla - IBM Corp., Bangalore, India
William Dungan - IBM Corp., Poughkeepsie, NY
Ricardo Nigaglioni - IBM Systems and Technology Group, Austin, TX
63
Tcl has been the language of design-automation since its inception in the
1980s. Tcls dominance is due in part to the ease of extending the language
by exposing existing C/object code and the availability of Tk for graphics
extension. As a language, it has relatively few firm syntax rules and can be
described as a nested string processor. That minimal syntax has led many
EDA engineers to learn just-enough of the language for the job at hand.
That minimized knowledge unfortunately leads users to develop coding
patterns that are not robust or even dangerous in large systems. The tutorial
will give a firm grounding to EDA users to develop code that works all of the
time instead of most of the time. It will discuss Tcl features that make coding
in Tcl more productive and will describe patterns to build complex EDA flows
and systems in Tcl.
65
WEDNESDAY, JUNE 8
64
CHAIR:
64.1 Fast and Furious: Keeping Pace with the Trends in Automotive
Architecture (3:30)
Jason Jones - Texas Instruments, Inc., Houston, TX
ORGANIZERS:
As the limited time available in the Design/IP Track session program was exceeded by the
quantity of great submitted content, we present the following posters in the
Design/IP Track Poster Session held Wednesday, June 8 from 5:00 to 6:00pm on
the Exhibit Floor.
65.5 Perforance Optimization without Area and Power Penalties in
Auto P&R Flow
Wootae Kim - Samsung Electronics Co., Ltd., Hwaseong-si, Republic of Korea
Hyung-Ock Kim, Jung Yun Choi - Samsung Electronics Co., Ltd., Yong-in,
Republic of Korea
65.7 A Methodology to Design Early and Efficient PowerDistribution-Network for Power-Gated Designs
Abhishek Mittal - Broadcom Corp., Banagalore, India
Anusha Gummana, Dileesh Jostin - ANSYS, Inc., Bangalore, India
WEDNESDAY, JUNE 8
DESIGN/IP TRACK POSTER SESSION
65.19 Early and Efficient Approach to Model Power & IR analysis
for Multimillion SOC using RTL VCD
Vaishali V. Huilgol, Shashank Bhonge, Jayanth Bandaru - Xilinx Inc.,
Hyderabad, India
67
WEDNESDAY, JUNE 8
WEDNESDAY, JUNE 8
WORK-IN-PROGRESS POSTER SESSION
101.32 Simultaneous Discrete Finite Automata for Wildcard Pattern
Matching by Separated nvTCAM Search Engines
Hsiang-Jen Tsai, Chien-Chih Chen, Keng-Hao Yang - National Chiao Tung
Univ., Hsinchu, Taiwan
Tay-Jyi Lin - National Chung Cheng Univ., Chiayi, Taiwan
Yen-Ning Chiang, Wei-Cheng Zhao, Meng-Fan Chang - National Tsing Hua
Univ., Hsinchu, Taiwan
Tien-Fu Chen - National Chiao Tung Univ., Hsinchu, Taiwan
101.42 Improving Performance and Energy Efficiency of STTMRAM-Based Handheld Platforms Under Read Disturbance
Hao Yan - Univ. of Texas at San Antonio, TX
Lei Jiang - Advanced Micro Devices, Inc., Austin, TX
Lide Duan - Univ. of Texas at San Antonio, TX
69
WEDNESDAY, JUNE 8
WORK-IN-PROGRESS POSTER SESSION
101.49 INsight: A Neuromorphic Computing System for Evaluation
of Deep Neural Networks
Jaeyong Chung, Taehwan Shin, Yongshin Kang - Incheon National Univ.,
Incheon, Republic of Korea
WELCOME TO AUSTIN!
Austin is home to world-class museums, unique attractions,
diverse nightlife, and stunning outdoor spaces.
70
THURSDAY, JUNE 9
DAC BEST PAPER AWARD PRESENTATION
Time: 9:00am - 9:10am | | Room: Ballroom A
DAC will present the research Best Paper Award as well as the Design/IP Track Best Presentation Awards.
71
THURSDAY, JUNE 9
66
CHAIR:
CO-CHAIR:
Jaeha Kim - Seoul National Univ., Seoul, Republic of Korea
Device mismatch and process variations are critical issues in analog and
RF design. This session begins with novel results in automated layout
generation and capacitor placement, followed by the design of SAR ADC
with self-learning techniques, and concludes with a statistical selection
method for design calibration.
67
CHAIR:
CO-CHAIR:
Phillip Stanley-Marbell - Massachusetts Institute of Technology, Cambridge,
MA
Improving energy efficiency requires considerations across different layers,
from device to circuit and architecture. The first two papers in this session
describe a low-power divider and a JPEG encoder under the approximate
computing paradigm. The third paper presents a joint architecture/circuit
optimization for FinFET-based SRAM. Last, a new circuit design technique,
asynchronous race, is introduced to greatly improve the power efficiency of
dynamic programming computation.
72
THURSDAY, JUNE 9
68
CHAIR:
CO-CHAIR:
Chia-Lin Yang - National Taiwan Univ., Taipei, Taiwan
Reconfigurable architectures are emerging to address the performance,
power and reliability concerns of modern systems. The first paper performs
experimental evaluation of the communication bandwidth and latency of
two CPU-FPGA platforms. The second paper presents a framework to
automatically generate RTL implementations of neural network accelerators.
The third paper presents Ta heterogeneous database accelerator MPSoC
that yields significant power efficiency improvements compared to highend CPU and GPU-based systems. The final paper improves the reliability
of FPGA-based reconfigurable architectures by performing kernel-specific
transient fault vulnerability reduction.
CHAIR:
CO-CHAIR:
73
THURSDAY, JUNE 9
70
CHAIR:
CO-CHAIR:
Dimin Niu - Samsung Semiconductor, Inc., Santa Clara, CA
Emerging non-volatile memory technologies enable new opportunities for
architecture designs and novel applications. The first paper introduces
a novel programmable logic-in-memory design (PLiM) using majorityinverter graphs with the ReRAM technology. The second paper describes
memory design with Ferroelectric FETs. The third paper proposes a new
register file design with STT-RAM for GPGPU, with techniques to reduce
write overheads for minimizing energy. The last paper addresses the read
reliability and write power concerns in STT-RAM with pseudo-differential
sensing schemes.
CHAIRS:
ORGANIZERS:
Ahmad-Reza Sadeghi - Technische Univ. Darmstadt, Germany
Yier Jin - Univ. of Central Florida, Orlando, FL
The Internet of Things (IoT) has become a popular concept in both industry
and academic settings, bringing along the vision of a bright future where
all unconnected things become connected. Whereas such a tightly
connected world brings about many benefits to our civilization, it comes
at the cost of privacy and security. The internet revolution has already
showed us once that leaving security as an afterthought has devastating
consequences. Repeating the same mistake with IoT would destroy the
utopic future we are aiming for.
In this special session IoT architects from academia and industry discuss
their views on how to properly secure IoT from the start, addressing
challenges of secure communication from the single IoT device, to groups of
devices, to the backbone network.
74
THURSDAY, JUNE 9
RESEARCH FUNDING LANDSCAPE FOR 2020 AND BEYOND
72
CHAIR:
ORGANIZER:
SPEAKER:
Kenneth Shepard - Columbia Univ., New York, NY
CHAIR:
Rangharajan Venkatesan - NVIDIA Corp, Santa Clara, CA
CO-CHAIR:
Jae-sun Seo - Arizona State Univ., Phoenix, AZ
Deep learning networks have recently emerged as one of the most promising
approaches to machine learning, and are advancing the field at a rapid pace.
How can these networks be implemented in hardware? The papers in the
session answer this question using novel approaches and emerging device
technologies.
73.1 C-Brain:A deep learning accelerator that tames the diversity of
CNNs through adaptive data-level parallelization (1:30)
Lili Song, Ying Wang, Yinhe Han, Xin Zhao, Bosheng Liu, Xiaowei Li
- Chinese Academy of Sciences & Institute of Computing Technology,
Beijing, China
THURSDAY, JUNE 9
74
CHAIR:
CO-CHAIR:
Sunil Khatri - Texas A&M Univ., College Station, TX
Approximate computing is an emerging design approach that exploits the
intrinsic error resilience of many applications to improve power efficiency.
This session has papers that address approximate computing at various
levels - the design of approximate adders, synthesis of approximate circuits,
and verification of approximate sequential circuits. The session concludes
with a paper that discusses improving timing error resilience at the circuit
level.
74.1 A Low-power Carry Cut-Back Approximate Adder with Fixedpoint Implementation and Floating-point Precision (1:30)
Vincent Camus, Jeremy Schlachter, Christian C. Enz - cole Polytechnique
Fdrale de Lausanne, Switzerland
74.2 An Efficient Method for Multi-level Approximate Logic
Synthesis under Error Rate Constraint (1:45)
Yi Wu, Weikang Qian - Shanghai Jiao Tong Univ., Shanghai, China
75
CHAIR:
CO-CHAIR:
Nan Guan - Hong Kong Polytechnic Univ., Hong Kong, Hong Kong
The recent introduction of multi-core and mixed-criticality systems has
resulted in the need for new scheduling algorithms capable of handling
these systems. The first paper generalizes harmonicity to real-time tasks
with deadlines shorter than periods, and applies it to workload partitioning
on multi-cores. The second paper proposes a probabilistic framework
for design and analysis of real-time mixed-criticality systems. The third
paper introduces a distributed scheduler for many-core systems based
on cooperative game theory to reduce inter-core processing overheads.
The last paper derives utilization bounds for partitioned rate-monotonic
multiprocessor scheduling of multi-mode real-time task systems.
76
THURSDAY, JUNE 9
76
CHAIR:
CO-CHAIR:
Takashi Sato - Kyoto Univ., Kyoto, Japan
This session features papers on enhancing HLS technology, beyond its
fundamentals. Papers describe techniques that help in selecting promising
micro-architecture directives to get the best circuit; building IP libraries for
data structures to enable broader deployment, and using HLS to improving
circuit reliability.
77
CHAIR:
CO-CHAIR:
Yongpan Liu - Tsinghua Univ., Beijing, China
The heterogeneous and distributed nature of IoT requires novel design
techniques. This session presents emerging approaches to reduce the
effort in designing distributed and dynamic sensing systems, ranging from
automatic learning and auto-generation to semantics-aware design and
statistical sampling.
77
THURSDAY, JUNE 9
78
CHAIRS:
Eric Keiter - Sandia National Laboratories, Albuquerque, NM
Peng Li - Texas A&M Univ., College Station, TX
ORGANIZER:
Ibrahim Elfadel - Masdar Institute of Science and Technology, Abu Dhabi,
United Arab Emirates
Near-field IoT solutions comprise devices and applications that leverage
high-frequency data sensing for near-field imaging, sensing, and
communication. They use the untapped and unregulated spectrum between
200GHz and 1000GHz the Terahertz range.
Such applications include medical, safety and security imaging; nondestructive testing; gas, explosive, and water detection; and food inspection.
In the pharmaceutical industry, target applications are lab-on-chip systems,
protection against medication tampering, and drug distinction.
79
CHAIR:
Michael Chen - Mentor Graphics Corp., Wilsonville, OR
ORGANIZER:
Valeria Bertacco - Univ. of Michigan, Ann Arbor, MI
More and more security attacks today are perpetrated by exploiting the
hardware: side-channel attacks leak secret keys to the outside world, weak
random number generators render cryptography ineffective, fault-based
attacks can compromise authentication, etc. Moreover, many of the tenets
of efficient design are in tension with guaranteeing security. For instance,
classic secure hardware does not allow to optimize common execution
patterns, share resources or provide deep introspection.
80
In this special session we will bring experts from academia and industry to
present the challenges that design engineers and CAD developers will be
facing to extend the reach of the Internet of Things to such near-range, highfrequency applications. The three presentations of this session will cover
many examples of near-field IoT applications, several design examples, and
discuss the landscape of CAD methodologies and tools in this emerging
research area.
CHAIR:
Robert Wille - Johannes Kepler Univ. of Linz, Austria
CO-CHAIR:
Shih-Hsu Huang - Chung Yuan Christian Univ., Taoyuan City, Taiwan
Increasing complexity of microfluidic and reversible circuits requires design
automation. This session addresses synthesis of micro-electrode-dot-array
digital microfluidic biochips, continuous-flow microfluidic biochips, boolean
satisfiability using quantum annealing and reversible circuits.
80.1 High-Level Synthesis for Micro-Electrode-Dot-Array Digital
Microfluidic Biochips (3:30)
Zipeng Li - Duke Univ., Durham, NC
Kelvin Yi-Tse Lai, Po-Hsien Yu - National Chiao Tung Univ., Hsinchu, Taiwan
Tsung-Yi Ho - National Tsing Hua Univ., Hsinchu, Taiwan
Krishnendu Chakrabarty - Duke Univ., Durham, NC
Chen-Yi Lee - National Chiao Tung Univ., Hsinchu, Taiwan
THURSDAY, JUNE 9
ITS ALL ABOUT MANAGEMENT! LOW POWER AT THE SYSTEM LEVEL
81
CHAIR:
CO-CHAIR:
Muhammad Shafique - Karlsruhe Institute of Technology, Karlsruhe,
Germany
82
CHAIR:
CO-CHAIR:
Dip Goswami - Technische Univ. Eindhoven, Netherlands Antilles
79
THURSDAY, JUNE 9
83
CHAIR:
Michail Maniatakos - New York Univ., Abu Dhabi, United Arab Emirates
CO-CHAIR:
Jeff Draper - Univ. of Southern California, Los Angeles, CA
Hardware security research has entered a new era where we are not just
protecting the hardware platform. The papers in this session awaken the
force inside the hardware to protect systems efficiently and effectively in
multiple ways.
84
CHAIR:
CO-CHAIR:
Yu Wang - Tsinghua Univ., Beijing, China
NVM technology provides promising solutions for memory and storage
bottlenecks in the big data era. However, it also brings grand challenges in
architecture, system and software. This session addresses several emerging
issues in NVM design from NVM control unit to NVM cache. The topics in
this session include bank-level parallelism, run-time monitoring for process
variation, cache management, and in-memory processing.
THURSDAY, JUNE 9
85
MODERATOR:
PANELISTS:
86
MODERATOR:
This panel aims at discussing the viability and the respective advantages of
both probabilistic and classical static timing analysis approaches and how
they fit the industrial needs and practices in terms of timing verification,
both from an application perspective as well as from an processor vendor
perspective.
PANELISTS:
Jaume Abella - Barcelona Supercomputing Center, Barcelona, Spain
Jan Reineke - Saarland Univ., Saarbruecken, Germany
Arne Hamann - Robert Bosch GmbH, Renningen, Germany
Glenn Farrall - Infineon Technologies AG, Bristol, United Kingdom
87
CHAIR:
ORGANIZER:
87.3 A Box of Dots: Using Scan-Based Path Delay Test for Timing
Verification (4:30)
Alfred Crouch - SiliconAid Solutions, Austin, TX
John Potter - ASSET InterTech, Inc., Austin, TX
Designers add margin to every aspect of their designs, often with good
reason. Timing margin in particular is critical to ensuring yield. But how much
margin is enough? This session looks at three important aspects of timing
signoff how can tool providers include flexibility for designers to make
informed decisions? What do chip makers need to do to ensure that they
include enough margin at sign off without leaving performance on the table?
Finally, how do margin and chip test interact, since final yield and quality
are determined by the ability to detect and remove marginal parts before
shipping them.
81
THURSDAY, JUNE 9
This session will teach the key SystemVerilog language skills needed
to understand and build class-based constrained random verification
environments, as used by UVM. The emphasis will be on learning to apply
the concepts of object-oriented programming to the creation of a reusable test bench infrastructure. Language features will be taught using
working code examples, which delegates can run immediately on the EDA
Playground website and will be available to use and share after the class.
This track is taught by Doulos CTO John Aynsley, winner of the Accellera
Systems Initiative 2012 Technical Excellence Award for his contribution to
the development of language standards
SPEAKER:
John Aynsley - Doulos, Ringwood, United Kingdom
This track is taught by Doug Perry, Doulos Senior Member Technical Staff.
SPEAKER:
Doug Perry - Doulos, San Jose, CA
This session will teach you how to use the SystemVerilog language for
hardware design by focusing on the parts of the SystemVerilog language
that are widely supported by commercial RTL synthesis tools. This session is
aimed at engineers who are currently using Verilog or VHDL for RTL design,
and who want to start taking advantage of the power of SystemVerilog to
better express their hardware design intent. Language features will be taught
using working code examples, which delegates can run immediately on the
EDA Playground website and will be available to use and share after the
class.
82
THURSDAY, JUNE 9
SPEAKER:
Carl Shaw - MathEmbedded Ltd., United Kingdom
SPEAKERS:
83
THURSDAY, JUNE 9
Elegant solutions may appear obvious in hindsight, but are difficult to identify
in the moment. During this interactive session well learn very practical
strategies for discovering creative solutions. Individual problem solving
methods and tactics will be explored, along with ways to overcome barriers
to innovative thinking. We then learn ways to approach interpersonal issues,
emphasizing techniques for promoting collaboration and overcoming the
emotional and psychological barriers of conflict. Finally, youll learn ways to
better manage and solve problems as a member of a team or group. Going
beyond brainstorming, well explore tactics to harness the creative energy of
the group while avoiding analysis paralysis and the dreaded groupthink.
TRACK 1, PART II: LEARN UVM USING THE EASIER UVM CODING GUIDELINES AND
CODE GENERATOR
Time: 2:15pm - 5:15pm | | Room: Ballroom E | | Event Type: Thursday is Training Day
Track: EDA | | Topic Area: Test & Verification
This track is taught by Doulos CTO John Aynsley, winner of the Accellera
Systems Initiative 2012 Technical Excellence Award for his contribution to
the development of language standards.
This session will teach the basics of UVM, the Universal Verification
Methodology for SystemVerilog, by taking advantage of Doulos Easier
UVM Coding Guidelines and Code Generator. All the main concepts of UVM
will be taught using working code examples. By running the Easier UVM
Code Generator on the EDA Playground website, delegates will be able to
run UVM examples immediately, experiment with what they have learned,
and share their examples with others after the class.
SPEAKER:
John Aynsley - Doulos, Ringwood, United Kingdom
The session is aimed at hands-on engineers who want to start writing UVM
code themselves and are looking for some specific advice on the best place
to start, the right UVM features and coding idiom to use, and the pitfalls to
avoid.
TRACK 2, PART II: THE DEFINITIVE GUIDE TO SYSTEMC TLM-2.0: LEARN THE
TECHNOLOGY STANDARD THAT UNDERPINS VIRTUAL PLATFORMS
Time: 2:15pm - 5:15pm | | Room: Ballroom F | | Event Type: Thursday is Training Day | | Track: EDA
Topic Area: System Architectures & SoC, Codesign & System Design
Following its launch back in 2008, the SystemC TLM-2.0 standard quickly
became the dominant standard for integrating transaction-level models in
the context of building virtual platforms for architectural exploration and
software development. TLM-2.0, which is now part of the IEEE 1666-2011
SystemC standard, standardizes a set of modeling mechanisms that allow
transaction level models from different sources to be interoperable and yet
to run at the fast execution speeds necessary to build a virtual platform for
software development.
SPEAKER:
David Black - Doulos, Austin, TX
This session will introduce the main concepts of both SystemC and TLM2.0, and will explain the tricks that allow TLM-2.0 to maintain speed and
interoperability in the context of virtual platform modeling. The features of
the standard will be demonstrated using working code examples, which
delegates can run immediately on the EDA Playground website and will be
available to use and share after the class.
84
THURSDAY, JUNE 9
SPEAKER:
Adrian Thomasset - Doulos, United Kingdom
Increasingly these devices are being connected to networks and this can
leave them vulnerable to remote attacks that can result in brand damage,
financial liabilities, product returns and even safety issues.
Hardening Linux systems to make them more resistant to attack is
possible and is something that should be performed for every connected
product. This introductory seminar introduces embedded systems
developers to the techniques of how to identify vulnerabilities and begins to
show ways in which the systems can be secured.
SPEAKERS:
Paul Fultz II - Advanced Micro Devices, Inc., Austin, TX
Zach Laine - NVIDIA Corp, Austin, TX
85
Visit DAC.com for more details and to download the FREE app!
Visit ChipEstimate.com
at DAC
Be the first to get the latest industry insights
from the worlds leading IP vendors and
foundries.
Discover IP Talks in the
ChipEstimate.com booth
#349 and enter to win a Nest
Learning Thermostat*!
*2 drawings per day
COLOCATED CONFERENCES
ACM/IEEE INTERNATIONAL WORKSHOP ON SYSTEM LEVEL INTERCONNECT
PREDICTION (SLIP) 2016
Date: Saturday, June 4 | | Time: 8:00am - 5:30pm | | Room: 12AB | | Event Type: Colocated Conference
Track: EDA, Design | | Topic Area: NoC & On-Chip Interconnects, Physical Design, System Architectures & SoC
ORGANIZERS:
SPEAKERS:
Kaushik Roy - Purdue Univ., West Lafayette, IN
Saverio Fazzari - Booz Allen Hamilton, Inc., Arlington, VA
Swarup Bhunia - Univ. of Florida, Gainesville, FL
Sanu Mathew - Intel Corp., Hillsboro, OR
EMBEDDED TECHCON
Date: Tuesday, June 7 - Wednesday, June 8 | | Time: 10:15am - 5:00pm | | Room: 13AB & 14
Event Type: Colocated Conference | | Track: Embedded Systems, IoT
Topic Area: Emerging Technologies, System Architectures & SoC, System Software
ORGANIZER:
The classes, which will be taught by leading industry experts, will cover
key embedded topics like IoT, automotive, and security, while drawing from
the industrys roots with topics like firmware development, debugging, and
open-source hardware and software.
88
www.acm.org/conf
For over 50 years, ACM has helped computing professionals to be their most creative, connect to peers
and see whats next, inspiring them to advance the profession and make a positive impact. We keep
inventing to push computing technology forward and to continue the legacy that unites us as like-minded
thinkers and makers. Join us on our mission to solve tomorrow.
The ACM Special Interest Group on Design Automation specializes in applications of computing to all phases
of the electrical and electronics design fields, including techniques, algorithms, and computer programs for
computer-aided design and testing systems, structure and software. www.acm.org/sigda
Membership Options
Professional
ACM Membership
q $99
SIGDA Membership
q $25
q $198
Student
$84*
q $19
q $15
$168*
q $42
*Special first year introductory rate (you must use this application form or call to receive this offer!)
Join ACM-W:
ACM-W supports, celebrates, and advocates internationally for the full engagement of women in all aspects
of the computing field. Available at no additional cost.
Payment Information
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ACM Member #
Mailing Address
Credit Card #
Exp. Date
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Fax: 212-944-1318
acmhelp@acm.org
acm.org/conf
PROMO CODE: CONF
COLOCATED CONFERENCES
CELUG/ESD ALLIANCE ENTERPRISE LICENSING CONFERENCE
Date: Tuesday, June 7 - Thursday, June 9 | | Time: 9:00am - 5:00pm | | Room: 9AB
Event Type: Colocated Conference | | Track: EDA | | Topic Area: General Interest
ORGANIZER:
Agenda:
11:30-11:55am: Registration
11:55am-12:00pm: Welcome and Introduction
12:00-12:30pm: IBM Platform Computing Strategy & Portfolio Overview
12:30-1:25pm: Introducing IBM Platform LSF 10.1
1:30-2:00pm: Client Case Study Presentation
2:00-2:30pm: Break
2:30-4:00pm: Deep Dive Sessions: Optimizing Software Licenses with RTM
& License Scheduler and Using LSFs Host Factory with OpenStack
4:00-4:30pm: Q&A and Closing Remarks
Topics of interest include (but are not limited to): synthesis and optimization;
power and timing analysis; testing, validation and verification; architectures
and compilation; and design experiences. Papers on the interaction of logic
synthesis with front-end or back-end design steps are welcome, specially
when considering the impact in the design flow. Submissions on modeling,
analysis and synthesis for emerging technologies are also encouraged
90
JOIN US!
The Electronic System Design Alliance provides a platform for
member companies to address technical, marketing, economic
and legislative issues affecting the entire industry. We also
provide networking events and targeted programs to assist
emerging companies in the design ecosystem.
ESD Alliance committees and working groups focus on critical
issues that affect the design ecosystem including -- Export
Regulations, License Management & Anti-Piracy, Market
Statistics Service, O/S Interoperability, Emerging Companies,
and Trade Shows.
NEW!
Advanced Packaging
Bringing together manufacturers and designers to enable the widespread use of
system scaling technologies such as 3D-IC and other multi-die approaches.
Embedded Software
Chip designers and embedded software designers working to develop best practices
and methodologies for implementing the hardware and software interface.
ADDITIONAL MEETINGS
A. RICHARD NEWTON YOUNG FELLOW PROGRAM WELCOME BREAKFAST
& ORIENTATION
Date: Sunday, June 5 | | Time: 7:30am - 9:00am | | Room: 18CD | | Event Type: Additional Meeting
Track: EDA | | Topic Area: General Interest
Welcome Breakfast and Orientation
Sunday, June 5
7:30 - 9:00am
Room: 18CD
design automation
92
Conferences
ASP-DAC, CANDE, DAC, DATE,
ESWEEK, ETS, FMCAD, ICCAD,
IOLTS, MEMOCODE, MPSoC,
NOCS, PATMOS, VLSI-SoC,
WF-IoT, and many other
technically sponsored events.
Publications
IEEE Transactions on
Computer-Aided Design (TCAD),
IEEE Design & Test (D&T),
IEEE Embedded Systems Letters,
and CEDA Currents.
Awards
CEDA honors innovative and
substantial technical contributions
to EDA, best published papers, or
contributions during the early
stages of ones research career.
IEEE CEDA
The only place for EDA and embedded
systems professionals, researchers,
and students to come together and
discover new technologies that are
advancing the state of the art!
CEDA is a nonprofit entity that provides
a platform for dissemination of ideas,
community feedback, and individual
recognition through its various awards,
publications, and conferences.
Visit us at http://ieee-ceda.org.
Join the CEDA mailing list for our
Ad-Free Quarterly Newsletter,
CEDA Currents, on major news
regarding the profession and CEDA.
To join, just send an (empty) email to
ceda-subscribe@listes.epfl.ch.
ADDITIONAL MEETINGS
DESIGN AUTOMATION SUMMER SCHOOL
Date: Sunday, June 5 | | Time: 9:00am - 6:00pm | | Room: 18CD | | Event Type: Additional Meeting
Track: IoT, Security | | Topic Area: Codesign & System Design, Cyber-Physical Systems, Emerging Technologies
he Design Automation Summer School (DASS) is a one-day intensive course
on research and development in design automation (DA). Each topic in this
course will be covered by a distinguished speaker who will define the topic,
describe recent accomplishments, and indicate remaining challenges. This
program is intended to introduce and outline emerging challenges, and to
foster creative thinking in the next generation of EDA engineers.
SPEAKER:
This years talk will focus on the challenges and opportunities facing EDA
vendors, including a view of the annual EDA forecast.
PANELISTS:
The panel discussion will focus on recent, highly effective ways to address
variation-aware design for Memory, Analog/RF and Standard Cell design.
The methodologies will include high-sigma Monte Carlo, PVT, statistical PVT,
and hierarchical Monte Carlo.
Opening by Amit Gupta (CEO, Solido) on custom IC design market data.
PANELISTS:
Azeez Bhavnagarwala - ARM, Inc., San Jose, CA
Glen Wiedemeier - IBM Corp., Austin, TX
Jeff Dyck - Solido Design Automation, Inc., Saskatoon, Canada
94
DESIGN, AUTOMATION
AND TEST IN EUROPE
The european event for
electronic system design & test
27 31 MARCH, 2017
Areas of Interest
Within the scope of the conference, the main areas of interest are: embedded systems, design methodologies, CAD languages,
algorithms and tools, testing of electronic circuits and systems, embedded software, applications design and industrial design
experiences. Topics of interest include, but are not restricted to:
System Specification and Modeling
System Design, Synthesis and
Optimization
Simulation and Validation
Design of Low Power Systems
Temperature-Aware Design
Power Estimation and Optimization
Temperature Modeling and
Management
Emerging Technologies, Systems and
Applications
Formal Methods and Verification
Network on Chip
Architectural and Microarchitectural
Design
Architectural and High-Level
Synthesis
Reconfigurable Computing
Logic and Technology Dependent
Synthesis for Deep-Submicron Circuits
Submission of Papers
Event Secretariat
Chairs
Phone:
Fax:
Email:
Papers can be submitted either for standard oral presentation or for interactive presentation. The Programme Committee also encourages proposals for Special Sessions,
Tutorials, Friday Workshops, University Booth, PhD Forum and Exhibition Theatre.
www.date-conference.com
ADDITIONAL MEETINGS
SYNOPSYS LUNCH: ROBUST AMS DESIGN VERIFICATION AT ADVANCED NODES
Date: Monday, June 6 | | Time: 11:30am - 1:30pm | | Room: Hilton Hotel, 6th floor, Austin Grand Ballroom G
Event Type: Additional Meeting | | Track: EDA | | Topic Area: Test & Verification
Industry leaders will discuss their design verification challenges that stem
from cutting-edge FinFET technologies and increasing design complexity
in memory, analog, and mixed-signal applications, and how they overcome
such challenges by using Synopsys AMS circuit simulation solutions to
ensure design robustness.
SPEAKER:
PANELISTS:
96
Visit www.ChipDesignMag.com
ADDITIONAL MEETINGS
SYNOPSYS PRIMETIME SIG DINNER: WORK SMARTER WITH ADVANCED SIGNOFF
TECHNOLOGY
Date: Monday, June 6 | | Time: 7:00pm - 9:00pm | | Room: Brazos Hall, 204 E 4th Street
Event Type: Additional Meeting | | Track: EDA | | Topic Area: General Interest
Synopsys hosts an annual event for the PrimeTime Special Interest Group
at DAC, providing an opportunity for users to stay connected with the latest
developments in timing analysis. We are pleased to host this PrimeTime SIG
event at DAC 2016.
Please join us and our panel of experts for breakfast as we discuss the
future of UVM and the challenges the industry is facing. We will also have
an update by Accellera Chair Shishpal Rawat and the presentation of the
Accellera Leadership Award. Event is free but registration at www.accellera.
org is required.
Join us to hear users discuss their experiences with FinFET custom design
challenges and how they have deployed Custom Compiler to improve their
custom design productivity for both FinFET and established nodes.
98
ADDITIONAL MEETINGS
IEEE CEDA LUNCHEON AND DISTINGUISHED LECTURE IN HONOR OF PROF.
EDWARD J. MCCLUSKEY
Date: Tuesday, June 7 | | Time: 12:00pm - 1:30pm | | Room: Ballroom D | | Event Type: Additional Meeting
Track: Design, EDA | | Topic Area: Test & Verification, Logic & High-Level Synthesis
DISTINGUISHED SPEAKER:
TRIBUTE SPEAKERS:
99
ADDITIONAL MEETINGS
ACM SIGDA PH.D. FORUM
Date: Tuesday, June 7 | | Time: 7:00pm - 9:00pm | | Room: Ballroom D | | Event Type: Additional Meeting
Track: EDA | | Topic Area: General Interest
ORGANIZERS:
For more information, please visit the ACM SIGDA Ph.D. Forum website.
Bronze Sponsor:
Silver Sponsors:
For further details and videos from previous years please visit the ACM
SIGDA University Booth site.
Booth Coordinators
Chair: Soonhoi Ha - Seoul National University, Korea
Vice Chair: Sudeep Pasricha - Colorado State Univ., Fort Collins, CO
Publicity Chair: Qi Zhu - Univ. of California, Riverside, CA
EDACAF
Visit EDACAF at DAC 2016 in booth #1226, and be entered to win a Kindle Fire!
#1 EDA NEWSLETTER
EDACafe.com is the #1 web portal for Electronic
Design Professionals. Visit our website today!
EDACAF
SPEAKER:
In longstanding Gary Smith EDA tradition, EDA chief analyst Laurie Balch
of Gary Smith EDA will share her views on the latest directions for the EDA
technology and business fronts. What new trends are facing the EDA,
semiconductor and design communities and how will they impact you?
What are the hot must see products at this years conference? How can
you prepare for the future of electronics design? Plus, get a rundown of the
annual Gary Smith EDA Sunday night kickoff talk.
ORGANIZER:
SPEAKER:
SPEAKER:
Rikky Muller - Univ. of California, Berkeley & Cortera Neurotechnologies,
Berkeley, CA
102
DAC PAVILION
LANZAS TECH VISION CHALLENGE: DARING TO MOVE TO OPEN SOURCE
Date: Monday, June 6 | | Time: 2:00pm - 2:45pm | | Room: DAC Pavilion - Booth 1839
Event Type: DAC Pavilion | | Track: EDA, IP | | Topic Area: General Interest
MODERATOR:
Lucio Lanza - Lanza TechVentures, Palo Alto, CA
Join Lucio Lanza for a fireside chat on the pros and cons of a move to an
open source EDA tools and IP design flow for the IoT SoC.
ORGANIZER:
PANELISTS:
In this talk, we explore the key SoC features, industry standards, and
software design patterns that enable the INTERNET of Things to reach its full
potential.
SPEAKER:
Bill Curtis - ARM Ltd., Austin, TX
SPEAKERS:
Andrew Goldberg - iFixIt, San Luis Obispo, CA
Sam Lionheart - iFixIt, San Luis Obispo, CA
103
DAC PAVILION
SOLVING THE DESIGN COST PUZZLE: HOW IP FITS
Date: Tuesday, June 7 | | Time: 10:30am - 11:00am | | Room: DAC Pavilion - Booth 1839
Event Type: DAC Pavilion | | Track: IP, EDA | | Topic Area: General Interest, Business
ORGANIZER:
Issues at the forefront of the design community include how die area
partitioning, the rise in IP block content per SoC and rising gate counts all
contribute to growing SIP market revenues. Other areas to explore include
emerging IP such as Programmable Fabric, Discretes (capacitors and
inductors), and the impact of rising design costs on design starts, units
and IP licensing revenues as well as the impact of new 10nm and below
processes that are already well under development.
SPEAKER:
Jim Feldhan - Semico Research Corp., Phoenix, AZ
SPEAKER:
ORGANIZER:
Laura Parker - Mentor Graphics Corp., Wilsonville, OR
Mentor Graphics Chairman and CEO talks with Semiconductor
Engineerings Ed Sperling in a live interview about consolidation, automotive
software, and what the semiconductor industry will look like in five years.
This talk will cover the technical features of the RISC-V ISA design ,
which has the goals of scaling from the tiniest implementations for IoT
up to the largest warehouse-scale computers, with support for extensive
customization. Well also describe three different industry-competitive opensource cores developed at UC Berkeley, all written in Chisel, a productive
new open-source hardware design language. Finally, well describe the
uptake of RISC-V and the development of the RISC-V ecosystem, including
the RISC-V Foundation.
SPEAKER:
Krste Asanovic - Univ. of California, Berkeley & SiFive, Inc., Berkeley, CA
The free and open RISC-V ISA began development at UC Berkeley in 2010,
with the frozen base user ISA standard released in May 2014, and has
since seen rapid uptake around the globe, including the first commercial
shipments.
ORGANIZER:
Michael Mac McNamara - Adapt-IP, Palo Alto, CA
PANELISTS:
104
DAC PAVILION
MORE IDEAS = MORE SOLUTIONS
Date: Tuesday, June 7 | | Time: 3:30pm - 4:00pm | | Room: DAC Pavilion - Booth 1839
Event Type: DAC Pavilion | | Track: Design, IoT | | Topic Area: Emerging Technologies, General Interest,
Physical Design
ORGANIZER:
SPEAKER:
SPEAKERS:
iFixit routinely tackles drones and will do so again this year at DAC. At
press time the model hadnt been determined but trust iFixit to choose well.
Drones may look like toys, though behind the colorful fascia lies some very
sophisticated electronicswhich make flying the things easier all the time.
You wouldnt guess that all the components iFixit will remove could lead to
that much fun for drone hobbyists (and that many headaches for potential
regulators).
SPEAKER:
Jan Vardaman, founder and president of Tech Search Inc. and a world
recognized authority on advanced packaging technology, will talk about the
state of packaging technology and 3D IC today. Jan will give insight into
the obstacles that we have to overcome, into applications and where the
industry needs to focus. The role of design will be highlighted throughout
the presentation. Join us for an insightful perspective from design into
manufacturing.
SPEAKER:
ORGANIZER:
Qi Wang - Cadence Design Systems, Inc., San Jose, CA
Cadences president and CEO talks with Semiconductor Engineerings Ed
Sperling about where the money is flowing, how its being spent or misspent, and how that will play out across the semiconductor industry.
105
DAC PAVILION
SKY TALK: SECURITY AT DIFFERENT LAYERS OF ABSTRACTIONS: APPLICATION,
OPERATING SYSTEMS, AND HARDWARE
Date: Wednesday, June 8 | | Time: 1:00pm - 1:30pm | | Room: DAC Pavilion - Booth 1839
Event Type: SKY Talk | | Track: Security, Embedded Systems | | Topic Area: Business
ORGANIZER:
SPEAKER:
Bryan Payne - Netflix, Los Gatos, CA
SPEAKER:
SPEAKER:
Scott Hanson - Ambiq Micro, Austin, TX
This is the company, after all, that developed the five-pointed Pentalobe
screw. Dont worry, iFixit made relatively short work of the Apple Watch last
year and is sure to do the same with the next device. Sorry, Sir Jony.
SPEAKERS:
Samantha Lionheart - iFixIt, San Luis Obispo, CA
Andrew Goldberg - iFixIt, San Luis Obispo, CA
106
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WEAR YOUR
I LOVE DAC
BUTTON
Thank You to Our Sponsors:
Booth 1648
Booth 519
Booth 1249
Visit DAC.com for more details and to download the FREE app!
50 points
Reception Sponsors
Amiq: Booth 1639
Fishtail: Booth 1812
Flexlogic: Booth 919
Mobiveil: Booth 1342
75 points
125 points
Gold Exhibitor
100 points
Mentor Graphics: Booth 949
Silver Exhibitor
Ansys: Booth 1449
75 points
* Check the Mobile App for the most up-to-date exhibitor list!
4. Find the missing treasure hidden around the show each day: 150 points
This gets you the most points! Each day of the exhibit (Monday, Tuesday and Wednesday) DAC will hide Elliott, the Engineering Superhero action figure. Elliott
will have a QR code on him, scan the code and earn the point. Please return Elliott to his hidden area for the next person to find.
PRIZES
DAC Attack ends at 4:00pm on June 8th. Rafe prizes and the grand prize winner will be announced on
Wednesday, June 8, 2016, at 5:00pm at the DAC Pavilion and by broadcast message within the App.
Registered attendees are eligible to win any of the prizes! There are two types of prizes: raffle prizes and the grand prize. Raffle winners will be selected from the top
50% of highest points scored. The Grand Prize will be randomly selected from the top 10% of the highest points scored.
Grand Prize:
Virtual Reality Headset
Raffle Prizes:
$150 Gift Card to the Apple Store
$150 Gift Card to Amazon
Beats Solo Headphones
Phantom Drone
EXHIBITING COMPANIES
Listing as of May 4, 2016
Orange Denotes First-time Exhibitor
COMPANY
BOOTH
COMPANY
BOOTH
ACM.......................................................................................................... 2430
Doulos......................................................................................................... 739
EDACafe.com............................................................................................ 1226
EMC........................................................................................................... 1239
EnSilica...................................................................................................... 1742
AMS............................................................................................................. 544
Evothings..................................................................................................... 939
ATopTech................................................................................................... 1648
IC Enable................................................................................................... 1541
ChipEstimate.com....................................................................................... 349
iFixit............................................................................................................. 939
CMP............................................................................................................ 343
Codasip..................................................................................................... 1113
Consensia.................................................................................................. 2219
IP Pavilion.................................................................................................. 1138
Laflin/Instigate............................................................................................. 331
Leti............................................................................................................. 1818
110
SoCScape................................................................................................. 2530
Menta.......................................................................................................... 640
Springer................................................................................................... Lobby
MOSIS......................................................................................................... 441
Nangate....................................................................................................... 442
TowerJazz.................................................................................................... 324
TRUECHIP................................................................................................. 1341
OpenText..................................................................................................... 638
TSMC.......................................................................................................... 848
UltraSoC.................................................................................................... 1138
PLDA........................................................................................................... 643
Verifyter..................................................................................................... 1820
Vtool............................................................................................................ 325
XYALIS....................................................................................................... 1918
IP PAVILION
Booth 1138
Aegis, LLC
Amphion Semiconductor Ltd
S3 Group................................................................................................... 2118
Seamless Devices
UltraSoc
EMBEDDED PAVILION
Booth 1138
Evothings
Hackster, Inc.
iFixit
SILVACO...................................................................................................... 649
krtkl inc.
Random Designs CA, Inc.
THANK
YOU
AISLE SIGNS
CONFERENCE BAG,
DAC T-SHIRT
IP TRACK
SUNDAY RECEPTION
NEWTON STUDENT
FELLOWSHIP
Investors in InnovationTM
WEDNESDAY RECEPTION
I LOVE DAC
REGISTRATION
THANK
YOU
EXHIBITING COMPANIES
ACM
Aegis, LLC
San Jose, CA
www.britesemi.com............................................................................ 1520
New York, NY
www.acm.org..................................................................................... 2430
Campbell, CA
www.adapt-ip.com............................................................................. 1138
San Jose, CA
www.cadence.com............................................................. 107, 507, 1138
Agnisys, Inc.
CAST, Inc.
Lowell, MA
www.agnisys.com................................................................................ 420
Woodcliff Lake, NJ
www.cast-inc.com................................................................................ 541
Aldec, Inc.
Chip Design
Henderson, NV
www.aldec.com.................................................................................... 619
San Francisco, CA
www.chipdesignmag.com.................................................................... 439
ALLEGRO DVT
ChipEstimate.com
San Jose, CA
www.chipestimate.com........................................................................ 349
AMIQ EDA
ChipStart LLC
Bucharest, Romania
www.amiq.com................................................................................... 1639
Palo Alto, CA
www.tekstart.com.............................................................................. 1338
ClioSoft, Inc.
Belfast, UK
www.amphionsemi.com..................................................................... 1138
Fremont, CA
www.cliosoft.com................................................................................. 519
AMS
CMP
Unterpremstaetten, Austria
www.ams.com...................................................................................... 544
Codasip
Sunnyvale, CA
www.analogbits.com............................................................................ 644
ANSYS, Inc.
Canonsburg, PA
www.ansys.com................................................................................. 1449
Freiburg, Germany
www.concept.de................................................................................ 1229
Santa Clara, CA
www.arcadiainnovation.com.............................................................. 1313
Dresden, Germany
www.coseda-tech.com...................................................................... 2119
Arduino LLC
Coventor, Inc.
Somerville, MA
www.arduino.cc.................................................................................... 939
Cary, NC
www.coventor.com............................................................................... 321
ARM, Inc.
San Jose, CA
www.arm.com............................................................................ 939, 1748
Framingham, MA
www.cst.com...................................................................................... 1719
DAC Pavilion
Santa Clara, CA
www.tukarla.com................................................................................ 2131
Louisville, CO
www.dac.com.................................................................................... 1839
ATopTech
Dassault Systemes
Santa Clara, CA
www.atoptech.com............................................................................ 1648
Waltham, MA
www.3ds.com....................................................................................... 548
Ausdia Inc.
Defacto Technologies
Sunnyvale, CA
www.ausdia.com................................................................................ 1119
Palo Alto, CA
www.defactotech.com....................................................................... 1129
Tewksbury, MA
www.avery-design.com........................................................................ 800
Grenoble, France
www.design-reuse.com........................................................................ 513
Digilent Inc
Vancover, Canada
www.blackcomb-da.com................................................................... 1919
Seattle, WA
www.digilentinc.com............................................................................ 939
DINI Group
Santa Clara, CA
www.bluepearlsoftware.com................................................................ 929
La Jolla, CA
www.dinigroup.com........................................................................... 2130
San Jose, CA
www.brekersystems.com................................................................... 1626
EXHIBITING COMPANIES
Doulos
IBM Corp.
EDACafe.com
IC Enable
EDXACT SA
IC Manage, Inc.
Embedded Pavilion
ICScape Inc.
EMC
EnSilica
Integrand Software
Entasys Inc.
Intel Corp.
ESD Alliance
Intento Design
EUROPRACTICE / IMEC
IP Pavilion
Evothings
Excellicon Inc.
Jama Software
Laguna Hills, CA
www.excellicon.com.......................................................................... 1213
Portland, OR
www.jamasoftware.com..................................................................... 1138
Jedat Inc.
Kapik Integration
Lake Oswego, OR
www.fishtail-da.com........................................................................... 1812
Toronto, Canada
www.kapik.com.................................................................................. 1541
Keysight Technologies
Mountain View, CA
............................................................................................................. 919
Santa Rosa, CA
www.keysight.com............................................................................... 727
Fractal Technologies
krtkl inc.
Los Gatos, CA
www.fract-tech.com........................................................................... 1718
San Francisco,
www.krtkl.com...................................................................................... 939
Fraunhofer IIS/EAS
Laflin/Instigate
Dresden, Germany
www.eas.iis.fraunhofer.de.................................................................. 1738
Portland, OR
www.laflinltd.com................................................................................. 331
Leti
Grenoble, France
www.cea.fr......................................................................................... 1818
Santa Clara, CA
www.graniteriverlabs.com.................................................................. 1541
Saratoga, CA
www.libtech.com.................................................................................. 743
Hackster, Inc.
Helic, Inc.
San Jose, CA
www.doulos.com.................................................................................. 739
Essex Junction, VT
www.ibm.com/technology................................................................... 719
Campbell, CA
www.edacafe.com.............................................................................. 1226
Dallas, TX
ic-enable.com/................................................................................... 1541
Voiron, France
www.edxact.com................................................................................ 1722
Campbell, CA
www.icmanage.com........................................................................... 1329
Louisville, CO
www.dac.com.................................................................................... 1138
Santa Clara, CA
www.icscape.com................................................................................ 738
Hopkinton, MA
www.emc.com.................................................................................... 1239
Berkeley Heights, NJ
www.integrandsoftware.com............................................................... 320
Santa Clara, CA
www.intel.com...................................................................................... 429
San Jose, CA
www.esd-alliance.org......................................................................... 1920
Paris, France
www.intento-design.com..................................................................... 329
Leuven, Belgium
www.imec.be........................................................................................ 440
Louisville, CO
www.dac.com.................................................................................... 1138
Stockholm, Sweden
www.evothings.com............................................................................. 939
Mountain View, CA
www.iroctech.com.............................................................................. 1638
Santa Clara, CA
www.lorentzsolution.com..................................................................... 327
San Francisco, CA
http://www.hackster.io......................................................................... 939
Paris, France
www.magillem.com............................................................................ 1413
San Jose, CA
www.helic.com..................................................................................... 819
115
EXHIBITING COMPANIES
Magwel NV
PLDA
Makers Market
ProDesign Electronics
Menta
Pulsic Inc.
Methodics, Inc.
Mixel, Inc.
Rocketick, Inc.
Mobile Semiconductor
Mobiveil Inc.
S2C Inc.
MOSIS
S3 Group
MunEDA GmbH
Nangate
Samsung Electronics
NEWRACOM Inc.
OneSpin Solutions
Seamless Devices
Open-Silicon Inc.
OpenText
Semifore, Inc.
Photeon Technologies
Si2
San Jose, CA
www.magwel.com.............................................................................. 1013
San Jose, CA
www.plda.com..................................................................................... 643
Louisville, CO
www.dac.com...................................................................................... 939
Mission Viejo, CA
www.profpga.com.............................................................................. 2218
San Jose, CA
www.proplussolution.com.................................................................. 1219
Wilsonville, OR
www.mentor.com................................................................................. 949
San Jose, CA
www.pulsic.com................................................................................. 1439
San Francisco, CA
www.methodics-da.com.................................................................... 1019
Sunnyvale, CA
www.randomdesignsca.com................................................................ 939
Sunnyvale, CA
www.micromagic.com.......................................................................... 231
Sunnyvale, CA
www.realintent.com.............................................................................. 527
San Jose, CA
www.mixel.com.................................................................................. 1233
San Jose, CA
www.rocketick.com...................................................................... 227, 328
Seattle, WA
www.mobile-semi.com....................................................................... 1722
Santa Clara, CA
www.rtda.com.................................................................................... 1728
Milpitas, CA
www.mobiveil.com............................................................................. 1342
San Jose, CA
www.s2cinc.com................................................................................ 1928
Dublin, Ireland
www.s3group.com/silicon.................................................................. 2118
Munich, Germany
www.muneda.com................................................................... 1328, 1438
Santa Clara, CA
www.sage-da.com............................................................................... 421
Santa Clara, CA
www.nangate.com............................................................................... 442
San Jose, CA
www.samsung.com...................................................................... 607, 706
Irvine, CA
www.newracom.com.......................................................................... 2230
Sunnyvale, CA
www.sankalpsemi.com...................................................................... 1541
San Jose, CA
www.omnidesigntech.com................................................................. 2018
Palo Alto, CA
www.scianalog.com........................................................................... 1339
Munich, Germany
www.onespin-solutions.com.............................................................. 1249
Belmont, MA
www.seamlessdevices.com............................................................... 1138
Milpitas, CA
www.open-silicon.com/...................................................................... 2431
Shanghai, China
www.smics.com................................................................................. 1520
Durham, NC
www.src.org....................................................................................... 2217
Mountain View, CA
www.oskitechnology.com.................................................................... 339
Palo Alto, CA
www.semifore.com................................................................... 1529, 1630
Culver City, CA
www.pacificmicrochip.com................................................................ 2231
Shanghai, China
www.hlmc.cn...................................................................................... 1723
Austria, Europe
www.photeon.com............................................................................. 1541
Austin, TX
www.si2.org.......................................................................................... 239
116
WORLD OF IoT
BE SURE TO VISIT ALL OF THE PARTICIPATING COMPANIES!
EMBEDDED
pavilion
EMBEDDED PAVILION
makers
market
MAKERS MARKET
IP pavilion
IP PAVILION
EXHIBITING COMPANIES
Siemens PLM Software
Sigasi
TowerJazz
TRUECHIP
TSMC
SILVACO
UltraSoC
SKILLCAD Inc.
SmartDV Technologies
Verification Academy
SoCScape
Verifyter
Veritools, Inc.
Springer
Vtool
StarNet Communications
XYALIS
SureCore Ltd.
Synopsys, Inc.
Zipalog Inc.
Plano, TX
www.siemens.com............................................................................. 2028
Kawasaki-shi, Kana
www.tjsys.co.jp/english/index.htm..................................................... 1138
Gentbrugge, Belgium
www.sigasi.com................................................................................. 2019
Newport Beach, CA
www.towerjazz.com............................................................................. 324
Bangalore, India
www.silabtech.com............................................................................ 1442
Los Altos, CA
www.truecircuits.com........................................................................... 827
Suwanee, GA
www.siliconcr.com............................................................................. 1539
New York, NY
www.truechip.net/.............................................................................. 1341
Campbell, CA
www.siliconfrontline.com................................................................... 1712
San Jose, CA
www.tsmc.com..................................................................................... 848
Santa Clara, CA
www.silvaco.com................................................................................. 649
Cambridge, UK
www.ultrasoc.com.............................................................................. 1138
San Jose, CA
www.skillcad.com.............................................................................. 1642
Alameda, CA
www.verific.com................................................................................... 538
San Diego, CA
www.smart-dv.com............................................................................ 1641
Wilsonville, OR
www.verificationacademy.com............................................................. 627
Mission Aiejo, CA
www.socspace.com........................................................................... 2530
Saskatoon, Canada
www.solidodesign.com........................................................................ 611
Lund, Sweden
www.verifyter.com.............................................................................. 1820
North Syracuse, NY
www.sonnetsoftware.com.................................................................. 1543
Los Altos, CA
www.veritools.com............................................................................... 221
New York, NY
www.springer.com............................................................................ Lobby
Sunnyvale, CA
www.starnet.com................................................................................. 543
Grenoble, France
www.xyalis.com................................................................................. 1918
San Jose, CA
www.zentera.net................................................................................... 812
Mountain View, CA
www.synopsys.com..................................................................... 149, 361
Plano, TX
www.zipalog.com............................................................................... 1819
Tanner EDA
SUPPLEMENTAL LISTING
Monrovia, CA
www.tannereda.com.......................................................................... 1828
Consensia Inc
Dunlin, CA
www.consensiainc.com..................................................................... 2219
Cedar Park, TX
www.bayermarketingservices.com.................................................... 1721
Beijing, China
www.wmpyrean.com.cn....................................................................... 738
Teklatech A/S
DK Frederiksberg C, Denmark
www.teklatech.com.............................................................................. 223
iFixit
Teraproc Inc.
Markham, Canada
www.teraproc.com............................................................................. 1925
Somerville, CA
www.spetral-dt.com........................................................................... 1922
TOOL Corp.
San Jose, CA
www.tool-corp.com............................................................................ 1531
Real Silicon
Cupertino, CA
www. realsilicon.com......................................................................... 2220
118
Redesigned and
Reimaginged
Real-Time Systems
HPEC
Industrial Computing
www.rtcgroup.com/rtc-digital
www.rtcgroup.com
COMMITTEES
EXECUTIVE COMMITTEE
General Chair
Charles Alpert
Cadence Design
Systems, Inc.
alpert@cadence.com
Vice Chair
Past Chair
Program Chair
Adapt IP
mac@adapt-ip.com
Anne Cirkel
X. Sharon Hu
Mentor Graphics
Corp.
anne_cirkel@
mentor.com
Panel Chair
Tutorial Chair
Valeria Bertacco
ARM, Inc.
rob.aitken@arm.com
Intel Corp.
ramond.rodriguez@
intel.com
Design/IP Track
Co-Chair
Design/IP Track
Co-Chair
Michael Mac
McNamara
Technical
Program
Co-Chair
Technical
Program
Co-Chair
Korea Advanced
Institute of Science and
Technology
Univ. of Michigan
valeria@umich.edu
Naehyuck Chang
Robert Aitken
Ramond Rodriguez
naehyuck@cad4x.
kaist.ac.kr
Automotive
Track Chair
Dirk Ziegenbein
Zhuo Li
Debashis
Bhattacharya
Cadence Design
Systems, Inc.
zhuoli@cadence.com
Huawei Technologies
Co., Ltd
d.bhattacharya@
huawei.com
Security Chair
ESS Chair
Finance Chair
NXP Semiconductors
Robert.oshana@
nxp.com
Synopsys, Inc.
Patrick.R.Groeneveld
@synopsys.com
Ramesh Karri
Publicity Chair
Michelle Clancy
Cayenne
Communication
michelle.clancy@
cayennecom.com
Conference
Manager
Kevin Lepine
MP Associates, Inc.
kevin@
mpassociates.com
Robert Oshana
Patrick Groeneveld
ACM
Representative
ESD Alliance
Representative
Vijaykrishnan
Narayanan
Graham Bell
Real Intent
graham@
realintent.com
Pennsylvania State
Univ.
vxn9@cse.psu.edu
Exhibit Manager
Lee Wood
MP Associates, Inc.
lee@mpassociates.com
120
IP Track Chair
Claude Moughanni
Lattice Semiconductor
Claude.Moughanni@
latticesemi.com
Industry Advisory
Chair
Rob van
Blommestein
S2C Inc.
robvb@s2cinc.com
IEEE/CEDA
Representative
Shishpal Rawat
Intel Corp
shishpal.s.rawat@
intel.com
Univ. of Michigan
Ann Arbor, MI
Naehyuck Chang
Valeria Bertacco
Pai Chou
Franco Fummi
Ramkumar Jayaseelan
Zaid Al-Ars
Chris Chu
Pierre-Emmanuel Gaillardon
Yier Jin
Todd Austin
Siddharth Garg
Eric Keiter
Danny Bathen
Florentin Dartu
Swaroop Ghosh
Sunil Khatri
Dip Goswami
Jaeha Kim
Paul Gratz
Jae-Joon Kim
Lars Bauer
Laleh Behjat
Univ. of Calgary
Calgary, AB, Canada
Sanjukta Bhanja
Swarup Bhunia
Univ. of Florida
Gainesville, FL
Paul Bogdan
Eli Bozorgzadeh
Oliver Bringmann
Univ. Tbingen
Tbingen, Germany
Philip Brisk
Ismail Bustany
Yu Cao
Luca Carloni
Columbia Univ.
New York, NY
Mario Casu
Politecnico di Torino
Torino, Italy
Deming Chen
Jian-Jia Chen
Charles Chiang
Synopsys, Inc.
Mountain View, CA
Bruce Childers
Univ. of Pittsburgh
Pittsburgh, PA
Kiyoung Choi
Univ. of Verona
Verona, Italy
Univ. of Utah
Salt Lake City, UT
Korea Univ.
Seoul, Republic of Korea
Suman Datta
Abhijit Davare
Intel Corp.
Hillsboro, OR
Rhett Davis
Dionisio de Niz
Alper Demir
Koc Univ.
Istanbul, Turkey
Dengqx Deng
Marco Di Natale
Gero Dittmann
Rainer Doemer
Frederic Doucet
Qualcomm, Inc.
San Jose, CA
Wolfgang Ecker
Infineon Technologies AG
Neubiberg, Germany
Saverio Fazzari
Peter Feldmann
D. E. Shaw Research
New York, NY
Zhuo Feng
Domenic Forte
Univ. of Florida
Gainesville, FL
Harry Foster
Jie Gu
Northwestern Univ.
Evanston, IL
Nan Guan
Sandeep Gupta
Arne Hamann
Andreas Hansson
ARM Ltd.
Cambridge, United Kingdom
Masanori Hashimoto
Osaka Univ.
Suita, Japan
Tsung-Yi Ho
Daniel Holcomb
Houman Homayoun
George Mason Univ.
Fairfax, VA
Jiang Hu
H. Howie Huang
Yu Huang
William Hung
Synopsys, Inc.
Mountain View, CA
Engin Ipek
Univ. of Rochester
Rochester, NY
Roozbeh Jafari
121
KNUPATH
Austin, TX
Jihong Kim
John Kim
KAIST
Daejeon, Republic of Korea
Taemin Kim
Intel Corp.
Hillsboro, OR
Cheng-Kok Koh
Purdue Univ.
West Lafayette, IN
Farinaz Koushanfar
Xenofon Koutsoukos
Vanderbilt Univ.
Nashville, TN
Tushar Krishna
Akash Kumar
Hai Li
Univ. of Pittsburgh
Pittsburgh, PA
Sheng Li
Intel Corp.
Santa Clara, CA
Xin Li
Yih-Lang Li
Yongpan Liu
Tsinghua Univ.
Beijing, China
Martin Lukasiewycz
Robert Bosch GmbH
Renningen, Germany
Saurabh Sinha
Steven Wilton
Enrico Macii
Massimo Poncino
Frank Slomka
Fei Xie
Ken Mai
Miodrag Potkonjak
Mircea Stan
Yuan Xie
Michail Maniatakos
Qinru Qiu
Walter Stechele
Jiang Xu
Peter Marwedel
Gang Qu
Daryl Stewart
Rami Melhem
Anand Raghunathan
Greg Stitt
Politecnico di Torino
Torino, Italy
Politecnico di Torino
Torino, Italy
Carnegie Mellon Univ.
Pittsburgh, PA
New York Univ. Abu Dhabi
Abu Dhabi, United Arab Emirates
Technische Univ. Dortmund
Dortmund, Germany
Univ. of Pittsburgh
Pittsburgh, PA
Brett Meyer
McGill Univ.
Montreal, QC, Canada
Univ. of Pennsylvania
Philadelphia, PA
Politecnico di Torino
Torino, Italy
Univ. of California, Los Angeles
Los Angeles, CA
Syracuse Univ.
Syracuse, NY
Univ. of Maryland
College Park, MD
Purdue Univ.
West Lafayette, IN
Sandip Ray
Intel Corp.
Hillsboro, OR
ARM, Inc.
Austin, TX
Univ. of Ulm
Ulm, Germany
Univ. of Virginia
Charlottesville, VA
Technische Univ. Mnchen
Munich, Germany
ARM Ltd.
Cambridge, United Kingdom
Univ. of Florida
Gainesville, FL
Cliff Sze
IBM Corp.
Austin, TX
Prabhat Mishra
Garrett Rose
Mehdi B. Tahoori
Jos Monteiro
Sanghamitra Roy
Vivek Tiwari
Univ. of Florida
Gainesville, FL
Univ. of Tennessee
Knoxville, TN
Utah State Univ.
Logan, UT
Onur Mutlu
Ahmad-Reza Sadeghi
Andres Torres
Seetharam Narasimhan
Soheil Samii
Antonino Tumeo
Vijaykrishnan Narayanan
Jack Sampson
Gabriela Nicolescu
Patrick Schaumont
Nicola Nicolici
McMaster Univ.
Hamilton, ON, Canada
Sam H. Noh
UNIST
Ulsan, Republic of Korea
David Z. Pan
Partha Pande
Michael Papamichael
Microsoft Research
Redmond, WA
Michele Petracca
Univ. of Connecticut
Storrs, CT
Miroslav Velev
Gunar Schirner
Natarajan Viswanathan
Northeastern Univ.
Boston, MA
Leo Selavo
Li-C Wang
Zili Shao
Yu Wang
Univ. of Latvia
Riga, Latvia
Hong Kong Polytechnic Univ.
Hong Kong, Hong Kong
Yiyu Shi
Zhao Wang
Thomas Wenisch
Ozgur Sinanoglu
Robert Wille
Apple, Inc.
Cupertino, CA
Univ. of Michigan
Ann Arbor, MI
122
Zuochang Ye
Tsinghua Univ.
Beijing, China
Bei Yu
Hao Yu
Huafeng Yu
Haibo Zeng
Xuan Zeng
Fudan Univ.
Shanghai, China
Wei Zhang
Zhiru Zhang
Cornell Univ.
Ithaca, NY
Jishen Zhao
Hai Zhou
Northwestern Univ.
Evanston, IL
Dakai Zhu
Cheng Zhuo
Intel Corp.
Hillsboro, OR
Graham Bell
Susie Horn
Michael Munsey
Herta Schreiner
Michelle Clancy
Dagmar Lambrecht
Yukari Ohno
Philippa Slayton
Diana Dearin
Sandra Larrabee
Tom Quan
Bob Smith
MP Associates, Inc.
Louisville, CO
Cadence Design Systems Inc.
San Jose, CA
ARM
San Jose, CA
Methodics, Inc.
Boston, MA
Consultant
San Jose, CA
TSMC
San Jose, CA
Synopsys, Inc.
Mountain View, CA
Mike Gianfanga
eSilicon Corp.
San Jose, CA
STRATEGY COMMITTEE
Vice Chair
Chuck Alpert
Michelle Clancy
Alex Kondratyev
Warren Savage
Tom Anderson
Craig Cochran
Larry Lapides
Craig Shirley
William D. Billowitch
Susie Horn
Steve Padnos
Anne Cirkel
Cayenne Communcation
Sunnyvale, CA
Cadence Design Systems, Inc.
San Jose, CA
MP Associates, Inc.
Louisville, CO
Xilinx Inc.
San Jose, CA
IPextreme
Campbell, CA
IC Manage, Inc.
Campbell, CA
S2C, Inc.
San Jose, CA
Cayenne Communication
Sunnyvale, CA
Danielle Arnold
Paul Cohen
Brian Fuller
Anne Cirkel
John Day
Joslyn Mclaughlin
Synopsys, Inc
San Jose, CA
ESD Alliance
San Jose, CA
ARM, Inc.
San Jose, CA
Automotive Electronics
Kalamazoo, MI
AUTOMOTIVE COMMITTEE
Automotive Track Chair
Dirk Ziegenbein
Robert-Bosch GmbH
Renningen, Germany
Marco Di Natale
Dip Goswami
Soheil Samii
Huafeng Yu
Wolfgang Ecker
Arne Hamann
Walter Stechele
Haibo Zeng
123
Zhuo Li
Debashis Bhattacharya
Back-End Committee
Binu Abraham
Jianwen Jin
Kevin Nesmith
Venugopal Thammana
Bertram Bradley
Michael Kazda
David Newmark
Badhri Uppiliappan
Jarrod Brooks
Masanori Kurimoto
Oscar Ou
Lata Valluri
Eli Chiprout
Koen Lampaert
Satish Raj
Natarajan Viswanathan
Hao Lee
Vivek Rajan
Tim Whitfield
Brian Cline
Robert Lipsey
Roman Schwarz
Seth Wilk
Sabya Das
Phil Matthews
Kuldeep Singh
Sunghee Yun
Homayoon Akhiani
Ashish Darbari
Robert Kaye
Wolfgang Roesner
Srinath Atluri
Alastair Donaldson
Dave Kelf
Erik Seligman
Karthik Baddam
Theo Drane
Carey Kloss
Rob Shearer
Aviv Barkai
David Goldberg
Jeremy Levitt
Danil Sokolov
Mike Bartley
Stefan Hoereth
Nitin Mhaske
Shang-Wei Tu
Tim Blackmore
Bhavin Patel
Miroslav Velev
Robert Carden IV
Alan Hunter
Harsh Patel
William Wallace
John Colley
Jennifer Hwang
John Redmond
Shan Yan
George Constantinides
Kyungsu Kang
Vincent Reynolds
Jason Andrews
Pat Brouillette
Benjamin Cab
Susmit Jha
Michael Brogioli
Mark Brown
Alex Chandra
Hyungwoo Lee
ANSYS, Inc.
San Jose, CA
GLOBALFOUNDRIES
Austin, TX
Cypress Semiconductor Corp.
Lexington, KY
Intel Corp.
Hillsboro, OR
Synopsys, Inc.
Mountain View, CA
ARM Ltd.
Austin, TX
Xilinx Inc.
San Jose, CA
EDDR Software
Austin, TX
Qualcomm, Inc.
Cary, NC
Oracle Corp.
Santa Clara, CA
Intel Corp.
Portland, OR
Jia-Wei Fang
MediaTek, Inc.
Hsinchu, Taiwan
Front-End Committee
Nvidia Corp.
Santa Clara, CA
Cavium, Inc.
San Jose, CA
Quick Logic
Sunnyvale, CA
ARM Ltd.
Cambridge, Great Britain
OneSpin Solutions GmbH
Stoneham, MA
Nervana Systems
Palo Alto, CA
Mentor Graphics Corp.
Fremont, CA
Synopsys, Inc.
Austin, TX
Intel Corp.
Chandler, AZ
Microsoft Corp.
Redmond, WA
Newcastle Univ.
Newcastle upon Tyne, Great Britain
MediaTek, Inc.
Hsinchu, TW
ESS Committee
ARM, Inc.
Ham Lake, MN
Polymathic Consulting
Austin, TX
Roku, Inc.
Tempe, AZ
Andrew Putnam
Michael Solka
Colin Walls
Amitabh Menon
Jan Rellermeyer
Alicia Strang
ChengYeh Wang
Robert Oshana
Adolph Seema
Xin-Xin Yang
Rei-Fu Huang
Claude Moughanni
Lionel Riviere
Priyank Shukla
Andrea Kroll
Steve Padnos
McKenzie Ross
Henning Spruth
Peng Liu
Farhan Rahman
Warren Savage
Farzad Zarrinfar
STMicroelectronics
Grenoble Cedex, FR
Qualcomm, Inc.
San Jose, CA
NXP Semiconductors
Austin, TX
Microsoft Research
Seattle, WA
Coherent Logix
Austin, TX
NXP Semiconductors
Chandler, AZ
ARM
Austin, TX
NXP Semiconductors
Beijing, CN
IP Committee
MediaTek Inc.
Hsinchu, TW
Heather Monigan
Intel Corp.
Chandler, AZ
Lattice Semiconductor
San Jose, CA
GLOBALFOUNDRIES
Austin, TX
Consultant
San Jose, CA
IPextreme
Campbell, CA
AMD
Austin, TX
IPextreme
Campbell, CA
Simon Rance
ARM Ltd.
Plano, TX
IP TRACK COMMITTEE
IP Track Chair
IP Track Vice-Chair
Lattice Semiconductor
San Jose, CA
Intel Corp.
Chandler, AZ
Claude Moughanni
Heather Monigan
Andrea Kroll
Simon Rance
Warren Savage
Peng Liu
McKenzie Ross
Priyank Shukla
ARM Ltd.
Plano, TX
IPextreme
Campbell, CA
IPextreme
Campbell, CA
Farzad Zarrinfar
SPONSORS COMMITTEE
General Chair
Charles Alpert
ACM/SIGDA Representative
Vijay Narayanan
Past Chair
Anne Cirkel
ACM/SIGDA Representative
Farrah Khan
ESD Alliance
San Jose, CA
SECURITY COMMITTEE
Security Chair
Security Vice-Chair
Ramesh Karri
Bill Eklow
Serge Leef
Peilin Song
125
SRC
Research Triangle Park, NC
Intel Corp.
Folsom, CA
INDEX
Additional Meetings92
Colocated Conferences88
Conference Sponsors5
SKY Talks10
Supplemental Listing118
Exclusive Sponsorships112
Exhibiting Companies114
Thursday Keynote71
Exhibitor List110
Thursday Sessions72
Important Information6
Tuesday Sessions37
In Memory12
Keynotes8
Wednesday Keynote53
Monday Keynote22
Wednesday Sessions54
Monday Sessions23
Monday Tutorials29
Networking Receptions7
Workshops18
126
NOTES
NOTES
NOTES
NOTES