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MKL25ZxxVFM4
MKL25ZxxVFT4
MKL25ZxxVLH4
MKL25ZxxVLK4
Performance
48 MHz ARM Cortex-M0+ core
Memories and memory interfaces
Up to 128 KB program flash memory
Up to 16 KB SRAM
Human-machine interface
Low-power hardware touch sensor interface (TSI)
Up to 66 general-purpose input/output (GPIO)
Communication interfaces
USB full-/low-speed On-the-Go controller with onchip transceiver and 5 V to 3.3 V regulator
Two 8-bit SPI modules
One low power UART module
Two UART modules
Two I2C module
System peripherals
Nine low-power modes to provide power optimization
based on application requirements
COP Software watchdog
4-channel DMA controller, supporting up to 63 request
Analog Modules
sources
Low-leakage wakeup unit
16-bit SAR ADC
SWD debug interface and Micro Trace Buffer
12-bit DAC
Bit Manipulation Engine
Analog comparator (CMP) containing a 6-bit DAC
and programmable reference input
Clocks
32 kHz to 40 kHz or 3 MHz to 32 MHz crystal oscillator
Timers
Multi-purpose clock source
Six channel Timer/PWM (TPM)
1 kHz LPO clock
Two 2-channel Timer/PWM modules
Periodic interrupt timers
Operating Characteristics
16-bit low-power timer (LPTMR)
Voltage range: 1.71 to 3.6 V
Real time clock
Freescale reserves the right to change the detail specifications as may be required to
permit improvements in the design of its products. 20122014 Freescale
Semiconductor, Inc. All rights reserved.
Ordering Information 1
Part Number
Memory
Flash (KB)
SRAM (KB)
MKL25Z32VFM4
32
23
MKL25Z64VFM4
64
23
MKL25Z128VFM4
128
16
23
MKL25Z32VFT4
32
36
MKL25Z64VFT4
64
36
MKL25Z128VFT4
128
16
36
MKL25Z32VLH4
32
50
MKL25Z64VLH4
64
50
MKL25Z128VLH4
128
16
50
MKL25Z32VLK4
32
66
MKL25Z64VLK4
64
66
MKL25Z128VLK4
128
16
66
1. To confirm current availability of ordererable part numbers, go to http://www.freescale.com and perform a part number
search.
Related Resources
Type
Description
Resource
Selector Guide
Solution Advisor
Product Brief
The Product Brief contains concise overview/summary information to KL2 Family Product Brief1
enable quick evaluation of a device for design suitability.
Reference
Manual
KL25P80M48SF0RM1
Data Sheet
KL25P80M48SF01
Chip Errata
KINETIS_L_xN97F2
Package
drawing
1. To find the associated resource, go to http://www.freescale.com and perform a search using this term.
2. To find the associated resource, go to http://www.freescale.com and perform a search using this term with the x
replaced by the revision of the device you are using.
System
Internal
watchdog
Debug
interfaces
Memories and
Memory Interfaces
Program
flash
Phaselocked loop
Frequencylocked loop
DMA
Interrupt
controller
Clocks
RAM
Low/high
frequency
oscillator
BME
MTB
Internal
reference
clocks
Security
Analog
Timers
Internal
watchdog
16-bit ADC
x1
Timers
1x6ch+2x2ch
Analog
comparator
x1
Low
power timer
x1
and Integrity
6-bit DAC
12-bit DAC
Periodic
interrupt
timers
Communication
Interfaces
Human-Machine
Interface (HMI)
GPIOs
with
interrupt
I C
x2
Low power
UART
x1
TSI
SPI
x2
RTC
UART
x2
USB LS/FS
x1
LEGEND
3
Freescale Semiconductor, Inc.
Table of Contents
1 Ratings.................................................................................... 5
1.1 Thermal handling ratings................................................. 5
1.2 Moisture handling ratings................................................ 5
1.3 ESD handling ratings....................................................... 5
1.4 Voltage and current operating ratings............................. 5
2 General................................................................................... 6
2.1 AC electrical characteristics.............................................6
2.2 Nonswitching electrical specifications..............................7
2.2.1 Voltage and current operating requirements....... 7
2.2.2 LVD and POR operating requirements................7
2.2.3 Voltage and current operating behaviors.............8
2.2.4 Power mode transition operating behaviors........ 9
2.2.5 Power consumption operating behaviors............ 10
2.2.6 EMC radiated emissions operating behaviors..... 16
2.2.7 Designing with radiated emissions in mind..........17
2.2.8 Capacitance attributes.........................................17
2.3 Switching specifications...................................................17
2.3.1 Device clock specifications..................................17
2.3.2 General switching specifications......................... 18
2.4 Thermal specifications..................................................... 18
2.4.1 Thermal operating requirements......................... 18
2.4.2 Thermal attributes................................................19
3 Peripheral operating requirements and behaviors.................. 19
3.1 Core modules.................................................................. 19
3.1.1 SWD electricals .................................................. 19
3.2 System modules.............................................................. 21
3.3 Clock modules................................................................. 21
3.3.1 MCG specifications..............................................21
3.3.2 Oscillator electrical specifications........................23
3.4 Memories and memory interfaces................................... 25
3.4.1 Flash electrical specifications.............................. 25
3.5 Security and integrity modules........................................ 27
3.6 Analog............................................................................. 27
3.6.1
3.6.2
4
Freescale Semiconductor, Inc.
4
5
6
7
9 Revision history.......................................................................57
Ratings
1 Ratings
1.1 Thermal handling ratings
Table 1. Thermal handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
TSTG
Storage temperature
55
150
TSDR
260
Description
Moisture sensitivity level
Min.
Max.
Unit
Notes
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
Description
Min.
Max.
Unit
Notes
VHBM
2000
+2000
VCDM
500
+500
100
+100
mA
ILAT
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human
Body Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.
5
Freescale Semiconductor, Inc.
General
Description
Min.
Max.
Unit
VDD
0.3
3.8
IDD
120
mA
VIO
0.3
VDD + 0.3
25
25
mA
ID
VDDA
VDD 0.3
VDD + 0.3
VUSB_DP
0.3
3.63
VUSB_DM
0.3
3.63
0.3
6.0
VREGIN
2 General
2.1 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
VIH
Input Signal
Low
High
80%
50%
20%
Midpoint1
Fall Time
VIL
Rise Time
All digital I/O switching characteristics, unless otherwise specified, assume the output
pins have the following characteristics.
CL=30 pF loads
Slew rate disabled
Normal drive strength
6
Freescale Semiconductor, Inc.
General
Description
Min.
Max.
Unit
VDD
Supply voltage
1.71
3.6
VDDA
1.71
3.6
0.1
0.1
0.1
0.1
VIH
VIL
0.7 VDD
0.75 VDD
0.35 VDD
0.3 VDD
0.06 VDD
mA
VHYS
Input hysteresis
IICIO
Notes
25
mA
VODPU
VDD
VDD
VRAM
1.2
1. All I/O pins are internally clamped to VSS through a ESD protection diode. There is no diode connection to VDD. If VIN
greater than VIO_MIN (= VSS-0.3 V) is observed, then there is no need to provide current limiting resistors at the pads. If
this limit cannot be observed then a current limiting resistor is required. The negative DC injection current limiting
resistor is calculated as R = (VIO_MIN - VIN)/|IICIO|.
2. Open drain outputs must be pulled to VDD.
Description
Min.
Typ.
Max.
Unit
Notes
0.8
1.1
1.5
7
Freescale Semiconductor, Inc.
General
Description
Min.
Typ.
Max.
Unit
Notes
2.48
2.56
2.64
VLVW2H
VLVW3H
VLVW4H
VHYSH
VLVDL
1
2.62
2.70
2.78
2.72
2.80
2.88
2.82
2.90
2.98
2.92
3.00
3.08
60
mV
1.54
1.60
1.66
VLVW2L
VLVW3L
VLVW4L
VHYSL
1
1.74
1.80
1.86
1.84
1.90
1.96
1.94
2.00
2.06
2.04
2.10
2.16
40
mV
VBG
0.97
1.00
1.03
tLPO
900
1000
1100
Description
Min.
Notes
1, 2
VDD 0.5
VDD 0.5
IOHT
Unit
VOH
Max.
1, 2
VDD 0.5
VDD 0.5
100
mA
General
VOL
Description
Min.
Max.
Unit
Notes
0.5
0.5
0.5
0.5
100
mA
IIN
IIN
0.025
IIN
65
IOZ
RPU
20
50
RPD
20
50
IOLT
1. PTB0, PTB1, PTD6, and PTD7 I/O have both high drive and normal drive capability selected by the associated
PTx_PCRn[DSE] control bit. All other GPIOs are normal drive only.
2. The reset pin only contains an active pull down device when configured as the RESET signal or as a GPIO. When
configured as a GPIO output, it acts as a pseudo open drain output.
3. Measured at VDD = 3.6 V
4. Measured at VDD supply voltage = VDD min and Vinput = VSS
5. Measured at VDD supply voltage = VDD min and Vinput = VDD
Description
After a POR event, amount of time from the
point VDD reaches 1.8 V to execution of the first
Min.
Typ.
Max.
Unit
300
9
Freescale Semiconductor, Inc.
General
Description
Min.
Typ.
Max.
Unit
95
115
93
115
42
53
4.6
4.4
4.4
Description
Temp.
Typ.
Max
Unit
Note
See note
mA
IDD_RUNCO_ CM
6.4
mA
IDD_RUNCO
3.9
4.8
mA
IDD_RUN
5.9
mA
10
Freescale Semiconductor, Inc.
General
Description
IDD_RUN
Temp.
Typ.
Max
Unit
Note
at 25 C
6.2
6.5
mA
3, 4
at 125 C
6.8
7.1
mA
IDD_WAIT
3.1
3.8
mA
IDD_WAIT
2.4
3.2
mA
1.6
mA
777
IDD_VLPRCO
171
420
IDD_VLPR
204
449
IDD_VLPR
262
509
4, 6
IDD_VLPW
Very low power wait mode current core disabled / 4 MHz system / 0.8
MHz bus / flash disabled (flash doze
enabled), all peripheral clocks disabled,
at 3.0 V
123
366
IDD_STOP
at 25 C
319
343
at 50 C
333
365
at 70 C
353
400
at 85 C
380
450
at 105 C
444
572
at 25 C
3.75
8.46
at 50 C
6.66
13.41
at 70 C
12.9
25.71
IDD_PSTOP2
IDD_VLPRCO _CM
IDD_VLPS
11
Freescale Semiconductor, Inc.
General
IDD_LLS
IDD_VLLS3
IDD_VLLS1
IDD_VLLS0
IDD_VLLS0
Description
Temp.
Typ.
Max
Unit
at 85 C
22.7
44.06
at 105 C
48.4
90.1
at 25 C
1.68
2.09
at 50 C
3.05
4.04
at 70 C
5.71
7.75
at 85 C
10
13.54
at 105 C
22.4
30.41
at 25 C
1.22
1.6
at 50 C
2.25
2.31
at 70 C
4.21
5.44
at 85 C
7.37
9.44
at 105 C
16.6
21.76
at 25 C
0.58
0.94
at 50 C
1.26
1.31
at 70 C
2.53
3.33
at 85 C
4.74
6.1
at 105 C
11.4
15.27
at 25 C
0.31
0.65
at 50 C
0.99
1.43
at 70 C
2.25
3.01
at 85 C
4.46
5.83
at 105 C
11.13
14.99
at 25 C
0.12
0.47
at 50 C
0.8
1.24
at 70 C
2.06
2.81
at 85 C
4.27
5.62
at 105 C
10.93
14.78
Note
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See
each module's specification for its supply current.
2. MCG configured for PEE mode. CoreMark benchmark compiled using Keil 4.54 with optimization level 3, optimized for
time.
3. MCG configured for FEI mode.
4. Incremental current consumption from peripheral activity is not included.
5. MCG configured for BLPI mode. CoreMark benchmark compiled using IAR 6.40 with optimization level high, optimized
for balanced.
6. MCG configured for BLPI mode.
7. No brownout.
12
Freescale Semiconductor, Inc.
General
Description
Temperature (C)
Unit
-40
25
50
70
85
105
IIREFSTEN4MHz
56
56
56
56
56
56
IIREFSTEN32KHz
52
52
52
52
52
52
IEREFSTEN4MHz
206
228
237
245
251
258
IEREFSTEN32KHz
VLLS1
440
490
540
560
570
580
nA
VLLS3
440
490
540
560
570
580
LLS
490
490
540
560
570
680
VLPS
510
560
560
560
610
680
STOP
510
560
560
560
610
680
ICMP
22
22
22
22
22
22
IRTC
432
357
388
475
532
810
nA
IUART
MCGIRCLK
(4 MHz
internal
reference
clock)
66
66
66
66
66
66
OSCERCLK
(4 MHz
external
crystal)
214
237
246
254
260
268
MCGIRCLK
(4 MHz
internal
reference
clock)
86
86
86
86
86
86
OSCERCLK
(4 MHz
external
crystal)
235
256
265
274
280
287
ITPM
13
Freescale Semiconductor, Inc.
General
Table 10. Low power mode peripheral adders typical value (continued)
Symbol
Description
Temperature (C)
Unit
-40
25
50
70
85
105
IBG
45
45
45
45
45
45
IADC
366
366
366
366
366
366
2.2.5.1
MCG in FBE for run mode, and BLPE for VLPR mode
USB regulator disabled
No GPIOs toggled
Code execution from flash with cache enabled
For the ALLOFF curve, all peripheral clocks are disabled except FTFA
14
Freescale Semiconductor, Inc.
General
Temperature = 25, VDD = 3, CACHE = Enable, Code Residence = Flash, Clocking Mode = FBE
8.00E-03
7.00E-03
6.00E-03
5.00E-03
4.00E-03
All Off
All On
3.00E-03
2.00E-03
1.00E-03
000.00E+00
'1-1
1
'1-1
2
'1-1
'1-1
'1-1
'1-1
'1-1
'1-2
12
24
48
CLK Ratio
Flash-Core
Core Freq (MHz)
15
Freescale Semiconductor, Inc.
General
400.00E-06
350.00E-06
300.00E-06
250.00E-06
All Off
All On
150.00E-06
100.00E-06
50.00E-06
000.00E+00
'1-1
'1-2
1
'1-2
'1-4
CLK Ratio
Flash-Core
Core Freq (MHz)
Description
Frequency
band
(MHz)
Typ.
Unit
Notes
1, 2
VRE1
0.1550
13
dBV
VRE2
50150
15
dBV
VRE3
150500
12
dBV
VRE4
5001000
dBV
IEC level
0.151000
VRE_IEC
2, 3
1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150
kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits - Measurement
of Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated EmissionsTEM Cell and
16
Freescale Semiconductor, Inc.
General
Wideband TEM Cell Method. Measurements were made while the microcontroller was running basic application code.
The reported emission level is the value of the maximum measured emission, rounded up to the next whole number,
from among the measured orientations in each frequency range.
2. VDD = 3.3 V, TA = 25 C, fOSC = 8 MHz (crystal), fSYS = 48 MHz, fBUS = 48 MHz
3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated EmissionsTEM Cell and
Wideband TEM Cell Method
Description
Input capacitance
Min.
Max.
Unit
pF
Min.
Max.
Unit
Description
Normal run mode
fSYS
48
MHz
fBUS
Bus clock
24
MHz
Flash clock
24
MHz
20
MHz
LPTMR clock
24
MHz
fFLASH
fSYS_USB
fLPTMR
modes1
fSYS
MHz
fBUS
Bus clock
MHz
Flash clock
MHz
24
MHz
fFLASH
fLPTMR
LPTMR
clock2
Table continues on the next page...
17
Freescale Semiconductor, Inc.
General
Description
Min.
Max.
Unit
16
MHz
16
MHz
16
MHz
MHz
MHz
1. The frequency limitations in VLPR and VLPS modes here override any frequency specification listed in the timing
specification for any other module. These same frequency limits apply to VLPS, whether VLPS was entered from RUN
or from VLPR.
2. The LPTMR can be clocked at this speed in VLPR or VLPS only when the source is an external pin.
Min.
Max.
Unit
Notes
1.5
Bus clock
cycles
100
ns
16
ns
36
ns
Description
Min.
Max.
Unit
TJ
40
125
TA
Ambient temperature
40
105
18
Freescale Semiconductor, Inc.
Symbol
Single-layer (1S)
RJA
Four-layer (2s2p)
Description
80
LQFP
64
LQFP
48 QFN 32 QFN
Unit
Notes
70
71
84
92
C/W
RJA
53
52
28
33
C/W
Single-layer (1S)
RJMA
59
69
75
C/W
Four-layer (2s2p)
RJMA
46
22
27
C/W
RJB
34
34
10
12
C/W
RJC
15
20
2.0
1.8
C/W
JT
Thermal characterization
parameter, junction to
package top outside center
(natural convection)
0.6
5.0
C/W
1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
ConditionsNatural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test
Method Environmental ConditionsForced Convection (Moving Air).
2. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental
ConditionsJunction-to-Board.
3. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate
temperature used for the case temperature. The value includes the thermal resistance of the interface material
between the top of the package and the cold plate.
4. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
ConditionsNatural Convection (Still Air).
19
Freescale Semiconductor, Inc.
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
25
MHz
1/J1
ns
20
ns
J2
J3
J4
ns
J9
10
ns
J10
ns
J11
32
ns
J12
ns
J2
J3
J3
SWD_CLK (input)
J4
J4
20
Freescale Semiconductor, Inc.
SWD_CLK
J9
SWD_DIO
J10
SWD_DIO
J12
SWD_DIO
J11
SWD_DIO
Description
Min.
Typ.
Max.
Unit
fints_ft
32.768
kHz
fints_t
31.25
39.0625
kHz
0.3
0.6
%fdco
Notes
21
Freescale Semiconductor, Inc.
Description
fdco_t
fdco_t
fintf_ft
fintf_ft
fintf_t
Min.
Typ.
Max.
Unit
Notes
+0.5/-0.7
%fdco
1, 2
0.4
1.5
%fdco
1, 2
MHz
+1/-2
%fintf_ft
MHz
floc_low
(3/5) x
fints_t
kHz
floc_high
(16/5) x
fints_t
kHz
31.25
39.0625
kHz
20
20.97
25
MHz
40
41.94
48
MHz
23.99
MHz
47.97
MHz
180
ps
ms
48.0
100
MHz
1060
600
2.0
4.0
MHz
FLL
ffll_ref
fdco
3, 4
640 ffll_ref
Mid range (DRS = 01)
1280 ffll_ref
5, 6
732 ffll_ref
Mid range (DRS = 01)
1464 ffll_ref
Jcyc_fll
tfll_acquire
fvco
Ipll
Ipll
fpll_ref
Jcyc_pll
10
fvco = 48 MHz
120
ps
50
ps
Description
Min.
Jacc_pll
Typ.
Max.
Unit
10
fvco = 48 MHz
1350
ps
600
ps
Dlock
1.49
2.98
Dunl
4.47
5.97
tpll_lock
Notes
10-6
150
+ 1075(1/
fpll_ref)
11
1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
mode).
2. The deviation is relative to the factory trimmed frequency at nominal VDD and 25 C, fints_ft.
3. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32 = 0.
4. The resulting system clock frequencies must not exceed their maximum specified values. The DCO frequency
deviation (fdco_t) over voltage and temperature must be considered.
5. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32 = 1.
6. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.
7. This specification is based on standard deviation (RMS) of period or frequency.
8. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,
DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,
FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
9. Excludes any oscillator currents that are also consuming power while PLL is in operation.
10. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise
characteristics of each PCB and results will vary.
11. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL
disabled (BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this
specification assumes it is already running.
Symbol
Description
Min.
Typ.
Max.
Unit
VDD
Supply voltage
1.71
3.6
IDDOSC
Notes
1
32 kHz
500
nA
4 MHz
200
8 MHz (RANGE=01)
300
16 MHz
950
1.2
mA
23
Freescale Semiconductor, Inc.
Description
24 MHz
Min.
Typ.
Max.
Unit
1.5
mA
Notes
32 MHz
IDDOSC
32 kHz
25
4 MHz
400
8 MHz (RANGE=01)
500
16 MHz
2.5
mA
24 MHz
mA
32 MHz
mA
Cx
Cy
RF
10
200
0.6
VDD
0.6
VDD
RS
2, 3
2, 3
2, 4
Vpp
3.3.2.2
Symbol
Typ.
Max.
Unit
32
40
kHz
fosc_hi_1
MHz
fosc_hi_2
32
MHz
fec_extal
48
MHz
tdc_extal
40
50
60
750
ms
250
ms
0.6
ms
ms
fosc_lo
tcst
Description
Notes
1, 2
3, 4
1. Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL.
2. When transitioning from FEI or FBI to FBE mode, restrict the frequency of the input clock so that, when it is divided by
FRDIV, it remains within the limits of the DCO input clock frequency.
3. Proper PC board layout procedures must be followed to achieve specifications.
4. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S
register being set.
25
Freescale Semiconductor, Inc.
3.4.1.1
The following specifications represent the amount of time the internal charge pumps are
active and do not include command overhead.
Table 21. NVM program/erase timing specifications
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
thvpgm4
7.5
18
thversscr
13
113
ms
thversall
52
452
ms
3.4.1.2
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
trd1sec1k
tpgmchk
60
45
trdrsrc
30
tpgm4
65
145
tersscr
14
114
ms
trd1all
1.8
ms
trdonce
25
65
tersall
88
650
ms
tvfykey
30
tpgmonce
3.4.1.3
Symbol
Description
Min.
Typ.
Max.
Unit
IDD_PGM
2.5
6.0
mA
IDD_ERS
1.5
4.0
mA
26
Freescale Semiconductor, Inc.
3.4.1.4
Symbol
Reliability specifications
Description
Min.
Typ.1
Max.
Unit
Notes
Program Flash
tnvmretp10k Data retention after up to 10 K cycles
50
years
tnvmretp1k
20
100
years
nnvmcycp
Cycling endurance
10 K
50 K
cycles
1. Typical data retention values are based on measured response accelerated at high temperature and derated to a
constant 25 C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in
Engineering Bulletin EB619.
2. Cycling endurance represents number of program/erase cycles at -40 C Tj 125 C.
3.6 Analog
3.6.1 ADC electrical specifications
The 16-bit accuracy specifications listed in Table 25 and Table 26 are achievable on
the differential pins ADCx_DP0, ADCx_DM0.
All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy
specifications.
3.6.1.1
Symbol
Description
Conditions
Min.
Typ.1
Max.
Unit
Notes
VDDA
Supply voltage
Absolute
1.71
3.6
VDDA
Supply voltage
-100
+100
mV
VSSA
Ground voltage
-100
+100
mV
VREFH
ADC reference
voltage high
1.13
VDDA
VDDA
VREFL
ADC reference
voltage low
VSSA
VSSA
VSSA
27
Freescale Semiconductor, Inc.
Description
VADIN
Input voltage
CADIN
RADIN
RAS
Input
capacitance
Min.
Typ.1
Max.
Unit
Notes
VREFL
31/32 *
VREFH
VREFL
16-bit mode
10
pF
Conditions
Input series
resistance
Analog source
resistance
(external)
VREFH
fADCK
1.0
18.0
MHz
fADCK
2.0
12.0
MHz
Crate
6
20.000
818.330
Ksps
Continuous conversions
enabled, subsequent
conversion time
Crate
6
37.037
461.467
Ksps
Continuous conversions
enabled, subsequent
conversion time
1. Typical values assume VDDA = 3.0 V, Temp = 25 C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for
reference only, and are not tested in production.
2. DC potential difference.
3. For packages without dedicated VREFH and VREFL pins, VREFH is internally tied to VDDA, and VREFL is internally tied to
VSSA.
4. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as
possible. The results in this data sheet were derived from a system that had < 8 analog source resistance. The
RAS/CAS time constant should be kept to < 1 ns.
5. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear.
6. For guidelines and examples of conversion rate calculation, download the ADC calculator tool.
28
Freescale Semiconductor, Inc.
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
ZADIN
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
leakage
due to
input
protection
ZAS
RAS
ADC SAR
ENGINE
RADIN
VADIN
CAS
VAS
RADIN
INPUT PIN
RADIN
INPUT PIN
RADIN
INPUT PIN
CADIN
3.6.1.2
Description
IDDA_ADC
Supply current
ADC
asynchronous
clock source
fADACK
Conditions1
ADLPC = 1, ADHSC =
0
ADLPC = 1, ADHSC =
1
ADLPC = 0, ADHSC =
0
Min.
Typ.2
Max.
Unit
Notes
0.215
1.7
mA
1.2
2.4
3.9
MHz
2.4
4.0
6.1
MHz
tADACK =
1/fADACK
3.0
5.2
7.3
MHz
4.4
6.2
9.5
MHz
LSB4
LSB4
ADLPC = 0, ADHSC =
1
Sample Time
TUE
DNL
Total unadjusted
error
12-bit modes
6.8
<12-bit modes
1.4
2.1
Differential nonlinearity
12-bit modes
0.7
1.1 to
+1.9
<12-bit modes
0.2
0.3 to 0.5
29
Freescale Semiconductor, Inc.
Table 26. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Symbol
INL
Description
Integral nonlinearity
EFS
Full-scale error
EQ
Quantization
error
ENOB
Conditions1
Min.
Typ.2
Max.
Unit
Notes
2.7 to
+1.9
LSB4
LSB4
VADIN =
VDDA5
12-bit modes
1.0
<12-bit modes
0.5
12-bit modes
5.4
<12-bit modes
1.4
1.8
16-bit modes
1 to 0
13-bit modes
0.5
12.8
14.5
bits
11.9
13.8
bits
12.2
13.9
bits
11.4
13.1
bits
0.7 to
+0.5
LSB4
Avg = 4
16-bit single-ended mode
Avg = 32
Avg = 4
SINAD
THD
Signal-to-noise
plus distortion
See ENOB
Total harmonic
distortion
dB
-94
dB
-85
dB
82
95
dB
78
90
dB
Avg = 32
16-bit single-ended mode
Avg = 32
SFDR
Spurious free
dynamic range
Avg = 32
16-bit single-ended mode
Avg = 32
EIL
Input leakage
error
IIn RAS
mV
IIn =
leakage
current
(refer to
the MCU's
voltage
and
current
operating
ratings)
VTEMP25
Temp sensor
slope
1.55
1.62
1.69
mV/C
Temp sensor
voltage
25 C
706
716
726
mV
30
Freescale Semiconductor, Inc.
15.00
14.70
14.40
14.10
ENOB
13.80
13.50
13.20
12.90
12.60
Hardware Averaging Disabled
Averaging of 4 samples
Averaging of 8 samples
Averaging of 32 samples
12.30
12.00
10
11
12
14.00
13.75
13.50
13.25
13.00
ENOB
12.75
12.50
12.25
12.00
11.75
11.50
11.25
11.00
Averaging of 4 samples
Averaging of 32 samples
10
11
12
31
Freescale Semiconductor, Inc.
Description
Min.
Typ.
Max.
Unit
VDD
Supply voltage
1.71
3.6
IDDHS
200
IDDLS
20
VAIN
VSS
VDD
VAIO
20
mV
CR0[HYSTCTR] = 00
mV
CR0[HYSTCTR] = 01
10
mV
CR0[HYSTCTR] = 10
20
mV
CR0[HYSTCTR] = 11
30
mV
VH
VCMPOh
Output high
VDD 0.5
VCMPOl
Output low
0.5
tDHS
20
50
200
ns
tDLS
80
250
600
ns
40
IDAC6b
INL
0.5
0.5
LSB3
DNL
0.3
0.3
LSB
1. Typical hysteresis is measured with input voltage range limited to 0.7 to VDD 0.7 V.
2. Comparator initialization delay is defined as the time between software writes to change control inputs (writes to
DACEN, VRSEL, PSEL, MSEL, VOSEL) and the comparator output settling to a stable level.
3. 1 LSB = Vreference/64
32
Freescale Semiconductor, Inc.
70.00E-03
60.00E-03
HYSTCTR
Setting
50.00E-03
0
1
2
3
40.00E-03
30.00E-03
20.00E-03
10.00E-03
000.00E+00
0.1
0.4
0.7
1.3
1.6
1.9
Vinn (V)
2.2
2.5
2.8
3.1
Figure 10. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0)
CMP Hysteresis vs Vinn
180.00E-03
160.00E-03
140.00E-03
120.00E-03
HYSTCTR
Setting
100.00E-03
0
1
2
3
80.00E-03
60.00E-03
40.00E-03
20.00E-03
000.00E+00
0.1
0.4
-20.00E-03
0.7
1.3
1.6
1.9
2.2
2.5
2.8
3.1
Vinn (V)
Figure 11. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1)
33
Freescale Semiconductor, Inc.
3.6.3.1
Symbol
Desciption
Min.
Max.
Unit
VDDA
Supply voltage
1.71
3.6
VDACR
Reference voltage
Notes
1.13
3.6
CL
100
pF
IL
mA
3.6.3.2
Symbol
Description
Min.
Typ.
Max.
Unit
250
900
Notes
tDACLP
100
200
tDACHP
15
30
0.7
Vdacoutl
DAC output voltage range low highspeed mode, no load, DAC set to 0x000
100
mV
Vdacouth
DAC output voltage range high highspeed mode, no load, DAC set to 0xFFF
VDACR
100
VDACR
mV
INL
LSB
DNL
LSB
DNL
LSB
0.4
0.8
%FSR
Gain error
0.1
0.6
%FSR
60
90
dB
TCO
3.7
V/C
TGE
0.000421
%FSR/C
Rop
250
SR
V/s
1.2
1.7
Description
High power (SPHP)
Min.
Typ.
Max.
0.05
0.12
Unit
Notes
1.
2.
3.
4.
5.
6.
3dB bandwidth
kHz
550
40
-2
-4
-6
-8
0
500
1000
1500
2000
2500
3000
3500
4000
Digital Code
35
Freescale Semiconductor, Inc.
1.499
1.4985
1.498
1.4975
1.497
1.4965
1.496
55
25
-40
85
105
125
Temperature C
3.7 Timers
See General switching specifications.
36
Freescale Semiconductor, Inc.
NOTE
The MCGPLLCLK meets the USB jitter specifications for
certification with the use of an external clock/crystal for
both Device and Host modes.
The MCGFLLCLK does not meet the USB jitter
specifications for certification.
Description
Min.
Typ.1
Max.
Unit
VREGIN
2.7
5.5
IDDon
125
186
IDDstby
1.1
10
IDDoff
650
nA
120
mA
ILOADstby
mA
3.3
3.6
2.1
2.8
3.6
2.1
3.6
1.76
2.2
8.16
Notes
ESR
100
ILIM
290
mA
37
Freescale Semiconductor, Inc.
Symbol
fop
tSPSCK
tLead
tLag
tWSPSCK
tSU
Min.
Max.
Unit
Note
fperiph/2048
fperiph/2
Hz
2 x tperiph
2048 x
tperiph
ns
1/2
tSPSCK
1/2
tSPSCK
tperiph 30
1024 x
tperiph
ns
16
ns
tHI
ns
tv
10
ns
tHO
ns
10
tRI
tperiph 25
ns
tFI
tRO
25
ns
tFO
11
Description
Frequency of operation
SPSCK period
1. For SPI0, fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS).
2. tperiph = 1/fperiph
Table 32. SPI master mode timing on slew rate enabled pads
Num.
Symbol
fop
tSPSCK
tLead
tLag
tWSPSCK
tSU
Description
Min.
Max.
Unit
Note
fperiph/2048
fperiph/2
Hz
2 x tperiph
2048 x
tperiph
ns
1/2
tSPSCK
1/2
tSPSCK
tperiph 30
1024 x
tperiph
ns
96
ns
Frequency of operation
SPSCK period
Table 32. SPI master mode timing on slew rate enabled pads (continued)
Num.
Symbol
tHI
tv
9
10
11
Description
Min.
Max.
Unit
Note
ns
52
ns
tHO
ns
tRI
tperiph 25
ns
tFI
tRO
36
ns
tFO
1. For SPI0, fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS).
2. tperiph = 1/fperiph
SS1
(OUTPUT)
3
SPSCK
(CPOL=0)
(OUTPUT)
11
10
11
5
5
SPSCK
(CPOL=1)
(OUTPUT)
6
MISO
(INPUT)
10
MSB IN2
BIT 6 . . . 1
LSB IN
8
MOSI
(OUTPUT)
MSB OUT2
BIT 6 . . . 1
9
LSB OUT
1. If configured as an output.
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
39
Freescale Semiconductor, Inc.
2
3
SPSCK
(CPOL=0)
(OUTPUT)
SPSCK
(CPOL=1)
(OUTPUT)
6
MISO
(INPUT)
11
10
11
7
MSB IN2
BIT 6 . . . 1
LSB IN
8
MOSI
(OUTPUT)
10
BIT 6 . . . 1
PORT DATA
Symbol
fop
tSPSCK
tLead
tLag
tWSPSCK
tSU
Min.
Max.
Unit
Note
fperiph/4
Hz
4 x tperiph
ns
tperiph
tperiph
tperiph 30
ns
ns
tHI
ns
ta
tperiph
ns
tdis
tperiph
ns
10
tv
22
ns
11
tHO
ns
12
tRI
tperiph 25
ns
tFI
tRO
25
ns
tFO
13
1.
2.
3.
4.
Description
Frequency of operation
SPSCK period
For SPI0, fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS).
tperiph = 1/fperiph
Time to data active from high-impedance state
Hold time to high-impedance state
38
40
<<CLASSIFICATION>>
<<NDA MESSAGE>>
Table 34. SPI slave mode timing on slew rate enabled pads
Num.
Symbol
fop
tSPSCK
tLead
tLag
tWSPSCK
tSU
Frequency of operation
SPSCK period
Min.
Max.
Unit
Note
fperiph/4
Hz
4 x tperiph
ns
tperiph
tperiph
tperiph 30
ns
ns
tHI
ns
ta
tperiph
ns
tdis
tperiph
ns
10
tv
122
ns
11
tHO
ns
12
tRI
tperiph 25
ns
tFI
tRO
36
ns
tFO
13
1.
2.
3.
4.
Description
For SPI0, fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS).
tperiph = 1/fperiph
Time to data active from high-impedance state
Hold time to high-impedance state
SS
(INPUT)
12
13
12
13
SPSCK
(CPOL=0)
(INPUT)
5
SPSCK
(CPOL=1)
(INPUT)
9
8
MISO
(OUTPUT)
see
note
SLAVE MSB
6
MOSI
(INPUT)
10
11
11
BIT 6 . . . 1
SEE
NOTE
7
MSB IN
BIT 6 . . . 1
LSB IN
41
Freescale Semiconductor, Inc.
2
3
SPSCK
(CPOL=0)
(INPUT)
SPSCK
(CPOL=1)
(INPUT)
see
note
SLAVE
MSB OUT
MOSI
(INPUT)
13
12
13
11
10
MISO
(OUTPUT)
12
9
BIT 6 . . . 1
BIT 6 . . . 1
LSB IN
7
MSB IN
Symbol
Standard Mode
Fast Mode
Minimum
Maximum
Minimum
Maximum
Unit
fSCL
100
4001
kHz
tHD; STA
0.6
tLOW
4.7
1.3
tHIGH
0.6
tSU; STA
4.7
0.6
tHD; DAT
02
3.453
04
0.92
tSU; DAT
2505
1003, 6
ns
tr
1000
20 +0.1Cb
300
ns
tf
300
20 +0.1Cb6
300
ns
tSU; STO
0.6
tBUF
4.7
1.3
tSP
N/A
N/A
50
ns
1. The maximum SCL Clock Frequency in Fast mode with maximum bus loading can only achieved when using the High
drive pins (see Voltage and current operating behaviors) or when using the Normal drive pins and VDD 2.7 V
42
Freescale Semiconductor, Inc.
tf
tSU; DAT
tr
tLOW
tf
tHD; STA
tSP
tr
tBUF
SCL
HD; STA
tHD; DAT
tHIGH
tSU; STA
tSU; STO
SR
Figure 18. Timing definition for fast and standard mode devices on the I2C bus
3.8.5 UART
See General switching specifications.
Description
Min.
Typ.
Max.
Unit
TSI_RUNF
100
TSI_RUNV
1.0
128
TSI_EN
100
TSI_DIS
1.2
TSI_TEN
66
TSI_CREF
1.0
pF
TSI_DVOLT
0.19
1.03
43
Freescale Semiconductor, Inc.
Dimensions
4 Dimensions
4.1 Obtaining package dimensions
Package dimensions are provided in package drawings.
To find a package drawing, go to freescale.com and perform a keyword search for the
drawings document number:
If you want the drawing for this package
32-pin QFN
98ASA00473D
48-pin QFN
98ASA00466D
64-pin LQFP
98ASS23234W
80-pin LQFP
98ASS23174W
5 Pinout
5.1 KL25 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
80
64
48
LQFP LQFP QFN
32
QFN
Pin Name
Default
ALT0
ALT1
ALT2
PTE0
DISABLED
PTE0
PTE1
DISABLED
PTE1
SPI1_MOSI
PTE2
DISABLED
PTE2
SPI1_SCK
PTE3
DISABLED
PTE3
SPI1_MISO
PTE4
DISABLED
PTE4
SPI1_PCS0
PTE5
DISABLED
PTE5
VDD
VDD
VDD
VSS
VSS
VSS
USB0_DP
USB0_DP
USB0_DP
10
USB0_DM
USB0_DM
USB0_DM
44
Freescale Semiconductor, Inc.
ALT3
UART1_TX
UART1_RX
ALT4
RTC_
CLKOUT
ALT5
ALT6
CMP0_OUT
I2C1_SDA
SPI1_MISO
I2C1_SCL
ALT7
SPI1_MOSI
Pinout
80
64
48
LQFP LQFP QFN
11
12
13
14
32
QFN
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
VOUT33
VOUT33
VOUT33
VREGIN
VREGIN
VREGIN
PTE20
ADC0_DP0/
ADC0_SE0
ADC0_DP0/
ADC0_SE0
PTE20
TPM1_CH0
UART0_TX
10
PTE21
TPM1_CH1
UART0_RX
15
11
PTE22
ADC0_DP3/
ADC0_SE3
PTE22
TPM2_CH0
UART2_TX
16
12
PTE23
TPM2_CH1
UART2_RX
17
13
VDDA
VDDA
VDDA
18
14
10
VREFH
VREFH
VREFH
19
15
11
VREFL
VREFL
VREFL
20
16
12
VSSA
VSSA
VSSA
21
17
13
PTE29
TPM0_CH2
TPM_
CLKIN0
22
18
14
PTE30
TPM0_CH3
TPM_
CLKIN1
23
19
PTE31
DISABLED
PTE31
TPM0_CH4
24
20
15
PTE24
DISABLED
PTE24
TPM0_CH0
I2C0_SCL
25
21
16
PTE25
DISABLED
PTE25
TPM0_CH1
I2C0_SDA
26
22
17
10
PTA0
SWD_CLK
TSI0_CH1
PTA0
TPM0_CH5
27
23
18
11
PTA1
DISABLED
TSI0_CH2
PTA1
UART0_RX
TPM2_CH0
28
24
19
12
PTA2
DISABLED
TSI0_CH3
PTA2
UART0_TX
TPM2_CH1
29
25
20
13
PTA3
SWD_DIO
TSI0_CH4
PTA3
I2C1_SCL
TPM0_CH0
SWD_DIO
30
26
21
14
PTA4
NMI_b
TSI0_CH5
PTA4
I2C1_SDA
TPM0_CH1
NMI_b
31
27
PTA5
DISABLED
PTA5
USB_CLKIN
TPM0_CH2
32
28
PTA12
DISABLED
PTA12
TPM1_CH0
33
29
PTA13
DISABLED
PTA13
TPM1_CH1
34
PTA14
DISABLED
PTA14
SPI0_PCS0
UART0_TX
35
PTA15
DISABLED
PTA15
SPI0_SCK
UART0_RX
36
PTA16
DISABLED
PTA16
SPI0_MOSI
SPI0_MISO
37
PTA17
DISABLED
PTA17
SPI0_MISO
SPI0_MOSI
38
30
22
15
VDD
VDD
VDD
39
31
23
16
VSS
VSS
VSS
40
32
24
17
PTA18
EXTAL0
EXTAL0
PTA18
UART1_RX
TPM_
CLKIN0
41
33
25
18
PTA19
XTAL0
XTAL0
PTA19
UART1_TX
TPM_
CLKIN1
42
34
26
19
PTA20
RESET_b
43
35
27
20
PTB0/
LLWU_P5
ADC0_SE8/
TSI0_CH0
ADC0_DP3/
ADC0_SE3
PTA20
ADC0_SE8/
TSI0_CH0
PTB0/
LLWU_P5
SWD_CLK
LPTMR0_
ALT1
RESET_b
I2C0_SCL
TPM1_CH0
45
Freescale Semiconductor, Inc.
Pinout
80
64
48
LQFP LQFP QFN
32
QFN
Pin Name
Default
ALT0
ADC0_SE9/
TSI0_CH6
ALT1
ALT2
ALT3
ALT4
ALT5
44
36
28
21
PTB1
ADC0_SE9/
TSI0_CH6
PTB1
I2C0_SDA
TPM1_CH1
45
37
29
PTB2
I2C0_SCL
TPM2_CH0
46
38
30
PTB3
I2C0_SDA
TPM2_CH1
47
PTB8
DISABLED
PTB8
48
PTB9
DISABLED
PTB9
49
PTB10
DISABLED
PTB10
SPI1_PCS0
50
PTB11
DISABLED
PTB11
SPI1_SCK
51
39
31
PTB16
TSI0_CH9
TSI0_CH9
PTB16
SPI1_MOSI
UART0_RX
TPM_
CLKIN0
SPI1_MISO
52
40
32
PTB17
TSI0_CH10
TSI0_CH10
PTB17
SPI1_MISO
UART0_TX
TPM_
CLKIN1
SPI1_MOSI
53
41
PTB18
TSI0_CH11
TSI0_CH11
PTB18
TPM2_CH0
54
42
PTB19
TSI0_CH12
TSI0_CH12
PTB19
TPM2_CH1
55
43
33
PTC0
56
44
34
22
PTC1/
LLWU_P6/
RTC_CLKIN
I2C1_SCL
TPM0_CH0
57
45
35
23
PTC2
I2C1_SDA
TPM0_CH1
58
46
36
24
PTC3/
LLWU_P7
DISABLED
59
47
VSS
VSS
VSS
60
48
VDD
VDD
VDD
61
49
37
25
PTC4/
LLWU_P8
DISABLED
PTC4/
LLWU_P8
62
50
38
26
PTC5/
LLWU_P9
DISABLED
63
51
39
27
PTC6/
LLWU_P10
CMP0_IN0
64
52
40
28
PTC7
65
53
66
54
67
55
68
56
69
EXTRG_IN
PTC3/
LLWU_P7
CMP0_OUT
TPM0_CH2
SPI0_PCS0
UART1_TX
TPM0_CH3
PTC5/
LLWU_P9
SPI0_SCK
LPTMR0_
ALT2
CMP0_IN0
PTC6/
LLWU_P10
SPI0_MOSI
EXTRG_IN
CMP0_IN1
CMP0_IN1
PTC7
SPI0_MISO
PTC8
CMP0_IN2
CMP0_IN2
PTC8
I2C0_SCL
TPM0_CH4
PTC9
CMP0_IN3
CMP0_IN3
PTC9
I2C0_SDA
TPM0_CH5
PTC10
DISABLED
PTC10
I2C1_SCL
PTC11
DISABLED
PTC11
I2C1_SDA
PTC12
DISABLED
PTC12
TPM_
CLKIN0
70
PTC13
DISABLED
PTC13
TPM_
CLKIN1
71
PTC16
DISABLED
PTC16
72
PTC17
DISABLED
PTC17
ALT7
EXTRG_IN
UART1_RX
46
ALT6
CLKOUT
CMP0_OUT
SPI0_MISO
SPI0_MOSI
Pinout
80
64
48
LQFP LQFP QFN
32
QFN
Pin Name
Default
ALT0
ALT1
PTD0
ALT2
ALT3
ALT5
73
57
41
PTD0
DISABLED
74
58
42
PTD1
SPI0_SCK
75
59
43
PTD2
DISABLED
PTD2
SPI0_MOSI
UART2_RX
TPM0_CH2
SPI0_MISO
76
60
44
PTD3
DISABLED
PTD3
SPI0_MISO
UART2_TX
TPM0_CH3
SPI0_MOSI
77
61
45
29
PTD4/
LLWU_P14
DISABLED
PTD4/
LLWU_P14
SPI1_PCS0
UART2_RX
TPM0_CH4
78
62
46
30
PTD5
SPI1_SCK
UART2_TX
TPM0_CH5
79
63
47
31
PTD6/
LLWU_P15
SPI1_MOSI
UART0_RX
SPI1_MISO
80
64
48
32
PTD7
DISABLED
SPI1_MISO
UART0_TX
SPI1_MOSI
PTD7
SPI0_PCS0
ALT4
ALT6
ALT7
TPM0_CH0
TPM0_CH1
47
Freescale Semiconductor, Inc.
PTD7
PTD6/LLWU_P15
PTD5
PTD4/LLWU_P14
PTD3
PTD2
PTD1
PTD0
PTC17
PTC16
PTC13
PTC12
PTC11
PTC10
PTC9
PTC8
PTC7
PTC6/LLWU_P10
PTC5/LLWU_P9
PTC4/LLWU_P8
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
Pinout
PTB10
PTE20
13
48
PTB9
PTE21
14
47
PTB8
PTE22
15
46
PTB3
PTE23
16
45
PTB2
VDDA
17
44
PTB1
VREFH
18
43
PTB0/LLWU_P5
VREFL
19
42
PTA20
VSSA
20
41
PTA19
40
49
PTA18
12
39
VREGIN
VSS
PTB11
38
50
VDD
11
37
VOUT33
PTA17
PTB16
36
51
PTA16
10
35
USB0_DM
PTA15
PTB17
34
52
PTA14
33
USB0_DP
PTA13
PTB18
32
53
PTA12
31
VSS
PTA5
PTB19
30
54
PTA4
29
VDD
PTA3
PTC0
28
55
PTA2
PTC1/LLWU_P6/RTC_CLKIN
27
56
PTE5
PTA1
PTC2
26
57
PTE4
PTA0
PTE3
25
PTC3/LLWU_P7
PTE25
58
24
PTE2
PTE24
VSS
23
59
PTE31
2
3
22
PTE1
PTE30
VDD
21
60
PTE29
PTE0
48
Freescale Semiconductor, Inc.
PTD7
PTD6/LLWU_P15
PTD5
PTD4/LLWU_P14
PTD3
PTD2
PTD1
PTD0
PTC11
PTC10
PTC9
PTC8
PTC7
PTC6/LLWU_P10
PTC5/LLWU_P9
PTC4/LLWU_P8
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
Pinout
PTB18
PTE20
40
PTB17
PTE21
10
39
PTB16
PTE22
11
38
PTB3
PTE23
12
37
PTB2
VDDA
13
36
PTB1
VREFH
14
35
PTB0/LLWU_P5
VREFL
15
34
PTA20
VSSA
16
33
PTA19
PTA18
32
41
31
VSS
VREGIN
30
PTB19
VDD
42
29
PTA13
VOUT33
28
PTC0
PTA12
43
27
PTA5
USB0_DM
26
PTC1/LLWU_P6/RTC_CLKIN
PTA4
44
25
PTA3
USB0_DP
24
PTC2
PTA2
45
23
PTA1
VSS
22
PTC3/LLWU_P7
PTA0
46
21
PTE25
VDD
20
VSS
PTE24
47
19
PTE31
PTE1
18
VDD
PTE30
48
17
PTE29
PTE0
49
Freescale Semiconductor, Inc.
PTD7
PTD6/LLWU_P15
PTD5
PTD4/LLWU_P14
PTD3
PTD2
PTD1
PTD0
PTC7
PTC6/LLWU_P10
PTC5/LLWU_P9
PTC4/LLWU_P8
48
47
46
45
44
43
42
41
40
39
38
37
Pinout
PTE20
30
PTB3
PTE21
29
PTB2
VDDA
28
PTB1
VREFH
10
27
PTB0/LLWU_P5
VREFL
11
26
PTA20
VSSA
12
25
PTA19
24
PTB16
PTA18
31
23
VSS
VREGIN
22
PTB17
VDD
32
21
PTA4
VOUT33
20
PTC0
PTA3
33
19
PTA2
USB0_DM
18
PTC1/LLWU_P6/RTC_CLKIN
PTA1
34
17
PTA0
USB0_DP
16
PTC2
PTE25
35
15
PTE24
VSS
14
PTC3/LLWU_P7
PTE30
36
13
PTE29
VDD
50
Freescale Semiconductor, Inc.
PTD7
PTD6/LLWU_P15
PTD5
PTD4/LLWU_P14
PTC7
PTC6/LLWU_P10
PTC5/LLWU_P9
PTC4/LLWU_P8
32
31
30
29
28
27
26
25
Ordering parts
VOUT33
20
PTB0/LLWU_P5
VREGIN
19
PTA20
VDDA
18
PTA19
VSSA
17
PTA18
16
PTB1
VSS
21
15
VDD
USB0_DM
14
PTC1/LLWU_P6/RTC_CLKIN
PTA4
22
13
PTA3
USB0_DP
12
PTC2
PTA2
23
11
PTA1
VSS
10
PTC3/LLWU_P7
PTA0
24
PTE30
PTE0
6 Ordering parts
6.1 Determining valid orderable parts
Valid orderable part numbers are provided on the web. To determine the orderable
part numbers for this device, go to freescale.com and perform a part number search
for the following device numbers: PKL25 and MKL25
7 Part identification
Kinetis KL25 Sub-Family, Rev5 08/2014.
51
Freescale Semiconductor, Inc.
Part identification
7.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
7.2 Format
Part numbers for this device have the following format:
Q KL## A FFF R T PP CC N
7.3 Fields
This table lists the possible values for each field in the part number (not all
combinations are valid):
Table 37. Part number fields descriptions
Field
Description
Values
Qualification status
KL##
Kinetis family
KL25
Key attribute
Z = Cortex-M0+
FFF
32 = 32 KB
64 = 64 KB
128 = 128 KB
Silicon revision
(Blank) = Main
A = Revision after main
V = 40 to 105
PP
Package identifier
CC
4 = 48 MHz
Packaging type
52
Freescale Semiconductor, Inc.
FM = 32 QFN (5 mm x 5 mm)
FT = 48 QFN (7 mm x 7 mm)
LH = 64 LQFP (10 mm x 10 mm)
LK = 80 LQFP (12 mm x 12 mm)
7.4 Example
This is an example part number:
MKL25Z64VLK4
8.1.1 Example
This is an example of an operating requirement:
Symbol
VDD
Description
1.0 V core supply
voltage
Min.
0.9
Max.
1.1
Unit
V
8.2.1 Example
This is an example of an operating behavior:
Symbol
IWP
Description
Digital I/O weak pullup/ 10
pulldown current
Min.
Max.
130
Unit
A
53
Freescale Semiconductor, Inc.
8.3.1 Example
This is an example of an attribute:
Symbol
CIN_D
Description
Input capacitance:
digital pins
Min.
Max.
7
Unit
pF
8.4.1 Example
This is an example of an operating rating:
Symbol
VDD
Description
1.0 V core supply
voltage
54
Freescale Semiconductor, Inc.
Min.
0.3
Max.
1.2
Unit
V
40
30
20
10
Operating rating
Measured characteristic
era
Op
in
rat
tin
)
in.
(m
g
tin
era
Op
ui
req
nt
e
rem
in.
(m
ax
t (m
en
rem
g(
tin
era
Op
u
req
tin
era
Op
in
rat
.)
x
ma
Fatal range
Fatal range
- No permanent failure
- Possible decreased life
- Possible incorrect operation
- No permanent failure
- Correct operation
- No permanent failure
- Possible decreased life
- Possible incorrect operation
ng
dli
n
Ha
ng
ati
.)
in.
(m
ng
li
nd
Ha
ng
ati
ax
(m
Fatal range
Handling range
Fatal range
No permanent failure
55
Freescale Semiconductor, Inc.
8.8.1 Example 1
This is an example of an operating behavior that includes a typical value:
Symbol
IWP
Description
Digital I/O weak
pullup/pulldown
current
Min.
10
Typ.
70
Max.
130
Unit
A
8.8.2 Example 2
This is an example of a chart that shows typical values for various voltage and
temperature conditions:
56
Freescale Semiconductor, Inc.
Revision history
5000
4500
4000
TJ
IDD_STOP (A)
3500
150 C
3000
105 C
2500
25 C
2000
40 C
1500
1000
500
0
0.90
0.95
1.05
1.00
1.10
VDD (V)
Description
Value
Unit
TA
Ambient temperature
25
VDD
3.3
9 Revision history
The following table provides a revision history for this document.
Table 39. Revision history
Rev. No.
Date
Substantial Changes
9/2012
9/2012
3/2014
57
Freescale Semiconductor, Inc.
Revision history
Date
Substantial Changes
58
Freescale Semiconductor, Inc.
08/2014