Lab 11 Report

Design of a Two-Stage Amplifier with Miller

Compensation
Kevin Bradshaw & Kai Qin
ECEN 326-502
Instructor: Sebastian Hoyos
Date Performed: April 22, 2016

Objectives
Understand the uses of a Miller compensation capacitor.
Design and analyze a two-stage amplifier configuration meeting certain constraints.
Evaluate the DC operating point of the transistor amplifier with proper feedback on top
of having a capacitor as the load.
Procedure
In this lab, the amplifier circuit designed from the pre-lab was constructed. The amplifier
was designed to fit the constraints shown in Figure 1:
Figure 1: Amplifier Design Constraints

Using a chosen value for the collector current through the differential, the current source
BJTs were designed accordingly. The base resistors of the current sources were
chosen using KVL. Using each current and the known emitter resistance value, the rest
of the emitter resistances were chosen. Then the small signal parameters were all
calculated for transistors 2, 3, 6, and 6. Using these values, the gain was calculated.
Lastly, the Miller compensation capacitor values were calculated for three different poles
at 30, 45, and 60. These values were tuned to find the proper poles for the
constraints. Figure 2 shows the resulting circuit designed and the actual values used in
the circuit. These values were adjusted after construction in order to get an optimum
gain.

Figure 2: BJT Shunt-Series Amplifier

After the circuit was adjusted, the operating currents and voltages were measured and
can be seen in Table 1. Furthermore, the miller capacitances used for the different
phase margins are listed in Table 2. The overall gain (dB) of this circuit can be seen in
Figure 3. The open loop bode plot can be seen in Figure 4. The closed loop bode plot
can be seen in Figure 5. Figures 6, 7, and 8 show the different phase margin for each
Miller capacitor used.

Figure 3: Overall Gain

Figure 4: Open Loop Configuration Bode Plot

Figure 5: Closed Loop Configuration Bode Plot

Figure 6: 30 Phase Margin

Figure 7: 45 Phase Margin

Figure 8: 60 Phase Margin

Data Tables
Table 1: Operating Bias Points
VB

VE

VC

IC

Q1

-3.82 mV

-0.68 V

4.32 V

1.66 mA

Q2

-4.7 mV

-0.66 V

4.27 V

1.76 mA

Q3

4.32 V

5V

4.32 V

1.66 mA

Q4

4.32 V

5V

4.274 V

1.76 mA

Q5

-3.64 V

-4.31 V

-1.01 V

3.44 mA

Q6

-3.64 V

-4.30 V

4.95 V

3.97 mA

Q7

4.27 V

5V

4.95 V

3.45 mA

Table 2: Measured Circuit Values

Phase Margin
30

Miller Capacitor Value

100 pF

45

1 nF

60

10 nF

Discussion
The overall circuit met the specification for closed loop gain. It was difficult to test this
circuit because of transistor Q7. It had some strange heating effects that caused it only
to be in the active region of operation when a thumb was placed on it. This increased
the heat which increased the gain. The closed loop gain was met and the Miller
capacitance tuned was found to give the optimum phase margin at 30.
Conclusion
The main lessons of this lab was to understand the feedback connection with a load
capacitor as well as the miller compensation in an amplifier. From this lab we have a
better understanding of how different capacitor values will affect the midband gain of the
circuit. Lastly, this configuration shows the proper connection of how the inside of an opamp truly works.