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phys. stat. sol. (c) 5, No. 12, 36813685 (2008) / DOI 10.1002/pssc.200780121

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current topics in solid state physics

High-frequency scalable
compact modelling of Si RF-CMOS technology

Antonios Bazigos1, Matthias Bucher*, 2, Paulius Sakalas3, 4, Michael Schroter4, 5, and Wolfgang Kraus6
1

National Technical University of Athens, 15780 Athens, Greece

Technical University of Crete, 73100 Chania, Greece
3
FPL, Semiconductor Physics Institute, 01108 Vilnius, Lithuania
4
Technical University of Dresden, 01069 Dresden, Germany
5
ECE Department, University of California San Diego, USA
6
Atmel, 74072 Heilbronn, Germany
2

Received 14 November 2007, accepted 19 November 2007

Published online 16 September 2008
PACS 85.30.Tv, 85.40.Bh
*

Corresponding author: e-mail bucher@electronics.tuc.gr, Phone: +30 28210 37210, Fax: +30 28210 37542

The aggressive downscaling of CMOS technologies offers record transit frequencies well above 100 GHz. Efficient RF
circuit design, employing such technologies, demands nonlinear, scalable compact models with high accuracy up to
high frequencies. EKV3 is an advanced MOSFET model,

based on charge sheet theory, that meets such demands.

Within this paper, the model is validated against DC and RF
measurements up to 30 GHz, for various devices of a modern
180 nm CMOS technology.

2008 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim

1 Introduction Modern deep submicron CMOS technologies offer record transit frequencies, while using ever
lower supply voltages. Efficient RF circuit design, employing such technologies, is based on ever more complex
compact models for circuit simulation, that describe precisely the nonlinear, analogue behaviour of the MOSFETs
up to high frequencies. EKV3 [1, 2] is an advanced,
scalable non-linear MOSFET compact model based on the
charge-sheet theory, which uses a unified equation set
to describe static to high-frequency behaviour in all operating regions. The model has been verified [3, 4] against
several advanced CMOS technologies with drawn gate
lengths down to 65 nm and has shown excellent fitting results.
The paper provides an extended RF validation of
EKV3 for a 180 nm CMOS process, which is currently a
preferred length for analog production design in industry.
An extended number of RF devices were fabricated in a
180 nm RF CMOS technology by Atmel. DC characteristics and S-parameters up to 30 GHz were measured over a
wide range of geometries bias conditions. Scalability issues of the multi-finger RF device structure are addressed.
The EKV3 model is validated for DC and RF performance.

Evaluation of RF IC design-relevant quantities, such as Yparameters, transit frequency, unilateral gain and maximum oscillation frequency versus bias current, is presented.
2 Experimental Within this work, a study on RF devices from a modern Si CMOS technology is conducted.
The process is a double-poly, twin-well process with 4
metal layers, rated at 1.8 V. The process offers many analog options such as analog metals, additional well etc. The
gate length L of the RF devices fabricated ranges from the
minimum of 180 nm to 360 nm. The width Wf of each finger ranges between 1 m and 4 m while the number of
fingers NF from 1 to 9. Both NMOS and PMOS devices
were studied. DC and RF measurements were performed
on all devices.
Two port S-parameter measurements were performed
on-wafer with an HP8510C vector network analyzer from
50 MHz to 30 GHz, with CW input power of -5 dBm and
attenuation of 10 dB on Port 1 (gate), and an averaging
factor of 256. CW power overdrive was controlled and was
not present due to large pad parasitics in comparison to the
tiny DUT. S-Parameters of a DUT were obtained after a
careful OPEN and SHORT de-embedding procedure. On 2008 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim

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A. Bazigos et al.: High-frequency scalable compact modelling of Si RF-CMOS technology

(a)

(b)
Figure 1 (a) A chip microphotograph showing the MOSFET device, the Ground-Signal-Ground pads and the RF probes after
they have made contact. (b) Layout of a typical multi-finger MOS
transistor for HF applications (NMOS; NF = 9).

wafer test structures were accessed with G-S-G 150 m

pitch RF probes. DC losses were accounted for by using
Kelvin type bias-Tees. A contact pad resistance was measured and de-embedded. A chip microphotograph and a
schematic representation of a typical layout of the RF devices is shown in Fig. 1.
3 Model validation Modern Si RF-CMOS technologies offer the designer a viable solution for low-power circuits with operating frequencies even up to decades of
GHz. It is mandatory that the RF models of the MOSFETs
cover scalability over channel length and width, bias and
temperature as in classical low-frequency design kits
but also for multi-finger layout transistors typically used in
RF design. The designers need accurate models that can
capture all geometrical and bias-dependent effects. The
models should offer high accuracy at all levels of inversion,
including moderate inversion where RF circuits often operate.
The EKV3 model is a MOSFET compact model. Its
physical foundation is based of the charge sheet approximation. The pinch-off voltage VP [1] is one of the important concepts of the model. VP is a function of the gate potential. The inversion charges at source and drain qs(d) are
functions of the difference VP - VS(D) [2]. The static and the
dynamic behaviour of the MOSFET, including noise, can
be described as a function of these inversion charges. Independently of the level of inversion, the same unified
equations are used, offering smooth and physical transitions among all levels of inversion and from linear operation to saturation.

2008 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim

Figure 2 DC analysis, ID and gm vs. VG, gm/ID vs. ID,

|VDS|={50m, 0.5, 1V}, ID and gds vs. VD [|VGS|={0.4, 0.6, 0.8, 1,
1.2V}], VSB =0V. (a) NMOS transistor, L=180nm, Wf=2m,
NF=4, (b) PMOS transistor, L=180nm, Wf=2m, NF=2. Measured
(markers) and simulated with EKV3 model (lines).

Figure 3 DC scaling plots of NMOS devices with gate length L

= 180 nm and finger width Wf = 2 m, vs. the number of fingers
NF. (a) Threshold voltage, corresponding to VGS for which IDS is
100 nA(W/L), at VSB = 0 V, where W = NF*Wf is the total width
of the device. (b) Drain current per finger determined as IDS/NF
for maximum VGS = 1.2 V. VDS takes the values 50 m (o), 0.5 ()
and 1 V () and VSB = 0 V. Markers stand for measurements
while lines for EKV3 simulations.

The EKV3 model is coded in Verilog-AMS [3] and

simulations are performed in ADS. The intrinsic model is
complemented by a fully scalable RF parasitic network for
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Figure 4 Y-parameters vs. frequency for an NMOS transistor

with L = 180 nm, Wf = 2 m, NF = 9. Measured (markers) and
simulated with EKV3 model (lines): VDS = 1 V; VGS = 0.3 (),
0.6 (o), 1.2 () V.

Figure 5 Y-parameters vs. frequency for a PMOS transistor with

L = 180 nm, Wf = 2 m, NF = 9. Measured (markers) and simulated with EKV3 model (lines): VDS = -1.2 V; VGS = -0.3 (),
-0.6 (o), -1.2 () V.

gate and substrate parasitics [4, 5]. A channel segmentation

technique ensures consistent handling of NQS modelling
[6] under small- and large-signal conditions.
Two typical RF devices are chosen to illustrate the
static capabilities of the model, one NMOS and one PMOS.
Their gate length is 180 nm and finger width is 2 m. The
NMOS has 4 fingers while the PMOS has 2 fingers. Figure
2 shows static characteristics drain current (ID), transconductance (gm) and output conductance (gds), as well as
transconductance-to-current ratio (gm/ID) of the two
devices. The EKV3 model shows excellent fits of all
the static characteristics. Other devices provide similar results.
Due to Shallow Trench Isolation (STI) stress effect,
threshold voltage and effective mobility depend on
the number of fingers of the RF transistors. EKV3
covers this effect employing a formulation similar to the

BSIM4 model [7], adapted to its own context. The results

in Figure 3 show that EKV3 offers a good description of
the dependence of electrical behaviour on the number of
fingers.
Figures 4 and 5 show measured and modelled Yparameters, as real and imaginary part, for a selected
NMOS and PMOS device. Bias conditions cover weak to
moderate and strong inversion while the devices are biased
in saturation. The real parts of Y21 and Y22 correspond to
gm and gds, respectively, at low frequency. The EKV3
model shows adequate fitting and scaling behaviour over
the whole bias and frequency ranges.
Some figures of merit of particular interest from the
designers point of view are the unity gain frequency fT,
obtained from H21, the unilateral gain U, and the maximum
oscillation frequency fmax obtained from U,

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Figure 6 H21, unilateral gain, fT, fmax, Re(Y21), Re(Y22) vs. ID,
evaluated at 5 GHz, of an NMOS (same as in Fig. 4). Markers
represent measurements (VDS = 0.5 (), 1.2 (o), 1.3 () V, with
VSB = 0 V) and lines the EKV3 model.

fT =

f
Im (Y11 Y21 )

U=

H 21 H12
,
4 (Re( H11 ) Re( H 22 ) + Im( H11 ) Im( H 22 ))

(1)
2

f max = U ( f ) f .

(2)
(3)

Figures 6 and 7 show these quantities, together with

Re(Y21) and Re(Y22) vs. ID, evaluated at 5 GHz, for the
same devices as in Figs. 4 and 5. The model provides good
qualitative and quantitative results. The analysis vs. ID is
especially useful for design optimization.
4 Conclusions The high-frequency capabilities of
modern Si RF CMOS technologies allow the designer to
implement low-voltage circuits operating at multi-GHz frequencies. Such technologies, though, need to be accompanied by accurate device compact models scalable over a
wide range of geometries and frequencies, and for biases
throughout all levels of inversion.
The present work showed a detailed study of the RF
behaviour of an 180 nm RF CMOS production process
technology. Static and high frequency behaviour of the
process was investigated for RF multi-finger devices of
both types, over an extended range of geometries and bias
conditions.

2008 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim

Figure 7 H21, unilateral gain, fT, fmax, Re(Y21), Re(Y22) vs. ID,
evaluated at 5 GHz, of a PMOS device (same as in Fig. 5). Markers represent measurements (VDS = -0.5 (), -1.2 (o), -1.3 () V,
with VSB = 0 V) and lines the EKV3 model.

The EKV3 MOSFET model is a full-featured, scalable

non-linear compact MOSFET model oriented to RF IC design, based on a clear physical basis. In this paper, the
model has been extensively validated. The model exhibits
excellent behaviour for frequencies up to 30 GHz, and over
a wide range of geometries and bias conditions.
Acknowledgement The authors A. Bazigos, M. Bucher, P.
Sakalas and M. Schroter are grateful to the German Ministry of
Research and Technology (BMFT) and Atmel Germany, Heilbronn, for financial support within the research project DETAILS
(HF design technology for precise analog IP-based front-end solutions in very-large-scale integrated data transmission systems).

References
[1] C. C. Enz and E. A. Vittoz, Charge-based MOS Transistor
Modeling (Wiley, 2006); ISBN 978-0-470-85541-6.
[2] M. Bucher, A. Bazigos, F. Krummenacher, J.-M. Sallese, and
C. Enz, EKV3.0: An Advanced Charge Based MOS Transistor Model, in: Transistor Level Modeling for Analog/RF IC
Design, edited by W. Grabinski, B. Nauwelaers, and D.
Schreurs, Chap. 3 (Springer, 2006), pp. 67-95.
[3] A. Bazigos, M. Bucher, and S. Yoshitomi, Benchmarking the
EKV3 MOSFET Model in Verilog-A and 0.14 m CMOS,
Proc. 11th Int. Conf. MIXDES, pp. 104-109, June 2004.
[4] S. Yoshitomi, A. Bazigos, and M. Bucher, EKV3 Parameter
Extraction and Characterization of 90 nm RF-CMOS, Proc.
14th Int. Conf. MIXDES, pp. 74-79, June 2007.

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[5] M. Bucher, A. Bazigos, S. Yoshitomi, and N. Itoh, Int. J. RF

Microw. Computer Aided Eng. 18(4), 314-325 (2008).
[6] M. Bucher and A. Bazigos, Solid-State Electron. 52(2), 275281 (2007), February 2008, doi:10.1016/j.sse.2007.08.015.
[7] M. V. Dunga, W. Yang, X. Xi, J. He, W. Liu, Kanyu, M. Cao,
X. Jin, J. J. Ou, M. Chan, A. M. Niknejad, and Ch. Hu, BSIM
4.6.1 MOSFET Model, Users Manual (UC Berkeley,
2007).

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