Explain various transistor switching times.

Ans.1. The time interval between the instant of application input pulse and output (collector)
currant to attain 10 percent of its maximum value is termed as the delay time td .
2. Rise time tr, is defined as the time required for the output currant Ic to go from 10% to 90% of
its maximum value.
3. The sum of delay time td, and rise time tr, is called the turn-ON time ton,
i.e.
4. TURN- OFF time is made up of a storage time ts, and a fall time tf
i.e.
5. Storage time ts, is defined as the time interval between the end of the input pulse (trailing
edge) and when the collector current falls to 90% of its maximum value.
OR
Storage time, is equal to the sum of time taken in removing excess charge stored and the time
taken by collector transition capacitance to discharge to 90% of its maximum but major portion
of the time is taken in removing excess charge storage.
The time duration of the output pulse measured between two 50% levels of rising and falling
waveform is known as the pulse width.
For a fast-switching transistor, turn-on time and turn-off time must be of the order of nano
seconds.

How is a transistor used as a switch.

Ans. A transistor can be employed as an electronic switch. Operating a transistor as a switch
means it at either saturation or cut-off nowhere else along the load line. When a transistor is
saturated it is like a closed switch from collector to emitter. When a transistor is cut off it is like
an open switch.

SWITCHING TIMES OF A TRANSISTOR

Instead of a step, if a pulse is applied to the transistor switch, how does the device respond? To
understand this, we consider the switching times of a transistor (see Fig. 6.24).
Let the input to the transistor switch be a pulse of duration T. When a pulse is applied, because of
stray capacitances, collector current will not reach the steady-state value instantaneously. To
know exactly when the device switches into the ON state and also into the OFF state, we define
the following switching times of the transistor.

The Turn-on Time of a Transistor

Turn-on time of the transistor is the time taken by the transistor from the instant the pulse is
applied to the instant the transistor switches into the ON state and is the sum of the delay time
and rise time. To find out the turn-on time of the transistor, the delay time and rise time have to
be calculated.
Delay Time (td). It is the time taken for the collector current to reach from its initial value to 10
per cent of its final value.
If the rise of the collector current is linear, the time required to rise to 10 per cent IC(sat) is 1/8
the time required for the current to rise from 10 per cent to 90 per cent IC(sat).

It is given as:
where, tr is the rise time.
Rise Time. Rise time, tr is the time taken for the collector current to reach from 10 per cent of its
final value to 90 per cent of its final value. From Fig. 6.24 it is seen that the moment input pulse
is zero, the collector current is expected to fall to zero. However, because of the stored charges,
the current remains unaltered for sometime interval ts1 and then begin to fall. The time taken for
this current to fall from its initial value at ts1 to 90 per cent of its initial value is ts2. The sum of
these ts1 and ts2 is approximately ts1 = ts and is called the storage time.
BREAKDOWN VOLTAGES
We have seen that by the application of a signal of proper polarity and magnitude, a transistor
switch can be driven into saturation. As a result, the voltage at the collector of the device
isVCE(sat) (typically 0.1 V for Ge and 0.2 V for Si). Now, when a signal of opposite polarity is
applied as input to the switch, ideally the voltage at the collector rises to VCC. Thus, we see that
the change in voltage at the collector is VCC VCE(sat) VCC. This output is connected to
operate some other circuits. For proper operation, it is desirable that VCC be made reasonably
large. However, by increasing the value of VCC, the reverse-bias voltage on the collector base
diode could become so large that an avalanche breakdown may occur in the collector diode. The
leakage current ICO will then become MnICO where, Mn is the avalanche multiplication factor.
Mn depends on VCB. An empirical relation for Mn, applicable for many transistor types is given
as:

Here, VCBO(max) is a maximum reverse-bias voltage that can be applied between the collector
and base terminals of the transistor when the emitter lead is open-circuited and n is typically in
the range of 2 to 10 which controls the sharpness of onset of a breakdown. Calculation of Mnis
illustrated in the Example 6.12.
The Breakdown Voltage with Base Not Open Circuited
Consider the figure shown in Fig. 6.31. VCEO(max) is the breakdown voltage between the
collector and emitter terminals with the base lead open. Now, if the base lead is not open
circuited, but a resistance RB is connected between the base and emitter terminals, the new
breakdown voltage may be termed as VCER(max). The expectation is that VCER(max) lies
somewhere between VCEO(max) and VCBO(max). Let us try to calculate the value of
VCER(max).

It is known that unless a voltage of V exists between base and emitter terminals, the diode
forward current is small and the collector to base leakage current will now flow through RB.
Once the forward-bias voltage of the base emitter diode is more than V, a large current flows
through the collector and the corresponding breakdown voltage is VCEO(max). Breakdown
occurs when VCE is greater than VCEO(max). When the threshold voltage V is reached, at that
instant the collector current is MnICO. Thus, at breakdown the current through RB is MnICO.

FIGURE 6.34 ICvs. VCE extended into breakdown region for different conditions
1. When the base is open circuited (IC = ICEO)
2. When RB is connected between the base and emitter
3. When RB is connected with a reverse-bias voltage VBB.

From Fig. 6.34, it is apparent that breakdown occurs at VCEO(max) with base lead open at the
point, the current rises abruptly. VCEO(max) is called the sustaining voltage. When RB is
connected between the base and emitter, the breakdown occurs at a larger voltage VCER(max).
After breakdown the voltage returns to the sustaining voltage. If RB = 0, breakdown occurs at a
slightly larger voltage. Further, we also see from the characteristics that if the emitter diode is
reverse-biased, the breakdown occurs at a still larger voltage. The larger is the reverse-bias
voltage, the larger is the breakdown voltage. These characteristics explain the possible
breakdown voltages for different conditions on the emitter diode, so that at these prohibited
voltages the transistor is not operated. The currents for all the possible connections (except for
ICEO) give two values for the same voltage. Also, once the breakdown occurs current in the
transistor increases with decreasing voltage, which means that the transistor exhibits negative
resistance characteristic. The transistor when used in the breakdown region is called an
avalanche transistor.
From Eq. (6.59) we see that VCEO(max) is dependent on hFE which in turn depends on the
collector current IC. DC current gain is the ratio of IC/IB at an operating point and is designated
as hFE or dc.
The parameter hFE is useful in determining whether a transistor is in saturation or not and it
varies with collector current IC (see Fig. 6.30). Typically hFE varies as shown in Fig. 6.35 which
is called current gain characteristic.
THE SATURATION PARAMETERS OF A TRANSISTOR AND THEIR VARIATION
WITH TEMPERATURE
The output characteristics of npn transistor having PT = 250 mW at room temperature in the
CE configuration are given in Fig. 6.36. The dc load line for RL = 400 is superimposed on the
characteristics. However, from the characteristics in Fig. 6.36 the saturation voltageVCE(sat) can
not be found as its value is typically a fraction of a volt (0.1 V for Ge and 0.2 V for Si). A
transistor is said to be in saturation when the emitter and collector diodes are forward-biased.
RL = 400 , VCC = 10 V
To draw the dc load line:

VCE(cut-off) = VCC = 10 V
To be able to read VCE(sat), the characteristics in the voltage range 0 to 0.5 V are expanded and
the dc load line for RL = 400 is again superimposed, as shown in Fig. 6.37(a). The region [see
Fig. 6.37(b)] around IB = 0.175 mA is expanded to see the variation in IC for larger values of IB
as shown as the dotted region in Fig. 6.37(a). It is seen for IB > 0.175 mA, that there is no
appreciable change in the collector current for a change in the base current as shown in Fig.
6.37(b), which indicates that the transistor is driven into saturation. Again from these
characteristics we see that for IB = 0.175 mA, VCE(sat) = 250 mV and for IB = 0.35 mA,
VCE(sat)= 125 mV. This variation explains that, the larger is the value of IB, the smaller is the
value ofVCE(sat). At a given operating point, the ratio of VCE(sat)/IC is called the saturation
resistanceRCS. RCS at the point Q is

FIGURE 6.36 Typical output characteristics of an npn transistor in the CE mode