UNIT III SYNCHRONOUS SEQUENTIAL CIRCUITS

SR, JK, T AND D FLIP-FLOPS

1. Show how the JK flip flop can be modified into a D flip flop or a T flip flop.(N/D
2014)
D is the external input and J and K are the actual inputs of the flip flop. D and Qp make
four combinations. J and K are expressed in terms of D and Qp. The four combination
conversion table, the K-maps for J and K in terms of D and Qp, and the logic diagram
showing the conversion from JK to D are given below.

2. Convert T flip flop to D flip flop.(A/M 2015)

3. Draw the truth table and state diagram of SR flip-flop. (N/D 2015)
State diagram

Truth table

4. Give the characteristic equation and characteristic table of SR flip-flop.(A/M 2016)

5. Write down the characteristic equation for JK flip-flop. (Dec09,Dec10,May11)

Characteristic equation for JK flip-flop is Qt+1 = J Q+ K Q
6. How do you eliminate the race around condition in a JK flip-flop.
(Dec 2010)
Race around condition in a JK flip-flop can be eliminated using master-slave
configuration. A master-slave flip-flop consists of two flip-flops where one circuit serves as a
master and other as a slave. The output of the master is fed as an input to the slave.

7. Realize JK flip flop using D flip flop.

(Dec 2011)

In this conversion, D is the actual input to the flip flop and J and K are the external inputs. J, K
and Qp make eight possible combinations, as shown in the conversion table below. D is
expressed in terms of J, K and Qp.
The conversion table, the K-map for D in terms of J, K and Qp and the logic diagram showing
the conversion from D to JK are given in the figure below.

8. Realise T-FF from JK-FF.

9. Draw the state table and excitation table of T flip-flop.

(Dec 2010)

10. How a D flipflop is converted into T flip-flop./ Convert D flip to T flip-flop.

(Dec 2012, May 2013)

11. How many flipflops are required to build a binary counter that counts from 0 to 1023.
(May 2013)
Number of flip-flops is given as 2n count +1, where n is the number of flipflops.
Therefore, 2n 1023 +1 , i.e., 2n 1024. It implies , n = 10
Hence, 10 flip-flops are required to build a binary counter that counts form 0 to 1023.
12. Define : Latches.
(Nov 2013)
The flip-flops that operate with signal levels are referred as latches. Latch is a memory cell
which is capable of storing one bit of information , ie. Logic 1 or logic 0. Latches are
controlled by enable signals and they are level sensitive devices. Latches are basic building
blocks of flip-flops.
13. Sketch the logic diagram of a clocked SR flip flop.

(May 2014)

14. Draw the master-slave JK flip-flop.

LEVEL TRIGGERING AND EDGE TRIGGERING

15. What are edge triggered flip flops? (N/D 2015)
Flip-flop changes its state either at positive edge or negative edge of the clock pulse and
is sensitive to its inputs only at this transition of the clock. These type of flipflops are
referred to as edge triggered flip flops.
16. What are level triggering flip flops?

17. Mention any two differences between the edge triggering and level triggering.
(May2010,May2012)
Edge Triggering
Level Triggering
Flip-flop changes its state either at positive When the clock pulse goes high the flip-flop is
edge or negative edge of the clock pulse and is said to be level triggered flip-flop.

sensitive to its inputs only at this transition of When flip-flop, changes its state by applying
the clock.

positive clock- positive level triggering.

When flip-flop, changes its state by applying
negative clock negative level triggering.

COUNTERS
18. What is meant by programmable counter? Mention its application.
A counter that divides an input frequency by a number which can be programmed is called
programmable counter. Applications: Frequency division, digital clock, stop watch and
programmable logic controller.
2. Compare the logics of synchronous counter and ripple counter.
Synchronous counter
Ripple ( Asynchronous counter)
In Synchronous counter, no connection exists Here flip-flops are connected in such a way
between output of first flip-flop and clock that output of first flip-flop drives the clock
input of next flip-flop.
If the "clock" pulses are applied to all the

for the next flip-flop.

All flip-flops are not clocked simultaneously.

flip-flops in a counter simultaneously,

then

such

counter

is

called

as

synchronous counter.

Circuit is simple.
High speed counters.
3. What is a ripple counter?

Circuit is complex.
Low speed is the drawback.

A ripple counter is a cascaded arrangement of flip-flops where the output of one flip-flop
drives the clock input of the following flip-flop. A ripple counter is also called as asynchronous
counter or a serial counter, as the clock input is applied only to the first flip-flop, also called the
input flip-flop in the cascaded arrangement.
4. Explain Modulo N counter (MOD-N counter).
In general, an n-bit ripple counter is called as modulo-N counter. Where, MOD number = 2 n. For
example, the 2-bit ripple counter is called as MOD-4 counter and 3-bit ripple counter is called as
MOD-8 counter.
Type of modulus

2-bit up or down (MOD-4)

3-bit up or down (MOD-8)

4-bit up or down (MOD-16)

5. Mention few applications of counters

Frequency counters , Digital clock ,Time measurement, A to D converter and Frequency divider
circuits are few applications of counters.
SHIFT REGISTERS
19. What is a shift register?
A register capable of shifting its binary information in one or both directions is called a
shift register.
20. Mention the types of shift register?
(i)
SISO Serial in Serial Out
(ii)
SIPO - Serial in Parallel Out
(iii)
PISO- Parallel in Serial Out
(iv)
PIPO Parallel in Parallel Out
(v)
Bidirectional shift register
MOORE AND MEALY MODELS
21. State the differences between Mealy and Moore state machines. (N/D 2014 & A/M
2016)
Moore Machine
Its output is a function of present state only.

Mealy Machine
Its output is a function of present state as well
as present input.
Input changes does not affect the output.
Input changes may affect the output of the
circuit.
It requires more number of states for It requires less number of states for
implementing the same function.
implementing the same function.
STATE DIAGRAM -STATE REDUCTION AND STATE ASSIGNMENT
22. State the rules for state assignment. .(A/M 2015)
Assignment of values to state variables is called state assignment. A binary value is assigned to
each of the states
23. What is state reduction?
The reduction of number of states in a state table is called as state reduction .By state
reduction the number of flip-flops in a sequential circuit is reduced.
24. What is a state diagram?
25.