FPGA Implementation of Digital Upconversion using Distributed Arithmetic FIR

Filters
T. Salim, J. Devlin, J. Whittington
Department of Electronic Engineering
La Trobe University Bundoora, VIC 3086 Australia
{ t.gillj.devlinj .whittington}@latrobe.edu.au
2 Direct Conversion Transmission Method

Abstract
Distributed Arithnietic (DA) is a high speed
multiplication technique wed for iniplenzentation of digital
filters and signal upconversions. The DA is bit serial word
parallel approach where throughput rate does not depend
on f l t e r length or data s t e . In this paper a serial DA
method is employed for FPGA implenientation of digital
coniponent of the TIGER transmitter. A prototype has been
Jynthested and mapped using Xilinx Virtex II. The design
with fourteen bit 100 tap FIRfirter and upsanipling ratio
of eight takes only 18% of the device. Performance of the
DA modulator is discussed with variable filter length and
precision level.

In the literature different methods are described for

direct conversion RF modulation. Most of these techniques
use some type of sine or cosine multiplication that
involves power sensitive signal processing function; power
consumption of such systems is considerably higher since
multiplication is performed at high frequencies. Using
multirate digital techniques this can be implemented as a
simple logic [l].
In this section we present an equivalent method of
generating digital signals for existing analog TIGER
transmitter system. We propose digital equivalent of only
beam generation system of the transmitter while power
amplifier and other associated analog circuitry remain the
same. The block diagram of the proposed method is shown
in Figure 1. The input Gaussian pulse is resampled at
higher clock rate and a high pass FIR filter is applied to
acquire the required spectral zone. The time delay is
introduced to steer the beam at a set azimuth angle. This
digital signal is converted to the analog domain using a
suitable DAC and a suitable analog reconstruction filter
(ARF). 7he output of ARF is sent to the existing power
amplifier through a transmitterireceiver switch.

Keywords
Field Programmable Gate Array (FPGA), Tasman
International Geospace Environment Radar (TIGER),
Distributed Arithmetic (DA).

1 Introduction
SuperDARN (Super Dual Auroral Radar Network) is an
international radar network, which evaluates the space
weather system. Tasman International Geospace
Environment Radar (TIGER) is one component of the
SuperDARN network that analyzes the space weather in
southem hemisphere. The existing radar architecture is
based on analog components with limitations of analog
imperfections. Currently we are investigating efficient
ways to implement this radar in FPGA technology to
introduce more flexibility and reconfigureability.
In this paper we present a serial DA algorithm to realize
digital counterpart of the current analog transmitter
system. In section 2, a direct conversion method is
described using FIR filtering. DA is a bit serial word
parallel approach for calculating dot product of filter and
data. A mathematical description of the DA is given in
section 3 with an example. A low scaled version of the
direct conversion transmission system is initially
implemented employing 8011s pulse duration. The
precision level of the system is fourteen hits since Digital
to Analog Converter (DAC) in the proposed system holds
the same size. Output pulse duration and spectrum of the
prototype system are described in section 4. Performance
of the modulator is discussed in section 5 with variable
length filter order and precision level. In the last section
conclusions are dram.

0-7803-8652-3/04/$20.00 0 2004 IEEE

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Figure 1 Block diagram of direct conversion

transmitter section.
The frequency range of input pulses varies between
200KHz to 500KHz and this 'baseband' signal is shifted to
bandwidth of 8MHz to 20MHz by the upsampling process.
The upsampling process introduces L - 1 spectral copies
in the signal spectrum when the signal is upsampled by a
factor of L . FIR filtering is used to select desired spectral
copy and suppress other images.
Simulations have been carried out to generate
modulated Gaussian pulses at HF frequencies between
8MHz and 20MHz. The baseband pulses are selected at
frequency range of SOOKHz, the frequency spectrum of the

335

ICFPT 2004

such a way that the arithmetic becomes distributed

throughout the structure [3].

generated Gaussian envelope is shown in Figure 2 (a). The

baseband signal is upsampled with a sampling frequency
of 20MHz and Nyquist frequency of 1OMHz. This signal
is filtered by a 200 tap high pass FIR filter with a cutoff
frequency of IOMHz. The FIR filter was designed using a
Kaiser-Bessel window. The modulated envelope and its
spectrum are displayed in Figure 3. The modulated pulse
duration is 300usec which is used for 45km range
resolution in the TIGER radar. The filtered spectral copy
exhibits more than 1 lOdB of dynamic range as shown in
Figure 3 (b). All signal components in these simulations
were represented with floating point numbers.

Figure 3 Output modulated pulse (a) in the time

domain (b) spectral copy
By way of explanations, we start from the sum of
products for a filter equation as follows [4]
.
bgusnry

I"

.
Hmz

x 10=

where hk are filter coefficients and xi are input data

words. The input data words can be represented in
fractional form provided
<1

Figure 2 Spectrum of (a) Gaussian pulse (b)

upsampled Gaussian pulse

Ix~I

The modulated Gaussian pulse can be generated with

different carrier frequency other than mentioned in the
above example. This can be achieved with changing
sampling rate and filter coefficients accordingly [2].

N-l

x, = -4, +

bh 2-n
"=I

where bh are bit 0 or 1, b,, is a sign bit, bk.N-Iis the

LSB and N represents number of bits in a digit. By

combining the above two equations we get

3 Serial DA Algorithm
Serial Distributed Arithmetic (SDA) is a high speed
multiplication technique based on serial processing at bit
level. Its high computation rate is helpful for calculating
sum of products or vector dot products for filtering
operations [2]. Unlike word serial bit parallel method, the
SDA is a bit serial word parallel (BSWP) method. The
output sample is available after its pipelined bits are
processed. This can also be represented as a vector
multiplication where each word is converted into an
equivalent number of bits and the bits are reordered in

(3)

The equation shows that the block ofdata bits bas a dot
product relationship with kilter coefficients. The above
equation can also be written as

By expanding the above equation we can arrive at

316

y = [bboh,+ b,,h,

The spectrum of the quantized Gaussian pulse shows

difference in dynamic range that is proportional to number
of bits. Since each bit in the precision is responsible for
about 6dB gain, therefore the dynamic range of the
quantized spectrum obeys that rule. providing
approximately 90dB resolution as shown in Figure 5 (b). A
similar effect can he seen in the filter response.

+ b,,h, + ..........b,,h,]

+[b& +b,,h, +b,,h, + ..........b,,h,h-'

+[b,,h,+b,h,+b,,h,+ ..........b,,h,]2-'

+ [b,,,.,lh,

+bii,v-lih2
+b,,,.,+, +-..-.......6i,N-Il
hI p

(5)
Equation ( 5 ) exhibits AND operation of each data bit
with the coefficient bits. The hoe,represents MSB of filter
coefficient h,and xObo represents MSB of the data
sample xo . The dot product is shown only for the fnst filter
sample with the data window. If there are M numbers of
samples in the filter window and in the data window then
total number of multiplications is M' . The total number
of additions example can be represented as M ( M - I).
In the next section we discuss FPGA implementation of
a 14 bit direct conversion modulator.

os

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bW.rr" I" Hsnr

3 5

1.5

ro'

4 Implementation of 14 bit DA FIR Modulator

The precision level for a prototype is chosen to be 14
bits, since size of the DAC is fourteen bits. A second
reason for this selection is dynamic range of the signal. For
this level of precision approximately 90dB gain can be
achieved. A combination of Visual HDL and Xilinx XST
VHDL is used to derive a digital Gaussian modulated
signal. The prototype was implemented using Xilinx
V i e x I1 device, starting from fifty samples of a Gaussian
pulse as shown in Figure 4. These samples are fixed point
number constrained to 14 bit.

0 5

1 5

2.5

*W"B"SY

I"

I
Hsnl

31

4 5

5
x 10.

Figure 5 Spectrum of (a) unquantized and (b)

quantized Gaussian pulse.
The quantized Gaussian pulse is oversampled eight
times and DA FIR filtering is performed with cut-off
frequency of 400KHzl filter length is 100 taps. When the
quantized filter response is multiplied with the upsampled
spectrum of the Gaussian pulse we get the output envelope
shown in Figure 6. The output envelope can he used for
80usec range radar transmission, which is modulated to
track 15 Km range ofthe ionosphere.

>

>
5
2
0
*
"e<numberd *ampler,

Figure 4 Time domain quantized and unquantized

samples.

337

The multirate upconverter with the 100 taps FIR filter

and upsampling of eight has been implemented on Virtex
II, the implementation takes 18 % device space with
approximately 7Msamples per second throughput when
input clock is 100MHz. This means a full strength
transmitter system can be implemented on the target
device.

SDA keeps the filter throughput at the same level

depending upon the word size. For larger word size the
inner product takes longer clock cycles to process each
sample. The result is shown in Figure 8 with input clock
speed of 100MHz.

Time (j

140E.07
g 120E.07
1.00E-07
2 8.WEt06
6.WEt06
4.WEt06
2WE+06
0 WEtOO

s-s,

/--

_..-.I_
.
. .

.
..... . ...

F,lferea r m y at OOKHI

-10
-20

12

14

16

24

32

word size

-30

4n

-60

Figure 8 Throughput rate for serial DA FIR

modulator

-70

A potential advantage of reconfigurable computing is

change in the function of the design with a s o h e flick.
For example a variable filter order can be synthesized with
a desirable precision level using a s o h a r e control.

40
Bo
-MO

0.5

1.5

2.5

rnvlvensy In Hen=

3.5

lo

Figure 6 (a) Modulated pulse, (b) spectral copy at

400KHZ.

6 Conclusions
In this paper we have presented a reconfigurahle direct
conversion modulator using serial DA. A prototype design
has been mapped employing Visual HDL and Xilinx tools.
For a fmed precision level of fourteen bits. output sample
rate of almost 7Msamples is available. Implementation
cost has been shown using device occupation. For a 100
tap FIR modulator employing eight time upsampling the
device occupation is just 18%. This result shows a full
strength system can be mapped on a single device using
DA technique.

5 Performance with Variable Word size and

Filter order
Device utilization is performance measure for any
FPGA design. Unlike the serial arithmetic design, SDA
throughput is kept at constant level even with a larger filter
order. However higher filter order requires larger device
occupation. In the last section multirate design is presented
with 14 hit precision and oversampling ratio of eighf the
device utilization was 955 slices. A similar design is
implemented with different upsampling ratio and results
are shown in Figure 7. Implementation results show
increase in the device area with increasing the filter order
and upsampling ratio.

...

7 References
[I] T. Salim, J. Devlin. .I.
Whittington, Investigation of
multirate techniques for digital generation of Transmitter
signals for TIGER Radar, IEEE INMIC Conference,
Lahore Pakistan, December 2001.
[2] The Role of Distributed Arithmetic in FPGA Based
Signal Processing. Xilinx Publications.
[3] K. K. Parhi. YLSI Digirar Signal Processing Svsrenrs:
Design and Inrpienrentation, Published by John Wily &
Sons 1999.
[4] S. A. White. Applications of Distributed Arithmetic to
Digital Signal Processing: A Tutorial Review, IEEE ASSP
Magazine, July 1989.

Sampllng rate

Figure 7 Device utilization for 50 tap and 100 tap

DA FIR modulator.

338