Computer Architecture 2 Exam

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1.
a) Explain how parameters and results are passed between
C++ and Assembly language subroutines.
The C++ program puts the parameters on the stack, and the assembly
subroutine gets them through the register that has the address of the
top of the stack.
The return value, when its 32-bit long, its returned through the EAX
register. When its 64-bit long, its return through both EAX and EDX
registers.
b) Explain the terms base class and derived class as used in the
C++programming language and hence give reasons for their
popularity.
Assuming that theres a class in the program which describes a person,
and at some point, a student must be represented. So, in that case,
person will be a base class for the creation of the derived class
student. Instead of creating a whole new class to student, its just
needed to create it like a derivation of a person, in which itll be added
the new features (like a student id or grades), but the student class
will have every characteristic that the person class has. This is so
popular because it brings optimisation to the code and its possible to
make comparisons and attributions between the two classes.
c) Give a reason for the use of virtual functions in C++. Hence
explain the term abstract base class and why it is such a useful
concept.
Virtual functions: When having a lot of classes in a program, specially
when theres inheritance involved, it is possible to have two different
classes with same method names. The problem is when one class is
derived from another and the implementation of this methods differs
between the two classes. In that case, the compiler normally decides
which function to call during compiling time, and it calls for the base
class function. But the programmer (and/or the user) usually wants to
have the derived class method. To solve this, its necessary to
postpone the decision of which method will be called until running

time, and that way, the program will correctly associate the type of the
variable with its class and call the correct method.
Base class: Abstract base classes happen when the base class dont
need to be represented itself in the main program. The programmer
needs to create a lot of objects of different classes, but they are all
similar. In that case, a base class is created, from which a lot of
derived classes will be created. But when the base class wont be used
to create an object in the program, its an abstract base class.
2.
a) In the context of the interface between DRAM memory chips
and the CPU, give reasons for use of the following:
(i) refresh counter (ii) address multiplexer
Refresh counter: Dynamic RAM uses every single bit as storage. After
all of its bits are filled, they need to be refreshed to make sure that
that information remains correct, hence its capacitors loose charge
with the time, but all the bits are in used. The refresh counter is to
know which row of bits is going to be refreshed at that time.
Address Multiplexer: In the memory, theres lines and columns,
resulting in 2 different addresses. So, a multiplexer is used to control
which one is being passed.
b) Comment on the connection between DRAM access time and
the use of cache memory in a computer system.
The DRAM access time is big, so it cant be used for the CPU to
continuous access. Although, a small amount of cache memory used is
enough to supply the big majority of CPU memory access.
c) Why is Dynamic RAM used as main memory in a computer
system rather than Static RAM? Draw a block diagram that
shows how a CPU would be interconnected with a DRAM based
memory system.
DRAM holds more memory for area than SRAM, and thats why its
used as main memory. SRAM is faster, so its used in the cache.

d) Explain the difference between daisy chained interrupts and

IPMC interrupts.
In the daisy chained interrupts, the next interrupt in order of priority is
going to be serviced after the CLI instruction, even if the next ISR is
from a lower priority than the current one.
In the IPMC interrupts, the next interrupt in order of priority is going to
be serviced after the CLI instruction ONLY if its from a higher priority
than the current ISR. Otherwise, its serviced only after the current
ISR clears its bit in the IMPC register.
3.
a) What design techniques are used to allow the PCI-Express
bus to achieve much higher speeds than traditional parallel
buses. Hence explain why 128b/130b encoding is used.
Traditional parallel buses are compound by a lot of wires put side by
side, and when the clock is big, the data suffers from problems with
interference, due to magnetic fields that interfere. The PCI Express
was designed to work with a 5GHz frequency, and has a mechanism
through which it can send and receive information at the same time,
with a double lane of links with devices. These lanes give the PCIe
scalability, once they can be added up to it, increasing the speed of
data transmission.
The 128b/130b encoding is used because of the lack of conditions in
generating a clock on a bus with high frequency. The frequency is
encoded in the data, and the receiving device can generate a clock
similar to the hypothetical transmitted one.
b) Explain the purpose of each of the following logical layers
used in the PCI-Express:
(i) Transaction Layer
(ii) Data Link Layer
(iii) Physical Layer
Hence identify how bus arbitration is handled.
Transaction Layer: The PCIe uses a special packet to make requests
and to complete data into other PCIe devices. The transaction layer
deals with these requests, besides doing power management.

Data Link Layer: Its an intermediate layer between the other two and
deals with error detection and correction.
Physical Layer: Its literally the physical components of the PCIe, e.g.
its pins.
c) The PCI-Express 3.0 standard is capable of an interconnect
bit-rate for a single lane of 8 GT/s (Giga Transfers per second)
in each direction. Calculate if it possible to achieve a usable
bidirectional transfer rate of 15GBytes/sec using 16 PCIExpress lanes.
Starting with:
1 lane has two directions, so 16GB/s. But for each 128 bits, it actually
has to send 130 bits. So, (128/130)*16 = 15,7 GB/s.
This is just for one lane. For 16 lanes: 252 GB/s.
Divided by 8, it returns 31.4 GB/s bi-directional data transfer, which
means that is possible to have 15GB/s using PCIe x16.
d) The block diagram in Figure 1 below shows a scenario where
2 CPUs each have local private buses with local memory and
local I/O. They also share a block of global memory which they
can use to pass data to each other. Describe the sequence of
events when CPU 1 begins execution of the instruction that
attempts to load the byte contents of location hex C0000000
into one of its internal registers

Address C000000 out on the address bus. Address valid to ready

timer.
Q12 of address decoder active.
BUSRQ0 active to bus arbiter.
BUSGT0 active from the arbiter and ready timer triggered.
Global address buffer and data transceivers enabled.
Connects CPU1 local address and data buses onto the global system
bus.
Global memory returns data.
Ready timer output active to memory ready i/p of CPU1.
CPU1 reads the databus.

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