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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

Ultralow-Voltage High-Speed Flash ADC Design


Strategy Based on FoM-Delay Product
James Lin, Student Member, IEEE, Ibuki Mano, Masaya Miyahara, Member, IEEE,
and Akira Matsuzawa, Fellow, IEEE

Abstract This paper discusses the ultralow-voltage (ULV)


design strategy for high-speed flash analog-to-digital converters
(ADCs). A lower supply voltage decreases the energy consumption at the cost of conversion speed. In this paper, a new index,
the figure-of-merit (FoM)-delay (FD) product, is introduced to
provide a balance between the energy efficiency and conversion
speed. As a prototype, a 0.5 V, 420-MS/s, and 7-bit, flash ADC is
developed using a 90-nm CMOS technology to demonstrate the
validity of ULV operation. To overcome the challenges associated
with a reduced supply voltage, a double-tail latched comparator
with a variable capacitance calibration technique using metal
oxidemetal capacitors is implemented. An all-digital timedomain delay interpolation technique further enhances the resolution with very little additional power consumption. Using twoway time-interleaving, the prototype ADC achieves an effective
number of bits (ENOB) of 5.5 bits while operating at 420 MS/s
consuming a total power of 4.1 mW. The lowest measured
FoM is the 195 fJ/conv.-step during single-channel operation
at 210 MS/s, which results in an extremely low FD product of
0.93 pJ ns/conv.-step.
Index Terms Analog-to-digital converter (ADC), delay
interpolation, figure-of-merit (FoM)-delay (FD) product, flash,
high speed, ultralow voltage (ULV).

I. I NTRODUCTION

IGH-SPEED, low-resolution analog-to-digital converters


(ADCs) are required for many applications, such as
disk drive front-ends, high-speed backplanes, ultrawideband
receivers, and millimeter-wave receivers [1], [2]. The ultralowpower characteristic is also very desirable for portable applications, ubiquitous wireless sensor networks [3], [4], and
wireless medical sensors [5]. In addition, such low-resolution,
low-latency ADCs are crucial building blocks for the development of higher resolution ADCs such as deltasigma ADCs,
subranging ADCs, and pipeline ADCs.
Conventionally, the highly digital flash architecture is the
most suitable candidate for high-speed applications because
Manuscript received July 1, 2013; revised January 31, 2014; accepted
June 26, 2014. This work was supported in part by the New Energy and
Industrial Technology Development Organization; in part by the Ministry
of Internal Affairs and Communications; in part by the Core Research for
Evolutionary Science and Technology in Japan Science and Technology
Agency; in part by the Semiconductor Technology Academic Research Center,
Tokyo, Japan; in part by Huawei; in part by Berkeley Design Automation for
the use of the Analog FastSPICE Platform, Berkeley, CA, USA; and in part
by VLSI Design and Education Center in collaboration with Cadence Design
Systems, Inc., Yokohama, Japan.
The authors are with the Department of Physical Electronics, Tokyo
Institute of Technology, Tokyo 152-8552, Japan (e-mail: james@
ssc.pe.titech.ac.jp; mano@ssc.pe.titech.ac.jp; masaya@ssc.pe.titech.ac.jp;
matsu@ssc.pe.titech.ac.jp).
Digital Object Identifier 10.1109/TVLSI.2014.2340995

of its low latency. Due to its similarities to digital circuits,


supply voltage lowering is an effective method in reducing
its power consumption [6]. Moreover, as CMOS feature size
decreases, the supply voltage will decease [7] causing the
conventional analog circuit techniques to lose its validity.
Therefore, the efforts to realize ultralow-voltage (ULV) analog
circuits [8], [9] and data converters [10], [11] will become very
important with further technology scaling.
For analog circuits, there are many challenges to overcome
to realize ULV operation, such as the reduced signal-to-noise
ratio, the reduced voltage headroom, and the increased effects
of transistor variations at low voltages. Several solutions
have been reported such as body-driven circuits [8], [11],
subthreshold operation [12], successive-approximationregister-based operation [13], [14], and comparator-based
switched-capacitor amplifiers [15], [16]. Although these
examples have been very successful and demonstrated very
good performance in ULV, they all suffer in speed.
As mentioned above, most ULV analog circuit techniques
gain energy efficiency while severely sacrificing the operating
speed. For high-speed applications, this is a serious drawback.
Unfortunately, this issue is not reflected in the conventional
figure of merit (FoM) as it focuses on energy efficiency [17].
As a result, a new index, the FoM-delay (FD) product, is
introduced for ULV ADCs to clearly illustrate the tradeoff
between the energy efficiency and the conversion speed [18].
The key advantage of the FD product is that it takes the
conversion speed into consideration acting as a clear indicator
when the speed is significantly compromised.
Another key challenge of the flash architecture is its large
power consumption. This is especially obvious when the resolution requirement increases; conventional flash ADCs suffer
exponentially in its power consumption, input capacitance, and
chip area with increasing resolution.
To address the issues associated with the increase of resolution in a flash ADC, [19] simplified its first stage latches
to lower its input capacitance to half by using a time-domain
latch interpolation technique. However, the implementation of
this technique introduced two additional stages of comparators
limiting its power saving potential. To alleviate the power
consumption from the added comparators, [20] and [21] implemented an all-digital solution. This virtually halves the power
consumption, input capacitance, and chip area compared with
the conventional design.
In this paper, the research topic of ULV high-speed design
for flash ADCs is explored [18], [21]. In Section II, the concept

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Focusing on the flash architecture, the key contributor to


the peripheral circuits energy consumption is the digital
circuits. By reducing the supply voltage, digital circuits
energy consumption is reduced by a square term. As a result,
ULV operation is very effective in suppressing the energy
consumption of the peripheral circuits in a flash ADC.
B. FoM-Delay Product

Fig. 1.

Energy consumption of recent published ADCs versus resolution.

of the FD product proposed in [18] is further elaborated


to include second-order effects; thus, this paper provides a
more comprehensive explanation of the FD product. This new
index forms the basis of the ULV design strategy for highspeed flash ADCs. In Section III, we discuss the FD-oriented
design and implementation of a prototype flash ADC with
a detailed comparative analysis of mismatch compensation
techniques for ULV circuits. In Section IV, the experimental results are reviewed showing the advantages of the FD
design strategy. Finally, the conclusion of this paper is drawn
in Section V.
II. U LTRALOW-VOLTAGE S TRATEGY
A. Energy Consumption of an ADC
A sampling circuit is an essential part of an ADC. Moreover,
it also determines the fundamental energy consumption for a
given resolution as expressed below [22]
E s = 24kT 22N

(1)

where E s is the sampling energy limited by the thermal noise,


k is the Boltzmann constant, T is the ambient temperature,
and N is the resolution.
In addition to the sampling energy, the comparison process
required to complete the data conversion further increases the
energy consumption [23]. If the capacitance required for each
comparison is assumed to be the same as the sampling capacitance and the number of comparison is N, then the energy
consumption of an ADC, E ADC , becomes the following:
E ADC N E s .

(2)

Fig. 1 plots the recently published ADCs energy consumption against their resolution [24]. Equations (1) and (2) are also
shown in Fig. 1. Fig. 1 shows that the energy consumption
of current ADCs with a resolution of higher than 9 bits is
reaching the fundamental limit. However, a larger gap exists
for lower resolution ADCs. This suggests that the thermal
noise is not the bottleneck for the recently published lowresolution ADCs. Instead, their energy consumption is limited
by the peripheral circuits such as logic gates, clock buffers,
interconnections, and reference circuits.

The conventional FoM for Nyquist-rate ADCs is expressed


as the following [17]:
Pd
(3)
FoM =
min{ f c , 2 f in } 2ENOB
where Pd is the power consumption of the ADC, f c is the
conversion frequency, f in is the input frequency, and ENOB
is the effective number of bits.
If E c is the energy consumption of a dynamic comparator
and the logic gates associated with it, (3) can be rewritten as
the following for highly digital flash ADCs assuming Nyquistrate operation, f c = 2 fin
fc Ec 2 N
= E c 2ENOB
(4)
f c 2 NENOB
where ENOB is a reduction of ENOB from its ideal value.
Note that (4) only describes the energy efficiency of a flash
ADC without any information about its conversion rate. Therefore, reductions of E c and ENOB are sufficient to attain a
low FoM [23].
E c can be described by the following including the subthreshold leakage current consideration:


VT
VDD
2
E c = Ccmp VDD
+ Isub exp
(5)

S
fc
where Ccmp is the unit capacitance of a comparator, VDD is
the supply voltage, Isub is the unit current of the subthreshold
leakage current, VT is the threshold voltage, and S is the
subthreshold swing.
If the static current of the peripheral circuits, such as the
reference circuit, is also considered and distributed evenly
among the comparators, then (5) becomes the following:



VT
VDD
2
(6)
E c = Ccmp VDD + Istatic + Isub exp

S
fc
where Istatic is the unit current of the static current from the
peripheral circuits distributed among each comparator.
To derive the equation for ENOB, the following signalto-noise and distortion ratio (SNDR) equation should be
considered for a flash ADC assuming the comparator noise
can be neglected

2
N
2 Vq /2 2

SNDR = 10 log

Vq /12 + (Voff ( ))2



2
2 N Vq /2 2

= 10 log

Vq /12



Voff ( ) 2
(7)
10 log 1 + 12
Vq
FoM =

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LIN et al.: ULV HIGH-SPEED FLASH ADC DESIGN STRATEGY

Fig. 2.

Estimated E c , FoM, and 2ENOB versus VDD .

where Voff ( ) is one standard deviation of the offset voltage


distribution and Vq is the quantization voltage. The first part
of (7) is the signal-to-quantization-noise ratio and the second
part is the SNDR degradation due to the offset voltage.
By taking the second part of (7), ENOB can be expressed
as the following:

2 

10 log 1 + 12 VoffVq( )
ENOB =
20 log 2



Voff ( ) 2
1
.
(8)
= log2 1 + 12
2
Vq
The estimated E c , FoM, and 2ENOB versus VDD are shown
in Fig. 2 with the following parameters: N = 7 bits, Voff ( ) =
10 mV, VT = 0.25 V, and fc = 400 MHz. The remaining
parameters are extracted from measured data; Ccmp = 170 fF,
Isub = 156 A, and S = 44 mV.
2 , while ENOB
Fig. 2 shows that E c is proportional to VDD
is inversely proportional to VDD due to the decrease of the
quantization voltage with VDD reduction. However, 2ENOB is
small enough that its impact on the FoM is negligible. As a
result, the FoM can be significantly reduced by lowering the
supply voltage.
While supply voltage lowering saves energy, the conversion frequency is severely reduced. To alleviate this issue,
time interleaving of multiple ADC cores may be applied to
increase the conversion frequency. The FoM would remain
virtually the same assuming the power consumption from
the additional circuits and the reduction of ENOB are
negligible.
However, excessive interleaving causes many issues such
as an increase of occupied area, a reduction of process,
voltage, and temperature margins, a reduction of ENOB, and
an increase of input drive difficulty. Therefore, FD is proposed
in [18], much like the energy-delay product in digital circuits
[25], [26]. This index shows the tradeoff for techniques that
aggressively increase energy efficiency at the cost of latency.
The delay time is defined as the reciprocal value of the
maximum conversion frequency of a single ADC core for a
given operating voltage. Similar to the equation of a digital

Fig. 3.

Estimated FoM, delay, and FD product versus VDD .

gate delay [26], a flash ADC can be viewed as a complex


gate with its delay estimated using the following:
Td = k

VDD
(VDD VT )

(9)

where Td is the delay time, k and are the fitting constants


to account for latency due to circuit complexity and shortchannel effects, and VT is the effective threshold voltage.
By multiplying (6) and (9), the FD product can be written
as such





VT
VDD
2
+ Istatic + Isub exp

FD = Ccmp VDD
S
fc


VDD
k
.
(10)
(VDD VT )
Fig. 3 shows the FoM from Fig. 2, the estimated delay
calculated using (9), and the estimated FD product using (10)
for a highly digital flash ADC. The parameters used for this
estimation are the following: VT = 0.25 V, k = 0.6, and
= 1.7. In Fig. 3, the FD product clearly indicates when
the conversion rate is compromised due to the aggressive
minimization of FoM through supply voltage lowering. Using
the FD product as a guideline, it is possible to design a
very-energy-efficient ADC without severely compromising its
speed.
At a supply voltage of around 0.5 V, the FD product
shows a fair tradeoff between energy efficiency and conversion rate. Further reduction in the supply voltage causes
a drastic increase in latency. Therefore, this FD product
suggests there is a balance between the number of interleaving
cores and the decrease of energy consumption through supply
voltage lowering. The same FD value at different supply voltages indicates that the speed performance and the
energy efficiency can be freely exchanged by altering the
supply voltage.
III. C IRCUIT D ESIGN
A. Mismatch Compensation Methods in Ultralow Voltage
ULV operation limits the number transistor stacks of a
comparator. As a result, a double-tail latched comparator [27]
is selected as a suitable candidate owing to its reduced number

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

TABLE I
S IMULATION C OMPARISON FOR C ALIBRATION M ETHODS

Fig. 4. Variable time delay calibration to compensate the dynamic comparators process mismatch through the first-stage dynamic amplifier.

Fig. 5. Variable capacitance calibration using MOM capacitors and switches.

of transistor stacks compared with that of a conventional


single-tail latched comparator. However, without the conventional static preamplifiers, the large offset voltage needs to be
compensated. Two schemes are investigated as potential ULV
calibration candidates in this paper: variable delay and variable
capacitance.
Conventionally, MOS varactors are widely used to compensate for the mismatch of dynamic comparators [28], [29].
Unfortunately, the sensitivity of the MOS varactors capacitance to the control voltage degrades as the supply voltage
is reduced. As a result, two novel calibration techniques for
ULV high-speed circuits are explored. Firstly, a mismatch
compensation technique using variable time delay is developed
to suppress the offset voltage. Fig. 4 shows the schematic of
the calibration circuit. In Fig. 4, the activation clocks, CLK P
and CLK N , for the output nodes of the dynamic preamplifier
are controlled by variable delay circuits. In addition to the
variable delay technique, a variable capacitance method using
metaloxidemetal (MOM) capacitors and switches is also an
excellent candidate for ULV operation. The MOM calibration
circuit is shown in Fig. 5, where the digitally controlled
variable capacitance acts as the load for the dynamic preamplifier circuit in a dynamic double-tail latched comparator.
By modifying the variable capacitance, the offset voltage can
be compensated.
The performance of several commonly used digital mismatch calibration methods are simulated and listed in Table I.
All the compared calibration methods have a resolution
of 5 bits due to digital circuit area consideration. From
the Monte Carlo simulation, the input-referred offset voltage is approximately 10 mV( ) without any calibration.
To minimize the ENOB degradation due to mismatch to less

than 0.5 least significant bit (LSB), the target input-referred


offset voltage is less than 1 mV( ). The varactor method
cannot compensate the mismatch to a sufficient accuracy. The
current-based method sufficiently suppresses the mismatch,
but the power consumption is high. The timing calibration
using variable delay circuits offers a fair tradeoff between
accuracy, power consumption, and delay; however, it does
not achieve the target. The MOM calibration method offers
the best calibration accuracy and power consumption with a
reasonably small delay. Therefore, the MOM calibration is
the most suitable candidate for this work to achieve a low
FD product.
B. Capacitance Calibration Using MOM Capacitors
To determine the compensation range of a capacitive
scheme, the output voltage equation of the dynamic amplifier first needs to be examined. Using the configuration
in Fig. 5, the following output voltage equation can be
reached:
IDS
t
Cc
(VDD Veff ) Cc

Vout_amp = VDD
tf =
Veff

IDS
= VGS VT

(11)
(12)
(13)

where Voutamp is the output voltage of the preamplifier, IDS is


the average drain current of the input transistor, Cc is the average value of the calibration capacitance at the output node, t is
the amplification time, t f is the end of the amplification time,
Veff is the effective gate voltage, and VGS is the gatesource
voltage. By differentiating (11) with respect to capacitance,
the following is obtained:
 Vout_amp
IDS
VDD Veff
= 2 tf =
.
C
Cc
Cc

(14)

Dividing the  Voutamp from (14) by the gain of the


amplifier, the input-referred compensation range can be
determined
2 (VDD Veff )
(15)
G amp =
Veff
Veff C
(VDD Veff ) C
 Vin_cal =
=
(16)
G amp
Cc
2 Cc
where G amp is the gain of the dynamic amplifier, Vin cal is
the input-referred calibration range, and C is the tunable
part of the calibration capacitance. To cover a 30-mV(3 )
range, the C/Cc ratio must be greater than 0.66 assuming

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LIN et al.: ULV HIGH-SPEED FLASH ADC DESIGN STRATEGY

Fig. 7.
Fig. 6. Estimated C/Cc requirement versus effective gate voltage for
various input ranges with some typical C/Cc ratios from MOS varactors
and MOM capacitors.

Veff = 91 mV. This can be easily achieved using MOM


capacitors, but it is very difficult to realize using conventional MOS varactors operating in ULV. This issue is
twofold; the sensitivity of MOS varactors is reduced and
the effective gate voltages of the input pairs are lowered due to the reduced supply voltage. Fig. 6 shows
the effect of the effective gate voltage on C/Cc ratio
requirement for various input ranges with some typical
C/Cc ratios for conventional MOS varactors and MOM
capacitors.
If other capacitance Co , such as additional load capacitance
and parasitic capacitance, exists, the calibration range would
be attenuated according to the following:
Vin_cal =

Veff C
1
 .
2 Cc 1 + Co Cc

(17)

Conventionally, to suppress this attenuation, a large Cc /Co


ratio is required, which increases the power consumption and
the latency of the preamplifier. Alternatively, it is also possible
to overcome the attenuation by designing a larger C/Cc
ratio than the one required. Conveniently, MOM capacitors
can easily offer a large C/Cc ratio. Therefore, using MOM
capacitors, it is possible to cover a large calibration range with
a small Cc . By maintaining a small Cc , the MOM calibration
method achieves the FD design strategy by saving power and
enhancing the speed performance compared with conventional
MOS varactors.
C. All-Digital Time-Domain Delay Interpolation Technique
To further reduce the power consumption of an ULV flash
ADC, an all-digital time-domain delay interpolation technique [20] can be implemented. Conventionally, the flash
architecture requires 2 N1 comparators to realize an N-bit
ADC. This means that increasing the resolution results in
an exponential increase in the number of comparators and,
thus, causing an exponential rise in power consumption, input
capacitance, and chip area.
To reduce the negative impacts related to increasing resolution as mentioned above, the time-domain delay interpolation,
shown in Fig. 7, is implemented. The concept is to compare

All-digital time-domain delay interpolation schematic.

the delays of two adjacent dynamic comparators, where the


intersection of the two comparators delays is the interpolation
point. This technique is extremely well suited for ULV design
due to the increase of delay from the reduced supply voltage.
When comparing the delays of two adjacent comparators, the
signal is always closer to the comparator with a longer delay
due to the effect of metastability. Therefore, by analyzing
the delays, we can extract additional information to further
quantize the input signal.
The schematic of the delay interpolation circuit is also
shown in Fig. 7, which consists of only digital setreset (SR)
latches in parallel with the existing SR latches. Each interpolation SR latch serves as a time comparator to determine
which of the two adjacent comparators has a longer delay.
This implementation significantly reduces the additional power
consumption and chip area from the increase of resolution,
because digital SR latches are extremely low power and
compact when compared with a conventional comparator.
Moreover, the additional input capacitance related to the
increase of resolution is completely eliminated. Furthermore,
due to its digital implementation, it is readily applicable to
ULV design.
The effectiveness of this technique is demonstrated in
simulation by adding a 1-bit delay interpolation to a 5-bit
ADC core to realize a 6-bit ADC core. Conventionally, to
increase the resolution by one bit would virtually double the
power consumption as the number of comparators doubles.
By applying the proposed technique, the ENOB increases by
0.9 bits, while the additional power consumption is suppressed
to only 16% resulting in a total FoM reduction of 38%.
Furthermore, these interpolation SR latches are in parallel
with the existing SR latches resulting in only an additional
latch delay. As a result, this technique complies with the
FD-oriented design strategy by increasing the energy efficiency
without a significant reduction in speed.
D. Effects of Forward Body Biasing
When the supply voltage is reduced to 0.5 V, the gate delay
time increases significantly. To reduce this effect, the forward
body biasing (FBB) technique is introduced. By changing the
body bias voltage, the threshold can be altered according to
the following:



|VSB + 2 F | |2 F |
(18)
VT = VT0 +

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Fig. 9.

Schematic of the 6-bit ADC core with delay interpolation.

Fig. 8. (a) Normalized gate delay time and estimated FD product versus
supply voltage with and without FBB and (b) schematic of tunable body
biases.

where VT0 is the threshold voltage when VSB = 0 V, is the


body effect parameter, 2 F is the surface potential, and VSB
is the sourcebody voltage.
At 0.5 V operation, the supply voltage is lower than the
built-in potential of the p-n junction. Thus, body biasing can
be used safely without the risk of latch-up. The measured
maximum reduction of VT due to FBB is 100 mV for nMOS
and 60 mV for pMOS transistors. The gate delay time can
be reduced to about half of the conventional CMOS circuit,
as shown in Fig. 8(a). Furthermore, Fig. 8 estimates the
FD product reduction due to FBB with the FoM values
from Fig. 2.
Changing VT enables speed enhancement at the cost of additional subthreshold leakage current. By substituting (9) and
(18) into (6), we can reach the following energy consumption
equation for each comparator, its related logic circuits, and its
share of the peripheral circuits

2
+ Istatic+Isub exp
E c = Ccmp VDD
 



|2 F +VSB | |2 F |
VT0 +

S


VDD VT0

2
kVDD

 .

|2 F +VSB | |2 F |

(19)

Equation (19) shows that it is possible to tune VSB to minimize


the energy consumption. If VSB is too small, a significant
amount of energy would be spent on the static current of
the peripheral circuits due to the slow conversion frequency.
If VSB is too large, the subthreshold leakage would consume
a substantial amount of energy. Therefore, to increase the
conversion efficiency, a suitable VSB should be chosen so
that the energy consumption due to the static current and
subthreshold leakage are balanced and minimized.
To make the body biasing tunable, the body terminals of
pMOS and nMOS are independently accessible as shown in
Fig. 8(b). By doing so, the nMOS and pMOS body terminals
can both be accessed independently to observe the effect of
body biasing on latency and energy efficiency. Although it is
not realized in this prototype, it is possible to implement a
low-power programmable resistive digital-to-analog converter
(RDAC) to control the body voltages on chip with the VBN and
VBP decoupled to ground and VDD , respectively. This would

Fig. 10.
(a) Estimated error rate due to nonisolated bubbles versus
quantization voltage for various noise levels and (b) the specific case that
is used to estimate the error rate.

suppress the impact of high-frequency supply variation. As


for VDD droop and temperature variation, these would require
a background calibration, which is a topic that is out of the
scope of this paper.
E. Overall Design of ADC
Fig. 9 shows the 6-bit ADC core with the delay interpolation
used in this ADC. Nine sample-and-hold (S/H) circuits
act as an input interface. This is to increase the available input frequency and to realize a flexible interface to
signals with a different common-mode voltage from that
of the ADC. However, it also increases the input capacitance, input switching current, and power consumption of
the ADC as the driving power for the S/H circuits will
increase. In contrast, two-bit gate-interpolation technique [30]
is implemented in the comparators to reduce the ADCs
power consumption. SR latches are inserted between adjacent comparators to realize delay interpolation. An array
of 5-bit up/down counters is used for the digital mismatch
compensation.
The bubble error is a well-known issue with the flash
architecture. Often, isolated bubbles can be easily corrected
with a simple digital error correction circuit. However, two
or more adjacent bubbles usually require a more sophisticated
correction method resulting in additional hardware overhead
and latency. In this ADC, two 6-bit ADC cores each with a
different shifted output curve are summed together to form a
7-bit ADC core. This enhances the robustness of the 7-bit ADC
core as the quantization voltage of each 6-bit ADC core is
double. Furthermore, each 6-bit ADC core can tolerate isolated
bubbles, thus increasing the 7-bit ADC cores immunity to
static and dynamic errors. Fig. 10(a) shows the estimated

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LIN et al.: ULV HIGH-SPEED FLASH ADC DESIGN STRATEGY

Fig. 11. Block diagram of the two-way time-interleaved 7-bit flash ADC
consisting of 4 6-bit ADC cores.

Fig. 13. Measured DNL at a conversion rate of 100 MS/s with a single core.

Fig. 14. Measured INL at a conversion rate of 100 MS/s with a single core.

Fig. 12.
Chip layout of the two-way time-interleaved 7-bit flash ADC
consisting of four 6-bit ADC cores.

probability of error due to two adjacent bubbles caused by


noise. The error rate is estimated by calculating the probability
of occurrence of a specific and most probable case shown in
Fig. 10(b) given that the input signal level is exactly at a
comparators threshold voltage.
Fig. 11 shows the overall block diagram of the ADC
presented in this paper. This ADC contains two 7-bit
ADC cores that are realized with four 6-bit ADC cores.
To reduce the added delay due to ULV operation, two
7-bit ADC cores are time-interleaved to obtain high-speed
operation.
IV. E XPERIMENTAL R ESULTS
The prototype ULV flash ADC is fabricated using a 90-nm
CMOS technology with the deep n-well and the low threshold
voltage options. The prototype is packaged using an 80-pin
quad flat package and measured on a printed circuit board.
Fig. 12 shows the chip layout of this ADC with a total occupied area of 0.39 mm2 . Approximately 1% of the total area
is occupied by the all-digital time-domain delay interpolation
for resolution enhancement.

Fig. 15. Measured two-way time-interleaved ADCs SNDR and SFDR versus
conversion rate with a 1-MHz input signal.

With a slow ramp input of approximately 10 kHz, the


static performance of this ADC is measured at a conversion
rate of 100 MS/s. Figs. 13 and 14 show the measured DNL
and INL with and without calibration with a 0.5 V supply.
After performing the capacitance calibration using MOM
capacitors, the DNL and INL are reduced to less than 0.95
and 0.97 LSB, respectively.
To measure the dynamic performance, a sinusoidal input is
applied. Fig. 15 shows the two-way time-interleaved ADCs

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Fig. 16. Measured SNDR versus input frequency, which shows the ERBW of
each single core and the interleaved ADC with a conversion rate of 210 MS/s
and 420 MS/s, respectively.

SNDR and spurious free dynamic range (SFDR) versus the


conversion frequency when the input signal is about 1 MHz
with a 0.5 V supply voltage. The SNDR remains higher than
35 dB (5.5-ENOB) up to 600 MS/s. This shows that with a
low frequency input, the prototype ADC performs well up to
600 MS/s.
Fig. 16 shows the SNDR versus the input frequency, which
shows effective resolution bandwidths (ERBWs) of 50 and
200 MHz for the interleaved and single core ADCs operating
at 420 and 210 MS/s, respectively. Although each ADC core
can achieve high input bandwidth, the interleaved ADC cannot
maintain its high performance up to the Nyquist rate due
to the clock skew in the clock generator. The low ERBW
[i.e., low f in in (3)] results in a degraded FoM of 0.9 pJ/conv.step for the interleaved ADC at 420-MS/s conversion rate
while consuming 4.1 mW from a 0.5 V. The single-core
operation results in a much lower FoM of 195 fJ/conv.-step
at a conversion rate of 210 MS/s while consuming 2.1 mW.
Considering the conversion latency, the measured FD product
shows that the interleaved ADC reaches 4.31 pJ ns/conv.step while the single core ADC achieves an extremely low FD
product of 0.93 pJ ns/conv.-step.
At 420 MS/s, this ADC consumes 0.5 mW of static power
from the reference ladders and 2.6 mW of leakage power
due to the FBB at 0.5 V. To increase the efficiency of the
ADC, the body biasing voltage can be tuned to give a better
balance between the static power, leakage power, and dynamic
power.
The delay and energy consumption versus body biasing
relationship is shown in Fig. 17. The pie charts in Fig. 17
clearly show that without FBB, a significant of energy is
spent on static current for peripheral circuits such as the
reference circuit. By applying FBB, the latency of the ADC
is reduced at the cost of larger leakage current. This figure
shows that the lowest energy consumption can be obtained at
VBS = 0.3 V, while the highest conversion rate can be achieved
at VBS = 0.5 V. Therefore, by tuning the body biasing voltage
(VBS ), the energy consumption can be altered up to 8% while
the latency changes up to 2.4 times. To maximize the speed
of this ADC, a VBS of 0.5 V is applied.

Fig. 17.
Measured delay and energy consumption versus VBS and the
energy consumption distribution among static, leakage, and dynamic power
consumptions.

The performance summary is presented in Table II along


with other state-of-the-art ULV ADCs. As mentioned in
Section I, the conventional FoM for Nyqust-rate ADCs
strictly focuses on energy efficiency. As a result, the merit
of conversion rate is not reflected. Using the proposed FD
product, the latency information becomes apparent. Taking
[13] and [14] as an example, [14] achieves an extremely
low FoM that is more than 2.5 times lower than [13]. However, the difference of 25 times in speed is ignored if one
only looks at the FoM. The proposed FD product captures
this difference resulting in [13] having a lower FD product
than [14]. Compared with all of the state-of-the-art ULV ADCs
listed in Table II, this paper achieves at least 3.5 times speed
enhancement in single-core operation and around 3 times
improvement in FD product.
The improvement stems from the speed consideration
throughout the entire design process. To realize ULV highspeed operation, dynamic comparators are employed. To suppress the offset voltages of the dynamic comparators without significantly compromising the speed, MOM capacitance
calibration is implemented. Since MOM capacitors have a
large C/Cc ratio, it achieves high speed and low power
while offering a wide calibration range. To further enhance
the resolution with a minimal power penalty, a time-domain
delay interpolation is realized using all-digital SR latches.
These interpolation latches process the timing information
from the comparators in parallel with the existing latches,
resulting in very little speed penalty. These techniques all
follow the FD concept improving the energy efficiency of the
circuit without significantly compromising the speed performance. Using the FD product, the tradeoff between energy
efficiency and speed performance of the circuit can be clearly
evaluated.

This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
LIN et al.: ULV HIGH-SPEED FLASH ADC DESIGN STRATEGY

TABLE II
P ERFORMANCE C OMPARISON W ITH O THER S TATE - OF - THE -A RT ULV ADCs

V. C ONCLUSION
In this paper, the ULV design strategy for high-speed
flash ADCs is explored for future technology and low-energy
operation. By adopting a lower supply voltage, the energy consumption can be significantly reduced at the cost of conversion
speed. As a result, a new index, the FD product, is proposed to
offer a better guideline between the energy efficiency and the
conversion speed. To overcome the challenges associated with
a reduced supply voltage, many circuit techniques applicable at
ULV operation are examined. The MOM capacitance calibration strongly supports the FD design strategy. In addition, the
all-digital time-domain delay interpolation technique further
increases the energy efficiency. This paper also investigates the
relationship between body bias, latency, and energy efficiency
for the flash architecture.
To validate the proposed design strategy, a 7-bit flash ADC
is designed and fabricated in 90-nm CMOS to operate with
a 0.5 V supply voltage. Using two-way interleaving, the
prototype achieves a maximum conversion rate of 420 MS/s
with an ERBW of 50 MHz. The total power consumption
of the interleaved ADC is 4.1 mW. During the single-core
operation, the ADC achieves 210 MS/s conversion rate with
an ERBW of 200 MHz. Since only one core is in operation,
the power consumption becomes 2.1 mW. This results in a
low FoM of 195 fJ/conv.-step and an extreme low FD product
of 0.93 pJ ns/conv.-step. In conclusion, the ULV design can
significantly reduce the energy consumption of highly digital
flash ADCs. Using the proposed FD-oriented design, this paper
achieves at least 3.5 times speed enhancement compared with
other state-of-the-art ULV ADCs, lowering the FD product by
a factor of three.
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James Lin (S11) received the B.A.Sc. degree


in electrical engineering from the University of
Toronto, Toronto, ON, Canada, in 2009 and the M.E.
degree in physical electronics from the Tokyo Institute of Technology, Tokyo, Japan, in 2011, where he
is currently working toward the Ph.D. degree.
His current research interests include ultralowvoltage circuits and mixed-signal circuits, in particular, data converters.

Ibuki Mano received the B.E. and M.E. degrees


in physical electronics from the Tokyo Institute
of Technology, Tokyo, Japan, in 2011 and 2013,
respectively.
He is currently with the HIOKI E.E. Corporation,
Nagano, Japan.

Masaya Miyahara (M09) received the B.E. degree


in mechanical and electrical engineering from the
Kisarazu National College of Technology, Kisarazu,
Japan, in 2004 and the M.E. and Ph.D. degrees
in physical electronics from the Tokyo Institute
of Technology, Tokyo, Japan, in 2006 and 2009,
respectively.
He has been an Assistant Professor with the
Department of Physical Electronics, Tokyo Institute
of Technology, since 2009. His current research
interests include RF complementary metaloxide
semiconductor and mixed-signal circuits.

Akira Matsuzawa (M88SM01F02) received


the B.S., M.S., and Ph.D. degrees in electronics
engineering from Tohoku University, Sendai, Japan,
in 1976, 1978, and 1997, respectively.
He joined Matsushita Electric Industrial Company,
Ltd., Osaka, Japan, in 1978. Since then, he has
been engaged in research and development of analog
and mixed-signal LSI technologies, ultrahigh-speed
ADCs, intelligent CMOS, RF CMOS circuits, and
digital read-channel technologies for DVD systems.
From 1997 to 2003, he was a General Manager with
the Advanced LSI Technology Development Center, Tochigi, Japan. In 2003,
he joined the Tokyo Institute of Technology, Tokyo, Japan, where he is a
Professor of Physical Electronics. His current research interests include mixedsignal technologies, RF CMOS circuit design for SDR, and high-speed data
converters.
Dr. Matsuzawa has been an IEICE Fellow since 2010. He served as the
Guest Editor-in-Chief of the special issue on analog LSI technology of
the IEICE Transactions on Electronics in 1992, 1997, and 2003, the ViceProgram Chairman of the International Conference on Solid-State Devices
and Materials in 1999 and 2000, the Guest Editor of special issues of the
IEEE T RANSACTIONS ON E LECTRON D EVICES , a Committee Member of
the Analog Technology in International Solid-State Circuits Conference, the
Educational Session Chair of the Asian Solid-State Circuits Conference,
an Executive Committee Member of the VLSI Symposia, the IEEE SolidState Circuits Society (SSCS) Elected Adcom, the IEEE SSCS Distinguished
Lecturer, the Chapter Chair of the IEEE SSCS Japan Chapter, and the Vice
President of the Japan Institution of Electronics Packaging. He was a recipient
of the IR100 Award in 1983, the Research and Development 100 Award, the
Remarkable Invention Award in 1994, and the ISSCC Evening Panel Award
in 2003 and 2005.

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