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I. I NTRODUCTION
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Fig. 1.
(1)
(2)
Fig. 1 plots the recently published ADCs energy consumption against their resolution [24]. Equations (1) and (2) are also
shown in Fig. 1. Fig. 1 shows that the energy consumption
of current ADCs with a resolution of higher than 9 bits is
reaching the fundamental limit. However, a larger gap exists
for lower resolution ADCs. This suggests that the thermal
noise is not the bottleneck for the recently published lowresolution ADCs. Instead, their energy consumption is limited
by the peripheral circuits such as logic gates, clock buffers,
interconnections, and reference circuits.
S
fc
where Ccmp is the unit capacitance of a comparator, VDD is
the supply voltage, Isub is the unit current of the subthreshold
leakage current, VT is the threshold voltage, and S is the
subthreshold swing.
If the static current of the peripheral circuits, such as the
reference circuit, is also considered and distributed evenly
among the comparators, then (5) becomes the following:
VT
VDD
2
(6)
E c = Ccmp VDD + Istatic + Isub exp
S
fc
where Istatic is the unit current of the static current from the
peripheral circuits distributed among each comparator.
To derive the equation for ENOB, the following signalto-noise and distortion ratio (SNDR) equation should be
considered for a flash ADC assuming the comparator noise
can be neglected
2
N
2 Vq /2 2
SNDR = 10 log
= 10 log
Vq /12
Voff ( ) 2
(7)
10 log 1 + 12
Vq
FoM =
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LIN et al.: ULV HIGH-SPEED FLASH ADC DESIGN STRATEGY
Fig. 2.
Fig. 3.
VDD
(VDD VT )
(9)
FD = Ccmp VDD
S
fc
VDD
k
.
(10)
(VDD VT )
Fig. 3 shows the FoM from Fig. 2, the estimated delay
calculated using (9), and the estimated FD product using (10)
for a highly digital flash ADC. The parameters used for this
estimation are the following: VT = 0.25 V, k = 0.6, and
= 1.7. In Fig. 3, the FD product clearly indicates when
the conversion rate is compromised due to the aggressive
minimization of FoM through supply voltage lowering. Using
the FD product as a guideline, it is possible to design a
very-energy-efficient ADC without severely compromising its
speed.
At a supply voltage of around 0.5 V, the FD product
shows a fair tradeoff between energy efficiency and conversion rate. Further reduction in the supply voltage causes
a drastic increase in latency. Therefore, this FD product
suggests there is a balance between the number of interleaving
cores and the decrease of energy consumption through supply
voltage lowering. The same FD value at different supply voltages indicates that the speed performance and the
energy efficiency can be freely exchanged by altering the
supply voltage.
III. C IRCUIT D ESIGN
A. Mismatch Compensation Methods in Ultralow Voltage
ULV operation limits the number transistor stacks of a
comparator. As a result, a double-tail latched comparator [27]
is selected as a suitable candidate owing to its reduced number
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TABLE I
S IMULATION C OMPARISON FOR C ALIBRATION M ETHODS
Fig. 4. Variable time delay calibration to compensate the dynamic comparators process mismatch through the first-stage dynamic amplifier.
Vout_amp = VDD
tf =
Veff
IDS
= VGS VT
(11)
(12)
(13)
(14)
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LIN et al.: ULV HIGH-SPEED FLASH ADC DESIGN STRATEGY
Fig. 7.
Fig. 6. Estimated C/Cc requirement versus effective gate voltage for
various input ranges with some typical C/Cc ratios from MOS varactors
and MOM capacitors.
Veff C
1
.
2 Cc 1 + Co Cc
(17)
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Fig. 9.
Fig. 8. (a) Normalized gate delay time and estimated FD product versus
supply voltage with and without FBB and (b) schematic of tunable body
biases.
|2 F +VSB | |2 F |
VT0 +
S
VDD VT0
2
kVDD
.
|2 F +VSB | |2 F |
(19)
Fig. 10.
(a) Estimated error rate due to nonisolated bubbles versus
quantization voltage for various noise levels and (b) the specific case that
is used to estimate the error rate.
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LIN et al.: ULV HIGH-SPEED FLASH ADC DESIGN STRATEGY
Fig. 11. Block diagram of the two-way time-interleaved 7-bit flash ADC
consisting of 4 6-bit ADC cores.
Fig. 13. Measured DNL at a conversion rate of 100 MS/s with a single core.
Fig. 14. Measured INL at a conversion rate of 100 MS/s with a single core.
Fig. 12.
Chip layout of the two-way time-interleaved 7-bit flash ADC
consisting of four 6-bit ADC cores.
Fig. 15. Measured two-way time-interleaved ADCs SNDR and SFDR versus
conversion rate with a 1-MHz input signal.
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Fig. 16. Measured SNDR versus input frequency, which shows the ERBW of
each single core and the interleaved ADC with a conversion rate of 210 MS/s
and 420 MS/s, respectively.
Fig. 17.
Measured delay and energy consumption versus VBS and the
energy consumption distribution among static, leakage, and dynamic power
consumptions.
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LIN et al.: ULV HIGH-SPEED FLASH ADC DESIGN STRATEGY
TABLE II
P ERFORMANCE C OMPARISON W ITH O THER S TATE - OF - THE -A RT ULV ADCs
V. C ONCLUSION
In this paper, the ULV design strategy for high-speed
flash ADCs is explored for future technology and low-energy
operation. By adopting a lower supply voltage, the energy consumption can be significantly reduced at the cost of conversion
speed. As a result, a new index, the FD product, is proposed to
offer a better guideline between the energy efficiency and the
conversion speed. To overcome the challenges associated with
a reduced supply voltage, many circuit techniques applicable at
ULV operation are examined. The MOM capacitance calibration strongly supports the FD design strategy. In addition, the
all-digital time-domain delay interpolation technique further
increases the energy efficiency. This paper also investigates the
relationship between body bias, latency, and energy efficiency
for the flash architecture.
To validate the proposed design strategy, a 7-bit flash ADC
is designed and fabricated in 90-nm CMOS to operate with
a 0.5 V supply voltage. Using two-way interleaving, the
prototype achieves a maximum conversion rate of 420 MS/s
with an ERBW of 50 MHz. The total power consumption
of the interleaved ADC is 4.1 mW. During the single-core
operation, the ADC achieves 210 MS/s conversion rate with
an ERBW of 200 MHz. Since only one core is in operation,
the power consumption becomes 2.1 mW. This results in a
low FoM of 195 fJ/conv.-step and an extreme low FD product
of 0.93 pJ ns/conv.-step. In conclusion, the ULV design can
significantly reduce the energy consumption of highly digital
flash ADCs. Using the proposed FD-oriented design, this paper
achieves at least 3.5 times speed enhancement compared with
other state-of-the-art ULV ADCs, lowering the FD product by
a factor of three.
R EFERENCES
[1] K. Okada et al., Full four-channel 6.3-Gb/s 60-GHz CMOS
transceiver with low-power analog and digital baseband circuitry, IEEE
J. Solid-State Circuits, vol. 48, no. 1, pp. 4665, Jan. 2013.
[2] B. Verbruggen, J. Craninckx, M. Kuijk, P. Wambacq, and
G. van der Plas, A 2.2 mW 1.75 GS/s 5 bit folding flash ADC
in 90 nm digital CMOS, IEEE J. Solid-State Circuits, vol. 44, no. 3,
pp. 874882, Mar. 2009.
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