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Data Sheet
July 1999
File Number
3575.4
Features
50A, 60V
rDS(ON) = 0.022
Temperature Compensating PSPICE Model
Peak Current vs Pulse Width Curve
UIS Rating Curve
175oC Operating Temperature
Symbol
Ordering Information
PART NUMBER
PACKAGE
BRAND
RFG50N06
TO-247
RFG50N06
RFP50N06
TO-220AB
RFP50N06
RF1S50N06SM
TO-263AB
F1S50N06
NOTE: When ordering, use the entire part number. Add the suffix, 9A,
to obtain the TO-263AB variant in tape and reel, i.e. RF1S50N06SM9A.
Packaging
JEDEC STYLE TO-247
JEDEC TO-220AB
SOURCE
DRAIN
GATE
DRAIN
(BOTTOM
SIDE METAL)
DRAIN
(FLANGE)
SOURCE
DRAIN
GATE
JEDEC TO-263AB
DRAIN
(FLANGE)
GATE
SOURCE
4-467
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
PSPICE is a registered trademark of MicroSim Corporation.
http://www.intersil.com or 407-727-9207 | Copyright Intersil Corporation 1999
RFG50N06, RFP50N06
RF1S50N06SM
60
60
20
50
(Figure 5)
(Figure 6, 14, 15)
131
0.877
-55 to 175
UNITS
V
V
V
A
W
W/oC
oC
oC
oC
300
260
CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. TJ = 25oC to 150oC.
Electrical Specifications
TYP
MAX
UNITS
PARAMETER
SYMBOL
BVDSS
TEST CONDITIONS
60
VGS(TH)
TC = 25oC
TC = 150oC
IDSS
VDS = 60V,
VGS = 0V
50
IGSS
VGS = 20V
100
nA
0.022
95
ns
12
ns
55
ns
td(OFF)
37
ns
tf
13
ns
rDS(ON)
Turn-On Time
tON
td(ON)
Rise Time
tr
tOFF
Qg(TOT)
VGS = 0 to 20V
Qg(10)
VGS = 0 to 10V
Qg(TH)
VGS = 0 to 2V
Input Capacitance
CISS
Output Capacitance
COSS
CRSS
75
ns
125
150
nC
67
80
nC
3.7
4.5
nC
2020
pF
600
pF
200
pF
RJC
(Figure 3)
1.14
oC/W
RJA
TO-247
30
oC/W
TO-220, TO-263
62
oC/W
SYMBOL
VSD
trr
4-468
TEST CONDITIONS
MIN
TYP
MAX
UNITS
ISD = 50A
1.5
125
ns
1.2
60
1.0
50
ID , DRAIN CURRENT (A)
0.8
0.6
0.4
0.2
40
30
20
10
0
0
0
25
50
75
100
125
TC , CASE TEMPERATURE (oC)
150
25
175
50
75
100
125
150
175
THERMAL IMPEDANCE
ZJC, NORMALIZED
1
0.5
0.2
0.1
0.1
PDM
0.05
t1
0.02
0.01
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZJC x RJC + TC
SINGLE PULSE
0.01 -5
10
10-4
10-3
10-2
10-1
t1 , RECTANGULAR PULSE DURATION (s)
101
100
100
100s
1ms
10
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
103
TJ = MAX RATED
SINGLE PULSE
TC = 25oC
10ms
VDSS(MAX) = 60V
1
100
175 T C
I = I 25 ------------------------
150
VGS = 20V
VGS = 10V
TC = 25oC
102
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
100ms
DC
10
4-469
400
40
10-3
10-2
10-1
100
101
102
t, PULSE WIDTH (ms)
103
104
300
125
100
VGS = 10V
STARTING TJ = 25oC
STARTING TJ = 150oC
10
If R = 0
tAV = (L) (IAS) / (1.3 RATED BVDSS - VDD)
VGS = 7V
75
50
0.1
VGS = 6V
VGS = 5V
25
If R 0
tAV = (L/R) ln [(IAS*R) / (1.3 RATED BVDSS - VDD) + 1]
1
0.01
VGS = 8V
100
VGS = 4V
0
0
10
1.5
3.0
4.5
6.0
7.5
100
-55oC
2.5
25oC
125
175oC
75
50
25
0
0
2.0
1.5
1.0
0.5
0
-80
10
-40
80
120
160
200
2.0
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
40
2.0
1.5
1.0
0.5
0
-80
-40
40
80
120
160
200
4-470
ID = 250A
1.5
1.0
0.5
0
-80
-40
40
80
120
160
200
3000
C, CAPACITANCE (pF)
10
60
4000
CISS
2000
COSS
1000
CRSS
0
0
10
15
20
VDD = BVDSS
VDD = BVDSS
7.5
45
5.0
30
0.75 BVDSS
0.75 BVDSS
0.50 BVDSS
0.50 BVDSS
0.25 BVDSS
0.25 BVDSS
RL = 1.2
Ig(REF) = 1.45mA
VGS = 10V
15
2.5
25
20
Ig(REF)
t, TIME (s)
Ig(ACT)
80
Ig(REF)
Ig(ACT)
tP
VARY tP TO OBTAIN
REQUIRED PEAK IAS
RG
VDS
IAS
VDD
VDD
-
VGS
DUT
tP
0V
IAS
0
0.01
tAV
tON
tOFF
td(ON)
VDS
td(OFF)
tf
tr
VDS
90%
90%
RL
VGS
DUT
RGS
VGS
VDD
90%
VGS
0
4-471
10%
10%
10%
50%
50%
PULSE WIDTH
(Continued)
VDS
VDD
RL
Qg(TOT)
VDS
VGS = 20V
VGS
Qg(10)
VDD
DUT
Ig(REF)
VGS = 10V
VGS
VGS = 2V
0
Qg(TH)
Ig(REF)
0
4-472
CA 12 8 3.68e-9
CB 15 14 3.625e-9
CIN 6 8 1.98e-9
DRAIN
2
LDRAIN
DBODY 7 5 DBDMOD
DBREAK 5 11DBKMOD
DPLCAP 10 5 DPLCAPMOD
10
DBREAK
EVTO
9
1
LGATE
20
GATE
RGATE
18
8
RDRAIN
6
8
VTO
16
ESG
+
EBREAK 11 7 17 18 64.59
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTO 20 6 18 8 1
DPLCAP
MOS1
RIN
8
12
LDRAIN 2 5 1e-9
LGATE 1 9 5.65e-9
LSOURCE 3 7 4.13e-9
13
8
S1B
+
EGS 6
- 8
17
EBREAK
18
RSOURCE
LSOURCE
S2A
14
13
15
17
RBREAK
S2B
13
CA
11
CIN
IT 8 17 1
S1A
DBODY
MOS2
21
3
SOURCE
18
RVTO
CB
14
+
5
EDS 8
IT
19
VBAT
+
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 8 19 DC 1
VTO 21 6 0.678
.MODEL DBDMOD D (IS=9.85e-13 RS=4.91e-3 TRS1=2.07e-3 TRS2=2.51e-7 CJO=2.05e-9 TT=4.33e-8)
.MODEL DBKMOD D (RS=1.98e-1 TRS1=2.35E-4 TRS2=-3.83e-6)
.MODEL DPLCAPMOD D (CJO=1.42e-9 IS=1e-30 N=10)
.MODEL MOSMOD NMOS (VTO=3.65 KP=35 IS=1e-30 N=10 TOX=1 L=1u W=1u)
.MODEL RBKMOD RES (TC1=1.23e-3 TC2=-2.34e-7)
.MODEL RDSMOD RES (TC1=5.01e-3 TC2=1.49e-5)
.MODEL RVTOMOD RES (TC1=-5.03e-3 TC2=-5.16e-6)
.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-6.75 VOFF=-2.5)
.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2.5 VOFF=-6.75)
.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2.7 VOFF=2.3)
.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=2.3 VOFF=-2.7)
.ENDS
NOTE: For further discussion of the PSPICE model consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature
Options; authors, William J. Hepp and C. Frank Wheatley.
4-473
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
4-474
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