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Binod Kumar
CADSL Group Seminar
IITB
outline
Introduction(Prologue)
Motivation
Problem Statement
Results
Drawbacks
PROLOGUE
PREVIOUS DEBUG
ARCHITECTURE
* E. Anis and N. Nicolici, Low cost debug architecture using lossy compression
for silicon debug, Proc. Design, Autom., Test Euro., pp. 16,2007
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MOTIVATION
GOLDEN RESPONSE
CY 1
CY2
CY 3
CY 4
CY 5
FF A
FF B
FF C
FF D
FF E
CY 1
CY 2
CY 3
CY 4
CY 5
FF A
FF B
FF C 0
FF D 0
FF E
* Joon-Sung Yang and Nur A. Touba ,Improved Trace Buffer Observation via Selective Data Capture Using
2-D Compaction for Post-Silicon Debug TVLSI, 2013.
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Session 2:Compaction
Session 2 : Compaction
Illustration(Example 1)
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nd
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Cycle tag bit shift register is used to provide serial access to the
tag bits so they can be checked one bit at a time each clock cycle.
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Experimental Results
[14]J. Shen and J. A. Abraham, Verification of processor microarchitectures, in Proc. IEEE VLSI Test Symp., 1999, pp. 189
194.
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DrawbacksNeed of further
investigation
1.As the tag data is read out of the trace buffer, it
can be overwritten in the trace buffer by the
captured data.
2.There is a need to calculate the area overhead
due to the debug module & look for ways to reduce
it.
3.Aliasing may also happen in the signatures.
4.Reducing the amount of tag bits that are
generated.
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