Lokender Singh Shekhawat

50, Fozdar New Park,

Ahmedabad-382345, Gujarat, India

shekhavl123@gmail.com

+91-8141924263

M.Tech from Nirma University with excellent academic record and keen interest and practical exposure in the field of
Physical Design, Signal Integrity & Power Integrity, Antenna Design, Verification, Automation and Wireless
Communication.

Core Competency
Good understanding of inputs and outputs of all the stages in the physical design flow i.e. floor planning, power
planning, clock tree synthesis, signal integrity, routing, design rule check and parasitic extraction (Making SPEF
file).
In clock tree synthesis, good understanding of clock tree quality check parameters (skew, latency, transition
variation etc...), H Tree, modelling of clock tree and buffered H Tree.
In signal integrity, good understanding of impedance mismatch, crosstalk, glitch effect, timing windows, crosstalk,
crosstalk delta delay analysis, noise protection technique, rail collapse noise, EMI, radiation issue, power supply
noise and power mesh solution.

Work Experience
STMicroelectronics India Ltd. (1 Year-Full Time)

June15- June16

Project: Power Integrity Analysis for Designs and its Automation

Parasitic extraction for PCB, Package, and substrate level interconnects using EM solver tools (Cadence
Sigrity Tool POWERSI).
Power Delivery Network (PDN) optimization for meeting the target impedance requirement in Keysight
ADS.
System modeling for High Speed links with integrated board, package, I/O pad ring models, CPM, Output
buffer SPICE netlists and then doing the transient simulations in integrated environment with ADS.
Obtained current profile of buffers under worst case scenario in order to observe the effect of SSN
(Simultaneous Switching Noise).
Co-Simulation of obtained system level models and the total variation in power supply was extracted in
ADS. The extracted power supply profile is then used to obtain the clock jitter.
Automation of importing design (i.e. netlist file such as SPICE file), Template design (Schematic/Layout
design) and DDS (Data Display Window) handling for PDN Optimization (Power Integrity Analysis) in ADS
using AEL script.
Project: S-Parameter Extraction from VNA
Calibration of VNA using SOLT technique.
Extraction of S-Parameters of a differential transmission line using VNA.
Analysis of the co-efficient of S-Parameters.
M.Tech Work

June14- May15

Project: Designed a Microstrip Patch Antenna using ANSYS HFSS

Designed a rectangular Microstrip patch antenna which radiates at 2.4 GHz using FR4 material. The
simulation was done using ANSYS HFSS simulation tool.
Project: Communication between Python & 8051 Microcontroller
This project emphasis on the serial communication between python and the microcontroller 8051. Both
Python and 8051 are serially configured and Python user can send a command to turn on/off a LED which
connected to the 8051.
Seminar: Application of Game Theory in Wireless Communication
Applied the algorithm of game theory in wireless communication to solve the issues like power control,
medium access control, call admission control, spectrum allocation and routing.

Technical Skills
Programming Languages

Application Extension Language (Keysight ADS), C, System

Verilog

Scripting Languages

TCL, Python, Shell script

Technical Software Tools

Keysight ADS, Cadence PowerSI, Synopsys HSPICE, Ansys

HFSS, MATLAB, Network Simulator, XILINX ISE

Trainings and MOOCs Online course

Did an summer internship with Reliance communications:

Exposure to Networking, Switches, IP addressing/subneting.
Optical Time Domain Reflectometer (OTDR), E1 carrier systems,
MNP.
UDEMYs Course: VLSI Academy Physical Design Flow
UDEMYs Course: VLSI Academy Signal Integrity
UDEMYs Course: VLSI Academy Clock Tree Synthesis Part 1
UDEMYs Course: SOC Verification Using System Verilog
UDEMYs Course: Learn System Verilog Assertions & Coverage Coding in depth
UDEMYs Course: Learn to build OVM and UVM Test benches from Scratch
VLSI-Expert: Static Timing Analysis
Courseras Course: Wireless Communication Emerging Technologies by Yonsei University

Education
M.Tech EC- (Communication Engineering)
IT-NU, CGPA 7.9/10

2014-16

B.E, Electronics and Communication Engineering

BMIT Jaipur RTU, 72.26%

2009-13

Web Presence

LinkedIn Profile: https://in.linkedin.com/in/lokender-singh-shekhawat-47ab6732 .

Blog Link: www.signalintegriti.blogspot.in

Declaration

I hereby declare that the above written particulars are true and correct to the best of my knowledge and
belief.

Date & Place

(Lokender Singh Shekhawat)