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Lecturer, Faculty of Electronics and Computer Engineering (FKEKK), University Teknikal Malaysia Melaka (UTeM),
Melaka, Malaysia, hafez@utem.edu.my
2, 3
Lecturer, 4 Senior Lecturer, Faculty of Electrical Engineering (FKE), University Teknikal Malaysia Melaka (UTeM),
Melaka, Malaysia, mohd.hafiz@utem.edu.my, tarmizi@utem.edu.my, mahidzal@um.edu.my
Abstract
Zeta converter is a fourth order dc-dc converter that can increases (step-up) or decreases (step-down) the input voltage. By
considering dynamic model of the converter, the accuracy of the converters modeling and simulation are increased thus make it
easier to produce the hardware version of the converter. State-space approach is a time-domain method for modeling, analyzing, and
designing a wide range of systems which can be described by differential equations or difference equations. This gives great
advantages because it particularly suited for digital computer implementation for their time-domain approach and vector-matrix
description. The converter needs feedback control to regulate its output voltage. This paper presents the dynamic model of zeta
converter. The converter is modeled using state-space averaging (SSA) technique. Full-state feedback controller is implemented on
the converter to regulate the output voltage. The simulation results are presented to verify the accuracy of the modeling and the
steady-state performance subjected to input and load disturbances.
Index Terms: Modeling, Zeta converter, SSA technique, Full-state feedback controller
-----------------------------------------------------------------------***----------------------------------------------------------------------1. INTRODUCTION
Nowadays, dc-dc converter is widely used as a power supply
in electronic system. In the battery-operated portable devices,
when not connected to the AC mains, the battery provides an
input voltage to the converter, which then converts it into the
output voltage suitable for use by the electronic load. The
battery voltage can vary over a wide range, depending on a
charge level. At the low charge level, it may drop below the
load voltage. Hence, to continue supplying the constant load
voltage over the entire battery voltage range, the converter
must be able to work in both buck and boost modes. The dc-dc
converters that meet this operational requirement are buckboost, Cuk, sepic, and zeta converters. For this paper, zeta
converter is selected because it has given the least attention.
Zeta converter is fourth order dc-dc converters that can stepup or step-down the input voltage. The converter is made up
of two inductors and two capacitors. Modeling plays an
important role to provide an inside view of the converters
behavior. Besides that, it provides information for the design
of the compensator. The most common modeling method for
the converter is state-space averaging technique (SSA). It
provides a systematic way to model the converter which is a
matrix-based technique. This state-space approach is a timedomain model where the system is described by differential or
difference equation. It allows greatly simplified mathematical
representation of the systems which is vector-matrix
differential equation. This poses great advantage because it
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Volume: 02 Issue: 08 | Aug-2013, Available @ http://www.ijret.org
34
(7)
VO CA1BU EU
(8)
For the small signal analysis, the derivatives of the steadystate component are zero:
x X ~
x 0 ~
x ~
x
Switch open
(1)
(2)
Where A is n x n matrix, B is n x m matrix, C is m x n matrix
and E is m x m matrix. Take note that capital letter E is used
instead of commonly used capital letter D. This is because D
is reserved to represent duty cycle ratio (commonly used in
power electronics).
Switch closed
(6)
~
~
~
x A1 D d A2 1 D d
X ~x B D d~ B 1 D d~U u~
1
x A1 x B1u
vO C1 x E1u
or in simplified form,
~
~
x A~
x Bu~ A1 A2 X B1 B2 U d
x A2 x B2u
vO C2 x E2u
(9)
For switch closed for the time dT and open for (1-d)T, the
weighted average of the equations are:
~
v~O C1d C2 1 d ~x E1d E2 1 d u~ C1 C2 X E1 E2 U d
or in simplified form,
x A1d A2 1 d x B1d B2 1 d u
(3)
vO C1d C2 1 d x E1d E2 1 d u
(4)
~
v~O C~x Eu~ C1 C2 X E1 E2 U d
(10)
TECHNIQUE
The schematic of zeta converter is presented in Fig -1. The
converter presented here is a dynamic model where they
consist of Equivalent Series Resistance (ESR) at both
capacitors and DC Resistance (DCR) at both inductors.
Basically the converter are operated in two-states; ON-state (Q
turns on) and OFF-state (Q turns off). When Q is turning on
(ON-state), the diode is off. This is shown as an open circuit
(for diode) and short circuit (for Q) in Fig -2. During this state,
inductor L1 and L2 are in charging phase. These mean that the
inductor current iL1 and iL2 increase linearly. When Q is
turning off (OFF-state), the diode is on. Opposite to previous
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Volume: 02 Issue: 08 | Aug-2013, Available @ http://www.ijret.org
35
1 D 2 R 1 rL 2
2 Df
L2
rC1D
R1 D
1 D R 1 rL2
2f
Fig -4: iL1 (left) and iL2 (right) waveform in CCM [3]
diL1
rL1iL1 vS
dt
Or
v
diL1
r
L1 iL1 S
dt
L1
L1
(11)
r R
r R
diL 2
R
rL 2 rC1 C 2 iL 2 vC1
vC 2 vS C 2 iZ
dt
rC 2 R
rC 2 R
rC 2 R
Or
r R
rC 2 R
diL 2
1
1
R
1
rL 2 rC1 C 2 iL 2 vC1
vC 2 vS
iZ
dt
L2
rC 2 R
L2
L2 rC 2 R
L2
L2 rC 2 R
(12)
iC1 C1
dvC1
iL 2
dt
dvC1
1
iL 2
C1
Or dt
(13)
dvC 2
R
1
R
iL 2
vC 2
iZ
dt
rC 2 R
rC 2 R
rC 2 R
Or
dvC 2
R
1
R
iL 2
vC 2
iZ
dt
C2 rC 2 R
C2 rC 2 R
C2 rC 2 R
(14)
rC 2 R
r R
R
iL 2
vC 2 C 2 iZ
rC 2 R
rC 2 R
rC 2 R
(15)
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Volume: 02 Issue: 08 | Aug-2013, Available @ http://www.ijret.org
36
1
L2
r R
rL 2 rC1 C 2
rC 2 R
C1
R
C 2 rC 2 R
1
L2
0
0
L
R
i L1 1
1
L2 rC 2 R i L 2
L
v
C1
0
0
vC 2
0
1
C 2 rC 2 R
0
rC 2 R
v S
L2 rC 2 R
iZ
0
C 2 rC 2 R
0
rC 2 R
vO 0
rC 2 R
iL1
rC 2 R vS
R iL 2
v 0
rC 2 R C1
rC 2 R iZ
vC 2
A1
0
1
L
1
1
B1 L
2
0
C1 0
1
L2
r R
rL 2 rC1 C 2
r
C2 R
C1
R
C 2 rC 2 R
0
1
L2
0
0
L2 rC 2 R
C 2 rC 2 R
r R
r R
di
R
vL 2 L2 L 2 rL 2 C 2 iL 2
vC 2 C 2 iZ
dt
r
R
r
R
r
C2
C2
C2 R
Or
r R
rC 2 R
diL 2
1
R
rL 2 C 2 iL 2
vC 2
iZ (17)
dt
L2
rC 2 R
L2 rC 2 R
L2 rC 2 R
Current through capacitor C1 can be written as:
iC1 C1
dvC1 1
iL1
dt
C1
iC 2 C2
dvC 2
R
R
iL 2
iZ
dt
rC 2 R
rC 2 R
Or
dvC 2
R
1
R
iL 2
vC 2
iZ (19)
dt
C2 rC 2 R
C2 rC 2 R
C2 rC 2 R
rC 2 R
r R
R
iL 2
vC 2 C 2 iZ
rC 2 R
rC 2 R
rC 2 R
(20)
rC 2 R
r R
E1 0 C 2
rC 2 R
L
iL1 1
1
L2 rC 2 R iL 2
L2
vC1 0
0
vC 2
0
1
C2 rC 2 R
0
rC 2 R
v S
L2 rC 2 R
iZ
0
C2 rC 2 R
0
vL1 L1
(18)
rC 2 R
L2 rC 2 R
C 2 rC 2 R
dvC1
iL1
dt
Or
rC 2 R
rC 2 R
vO 0
diL1
rC1 rL1 iL1 vC1
dt
Or
diL1
1
1
rC1 rL1 iL1 vC1
dt
L1
L1
rC 2 R
rC 2 R
iL1
r R v
R iL 2
0
0 C 2 S
rC 2 R vC1
rC 2 R iZ
vC 2
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37
rL 2 C 2
L2
rC 2 R
A2
1
C1
R
0
C 2 rC 2 R
0
B2
0
0
rC 2 R
L2 rC 2 R
C 2 rC 2 R
C 2 0
rC 2 R
rC 2 R
L2 rC 2 R
C 2 rC 2 R
1
L1
0
0
0
D
L
1
D
BS
L2
0
0
0
R rL 2 DrC1 rC 2 R
L2 rC 2 R
D
C1
R
C 2 rC 2 R
1 D
L1
D
L2
0
0
D
L
1
D
B B1D B2 (1 D) L2
0
rC 2 R
L2 rC 2 R
C2 rC 2 R
C C1 D C 2 (1 D) 0
rC 2 R
rC 2 R
L2 rC 2 R
C 2 rC 2 R
0
E E S
rC 2 R
r R
E E1 D E2 (1 D) 0 C 2
r
C2 R
r R
E Z 0 C 2
rC 2 R
Thus,
r R
E Z C 2
rC 2 R
E S 0
rC 2 R
L r R
BZ 2 C 2
0
C2 rC 2 R
Also,
A A1D A2 1 D
rC 2
rC 2 R
L2 rC 2 R
C2 rC 2 R
0
Thus,
rC 2 R
D
L
1
D
BZ L2
0
B BS
r R
E 2 0 C 2
rC 2 R
rC1 (1 D) rL1
L1
A
1 D
C1
(21)
1
(22)
D
VO VS
2
1 D rL 2 rC1 D rL1 D
1 R R 1 D R 1 D
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Volume: 02 Issue: 08 | Aug-2013, Available @ http://www.ijret.org
38
~
~
x A~
x Bu~ A1 A2 A1 BU B1 B2 U d
Or
(23)
~
~
x A~
x Bu~ Bd d
Where,
Bd A1 A2 A1 BU B1 B2 U
L 1 D R rL 2 DrC1 VS DrL1 RI Z
1
1 1 D R r V r 1 D Dr RI
1
L2
S
C1
L1
Z
Bd
L1
2
r
r D rL1 D
2
1
R1 D 1 L 2 C1
DV
R
1
D
I
S
Z
R
R 1 D R 1 D
C1
(24)
Equation (10) is recalled, the small signal output equation is
written as
~
v~O C~x Eu~ C1 C2 X E1 E2 U d
(25)
FEEDBACK
CONTROLLER
(FSFBC)
For a system that is completely controllable and where all the
states are accessible, feedback of all of the states through a
gain matrix can be used. The control law used for state
feedback is:
(26)
u Kx
Where K is the feedback gain matrix This type of compensator
is said to employ full-state feedback controller as presented in
Fig -5.
I A BK 0
(27)
s p1 s p2 s p3 s pn 0
(28)
u
Fig -5: Full-state feedback controller implementation
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39
J x T Qx u T Ru dt
0
PA A P PBR B P Q 0
T
K R 1 BT P
2.38 x10 3
0
A
2.55 x10 3
0
1.43x10 4
7.45 x10 3
4.49 x10 3
7.45 x10 3
1.2 x10 4
BZ
BS
2.55 x10 3
1.10 x10 4
0
0
0
3
5.08 x10
0
3
4.49 x10
ES
1.45 x10 4
0
2
1.60 x10
EZ 0 3.46 x10 1
3.50 x10 5
4.75 x10 5
Bd
3.36 x10 4
5. SIMULATION MODEL
Table -1 shows the parameters that are used for the zeta
converter circuit. By substituting all the parameters in the state
equations derived previously, the state matrices can be
gathered as presented. Also, the eigenvalues for the zeta
converter system can be calculated. Table -2 shows the pole
placement group. Poles 3x, Poles 5x and Poles 7x refer to the
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40
6. RESULTS
Table -5 shows the design requirement for the zeta converter.
The desired output is 24V when the disturbances are within
the allowable limit. Fig -9 to Fig -11 show the open-loop
response for the zeta converter without any disturbance. For
the open-loop, when subjected to input voltage disturbance of
vS=1V, the output increased significantly to approximately
27V (Fig -12). While for load current disturbance of iZ
=1A,
the output decreased to about 21.6V (Fig -13). This response
to disturbance is very undesirable.
Table -5: Zeta converter design requirement
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Volume: 02 Issue: 08 | Aug-2013, Available @ http://www.ijret.org
41
(a)
(b)
(b)
Fig -13: Open-loop output voltage, VO response to
disturbance iZ
=1A
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Volume: 02 Issue: 08 | Aug-2013, Available @ http://www.ijret.org
42
[5]
[6]
[7]
[8]
CONCLUSIONS
In this paper, modeling and control of a zeta converter
operating in Continuous Conduction Mode (CCM) has been
presented. The state-space averaging (SSA) technique was
applied to find the steady-state equations and small-signal
linear dynamic model of the converter. To ensure the output
voltage maintain at the desired voltage regulation requirement,
full-state observer and controller are used as the controller. To
compensate the output voltage from the input voltage and load
current disturbances, feedback controller gain for Poles 7x and
(iL22, 100vC22) is proven to produce the best compensated
output voltage for FSFBC based on pole placement and
optimal control technique, respectively.
[9]
[10]
[11]
ACKNOWLEDGEMENTS
The author would like to express gratitude to the Ministry of
Higher Education (MoHE) Malaysia and Universiti Teknikal
Malaysia Melaka (UTeM), Malaysia for the financial support.
REFERENCES
[2]
[3]
[4]
BIOGRAPHIES
AFFILIATION
[1]
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