CGL2 REVAMPING

Project
FileName

C 0004*

10Hz

ASR Proportional gain

KSP
ASR Integration constant
KSI

PLC I/F node number

Voltage control factor setting

KVOUT

0.1%

C 0008*

Motor rated frequency

FREQW

Rated slip frequency

FREQS
It* changing rate limiter
di/dt

0.1S

52ON TD
x 0.2s

0.2S

Run F/B TD
x 0.1s

1min

RAMP GENE
0100% changeable time

52 OFF TD
x 0.2s

( 0.2S )0.2S

0.01%

( 3 ):250kbps ( 0.4S )0.2S

Torque current limiter

(Positive side)

Iq ACR proportional gain

KCPQ1

Exciting current limiter

(Positive side)

Exciting current limiter

(Negative side)

Iq ACR integration constant

KCIQ1

Stall limitation
Positive limiter

Stall limitation
Negative limiter

0.01Times

5%

5%

Over speed detection level

OSPL

1%+100%

0.001S

For stall detection

Stop(70) level

bias
for voltage Ref.

0.1%

C 000A*

0.1mS

Over current detection level

OCL

bias
for voltage FB

5%

0.1

IM cooling FAN
stop TD

1min

ws comp. gain
KEDO

0.2%

Saturation comp. coefficient

Top gain

Speed differential output

delay time

Shaft vibration control

on speed level

10%

x1mS

*0.01Times+1.0Times

inverter capacity

5mS

0.1%

Current limiter rate at PLC DOWN ws comp. integration start level

1kVA

1%

Issued by

60mS

C 000B*

EMF voltage setting

KQLM

0.1%

Leak inductance l1+l2 '(Vq comp)

KQL1

0.1%

0.1%

0.1%

ACR/ASR switch
TD

0.1S

Averaging speed R I/O normal.

(N times)
Pulse width

Saturation comp.
FG gain 1
*0.01Times+1.0Times

Saturation comp.
FG speed level 1

0.5%

60mS

Local net
Gr . No.

Torque current limiter

(Positive side)

C 000F*

5%

Torque current limiter

(Negative side)

5%

Drooping
time-lag of first order

Iq operation
time-lag of first order

10mS

1mS

Saturation comp.
FG gain 2
*0.01Times+1.0Times

Saturation comp.
FG speed level 2

0.5%

ASR
time-lag of first order

KT1

0.1mS

PAGE

Measured by

10mS

EDONL

TD counter

(-1)%

Leak inductance l1+l2 '(Vd comp)

KQL12

0.01S

Shaft vibration control

differential gain

1%

Amount of ON DELAY
compensation second step

C 000E*

Shaft vibration control

comp. amount limiter

(-1)%

R1 Regulation setting
R1

)*5%+100%

Heavy fault detection

0.05Times

ON DELAY rate phase angle

The second step

upper limit

ACR/ASR switch
Rate of change limitation

0.1mS

1%

0.1mS

0.1%

0.05S

bias
for ON DELAY

ASR gain compensation

C 000D*

100S

ws comp.
full output speed

Ratio TOP/BASE speed

BASESP

0.5S

ws comp. integration constant bias for current FB detection

KEDI
DTSITAF

0.001Times

Secondary coil time constant

KT2,KT2FX

0.001S

Torque current limiter

(Negative side)

0.1%

Id ACR integration constant

KCID1

CAN transfer
Excitation
70 detection
rate
establishment TD
level

C 000C*

2%

30mS

0.1S

ws comp. proportional gain

KEDP

1%

0.1S

Exciting current setting

FLUX0

0.01Times

SUICIDE release
OFF TD

RAMP GENE
0100% limitation time

0.1S

ws comp.
start speed

70ON TD
x 0.1s

C 0007*

Id ACR proportional gain

KCPD1

0.1S

C 0009*

0.01Hz

C 0006*

ASR LEAD/LAG
COMP time-lag constant

REF-013

Date of issue

External light
fault TD

2mS

ASR LEAD/LAG
COMP time-lead constant.

0.1S

0.01Times

0.02S

Type

C 0005*

PLG/S/E output frequency at ratings RPM

FREQ0

Control constant setting table (3/9) [HMD93*]

Usage

COMMISSIONING TEST REPORT

Title

CGL2 REVAMPING

Project
FileName
*

Usage
C 0010*

FF comp. response delay

TREF

TNFF

5mS

FF current ref. delay

TFF

5mS

Single phase SW Pulse open-phase

1S

AO1 offset comp.value

0.01Times

AO1 100% output voltage

KAOS1

0.1V

AO2 offset comp.value

50mV

50mV

Overload integration
start level

C 0012*

1%+100%

AO1 100% output voltage

max.value AO1LIMF

AO1 100% output voltage

min.value AO1LIMR

Stall integration
start level

ON DELAYdecrease
start speed

ON DELAY
all off speed

ASR error limiter

Current F/B transmission

Filter time constant

Speed F/B transmission

Filter time constant

Taper control (first step)

Current limiter positive side

(-0.1)V

5%

10mS

Control constant setting table (4/9) [HMD93*]

Type

C 0011*

0.1V

FF ASR proportional gain

KSPFF

protection TD detection level

FF comp. incomplete integration

5mS

COMMISSIONING TEST REPORT

Title

5%

10mS

1%

1%

1%+100%

C 0013*

Overload
Curve No.
Stall
Curve No.

KBIFB
Overload light fault

detection level

10%

current F/B gain

0.001Times

stop ASR integral time constant Torque current limiter at stop

ITLIMF1
KSI1

20mS

ASR err limiter

rate of change

1%

ASR proportional gain at stop

KSP1

10mS

Taper control(first step)

Current limiter negative side

W1 * delay comp.
differential time constant

(-1)%-100%

0.1mS

0.01Times

W1 * delay comp. time-lag of

first order time constant

1mS

C 0014*
#1 Data address
(/
)

C 0015*
#2 Data address
(/
)

C 0016*
#3 Data address
(/
)

C 0017*
#4 Data address
(/
)

#1Upper limit
MSD polarity (+/-:0/1) + multiple( x 0.1 )

#2Upper limit
MSD polarity (+/-:0/1) + multiple( x 0.1 )

#3Upper limit
MSD polarity (+/-:0/1) + multiple( x 0.1 )

#4Upper limit
MSD polarity (+/-:0/1) + multiple( x 0.1 )

#1Lower limit
MSD polarity (+/-:0/1) + multiple( x 0.1 )

#2Lower limit
MSD polarity (+/-:0/1) + multiple( x 0.1 )

#3Lower limit
MSD polarity (+/-:0/1) + multiple( x 0.1 )

#4Lower limit
MSD polarity (+/-:0/1) + multiple( x 0.1 )

C 0018*
#5 Data address
(/
)

C 0019*
#6 Data address
(/
)

C 001A*
#7 Data address
(/
)

#5Upper limit
MSD polarity (+/-:0/1) + multiple( x 0.1 )

#6Upper limit
MSD polarity (+/-:0/1) + multiple( x 0.1 )

#7Upper limit
MSD polarity (+/-:0/1) + multiple( x 0.1 )

#5Lower limit
MSD polarity (+/-:0/1) + multiple( x 0.1 )

#6Lower limit
MSD polarity (+/-:0/1) + multiple( x 0.1 )

#7Lower limit
MSD polarity (+/-:0/1) + multiple( x 0.1 )

C
*

Stall taper speed 1

W1ST1

C 001B*

0.05%

Stall taper speed 2

W1ST2

0.05%

Stall taper torque curr. limiter Stall taper torque curr. limiter
(Positive side)ILIMSTF
(Negative side)ILIMSTR

1%

curr.F/B change level1

IFBCHL

2%

(-1)%

curr.F/B change level2

IFBCHH

2%

Stall taper limiter

time-lag of first order TDTAPER

1S

Measured by

Issued by

PAGE

Date of issue

REF-014

ASR P :KSP0(/8BCE) , ASR(FF) :KSPCOMP(/8C38) , FF ASR :KSPFF00(/919E) , ():LIMFLIM(/9296) , ():LIMRLIM(/9298)

Project

CGL2 REVAMPING

FileName
*

COMMISSIONING TEST REPORT

Title

Control constant setting table (5/9) [HMD93*]

Usage
C 001C*
#8 bit shift amount

Type

C 001D*
#10 bit shift amount

C 001E*
#12 bit shift amount

C 001F*

for emergency running

reference off TD TDREF70

0.5s

#8 data address
(/
)

#10 data address

(/
)

#12 data address

(/
)

#9 bit shift amount

#11 bit shift amount

#13 bit shift amount

#9 data address
(/
)

#11 data address

(/
)

#13 data address

(/
)

polarity
(1/0:-/+)

for emergency running

acc/dec rate EMGSTEP

1s

emergency running speed reference

EMGREF

1%

C
*

C
*

Speed notch filter 1

integral time constant

C 0020*

0.1mS

Speed notch filter 1

proportional gain

0.1Times

Speed notch filter 1

time lag constant

0.1mS

Speed notch filter2

integral time constant

Speed notch filter2

proportional gain

0.1mS

0.1Times

Speed notch filter 2

time lag constant

0.1mS

AO setting value 3CH

AOSETX3

AO setting address 4CH

AOADR4

AO setting value 4CH

AOSETX4

C 0021*

C 0022*

AO2 output data 100% value

NORM1
AO2 output voltage100% value

AO Tracer 16bit Use( V C00600 1bit OFF BAOTRC32=0 ) AO Tracer 16bit Use( V C00600 1bit OFF BAOTRC32=0 )

KAOS2

0.1V

Id ACR proportional cal.

IDACRONL
0.1%

0.1%

R1 Regulation setting

Id ACR lag time constant

0.1%

STOP(70)detect level

TVD1B

1mS

Id F/B differntial comp.gain

0.1%

Id ACR integral HOLD level

0.1%

0.6mS

Id F/B differntial comp.lag

time constant TVD1C

1mS

TVD2B

RIKALAG

1mS

Issued by

0.01S

generator comp.speed dead band level

WRDBL

1mS

Id F/B differntial comp.read

time constant TCD2C

0.1Times

generator comp.time lag constant

1mS

Id F/B differntial comp.lag

KIDLAG

KAGAIN

W1*bais

0.1%

generator comp.It* dead band generator comp.It* dead band

level H
ITSDBLH
level L
ITSDBLL

0.1%

0.1%

L/TD(filter)

W1BIAS

KIQQ

0.1%

0.1%

first second resistance(r1+r2')

R12Q

0.1%

calculation speed time lag constant

set(1-exp(-0.6/Tobs))10000
WRLAG

0.1mS

PAGE

Measured by

KIDD0

Id ACR read time constant

C 0023*

generator comp. gain

REF-015

Date of issue

AO setting address 3CH

AOADR3

R1 Regulation setting

IDOFFL

AO setting value 2CH

AOSETX2

AO Tracer 16bit Use( V C00600 1bit OFF BAOTRC32=0 ) AO Tracer 16bit Use( V C00600 1bit OFF BAOTRC32=0 )

C 0020*

SP70ONL0

AO setting address 2CH

AOADR2

C 0023*
AO2 Data address

AO Tracer 16bit Use( V C00600 1bit OFF BAOTRC32=0 ) AO Tracer 16bit Use( V C00600 1bit OFF BAOTRC32=0 )

(Vq comp) R1Q

C 0022*

AO setting value 1CH

AOSETX1

AO Tracer 16bit Use( V C00600 1bit OFF BAOTRC32=0 ) AO Tracer 16bit Use( V C00600 1bit OFF BAOTRC32=0 )

(Vd comp) R1D

C 0021*

AO setting address 1CH

AOADR1

CGL2 REVAMPING

Project
FileName

C 0028*

curr.phase switch start level

1mS

1%

Dr1comp.on level
DR1ONL

Dr1comp.gain

speed/ref. Change level H

WRCHH

Im variable amount
IMREF1

speed deviation differential comp.

1%

C 002C*
KCPD

0
KCID

0.01Times

0.001S
KCPQ

Id ACR proportional gain

Id ACR integration constant

Vd detect filter time constant Vq datect filter time constant

TVQ
TVD

0.1mS

detect level

bias for voltage detect

DTSIAV

1%

1%

1%

speed deviation differential comp.

differential time constant WIDD0

0.6mS

Iq initial set start speed level

WSH2

0.01%

C 002E*

C 002F*

E.Stop Base-SP1 speed change rate setting

VSTEPE2

1Unit

1%

1Unit

1%

Base-Top speed change rate setting

VSTEPT

1%

Iq initial set transform

coefficient
HK

0.01%

for calculation speed Iq ACR out lower limit

A1QRLL

EMF control reference

EQREF

0.1%

Iq initial set start speed level

WSH1

0-Base speed change rate setting

VSTEPB

EMF control proportional gain

KEQP

0.1Times

EMF control integral gain

KEQI

0.01S

0.001Times

AeqR integral time constant

KEDI2

5S

Issued by

Fixed Drooping 0
KDROOP0 x 0.1%/0.5%

0.01S

E.Stop SP1-Top speed change rate setting

VSTEPE3

0.01S

0.01S

E.Stop rate change SP1 setting

NRTCHG

0.01S

C 0032*

HOCL

Im*forcing lag time

constant KTDIMS

Im*forcing upper limit

IMSFX

HOCV

Fixed Drooping 1
KDROOP1 x 0.1%/0.5%

Fixed Drooping 2
KDROOP2 x 0.1%/0.5%

Fixed Drooping 3
KDROOP3 x 0.1%/0.5%

Fixed Drooping 4
KDROOP4 x 0.1%/0.5%

1mS

1%

1%

0.05S

1%

1%

C 0033*

Im*forcing differential time

constant KT2D

1%

0.01S

hardware over current detect level

0.001V
hardware over voltage detect level

0.001V

1%

1%

PAGE

Measured by

Im variable speed 2
IMWR2

0.1S

for calculation speed Iq ACR out upper limit

A1QRUL

AeqR proportional gain

KEDP2

0.1mS

Im variable speed 1
IMWR1

0.1S

EMF vlotage set low speed increase value

DKQLM

Taper limiter end speed

WTAPERE

1mS

10%

auto restart TD1

TDPATCH2

1mS

Taper limiter start speed

WTAPERS

Ed detect time lag constant

TDEDTB

lower linit

1%

auto restart TD1

TDPATCH1

15S

REF-016

Date of issue

1Times

1mS

FF ASR gain change bit shift

FFSHG

0.1%

EMF control out

1%

C 002B*

curr.phase change time lag constant

PHAILAG

E.Stop 0-Base speed change rate setting

VSTEPE1

0.1%

0.001Times

phase comp.time lag constant during restart

PHAILAG
change time x15

Motor quantity decrease A.B.

number adjust QTYNY

C 0031*

pulse absence phase pulse absence phase

1%

C 002A*

Motor quantity after change

QTYNX

1Unit

FF ASR gain change speed

FFCHSPL

cuur.limit at restart
PATCHLIMF

motor quantity
QTY1

0.5S

C 0030*

0.1mS

1%

C 002D*

0.001S

off level W1DOFFL

Exciting current ON TD

0.01Times

Motor voltage F/B gain

KVM

1%

1%

Iq ACR proportional gain

0.1%

Iq ACR integration constant

KCIQ

1S

ASROFFL

0.1%

speed/ref. Change level L

WRCHL

0.01%

52 OFF TD
TD52OFF

1%
ASR OFF level

Ws max.value
WSHMAX

0.1%

Iq F/B time lag constant

IFBLAG

Type

C 0029*

Id F/B differntial comp.

on level

Control constant setting table (6/9) [HMD93*]

Usage

COMMISSIONING TEST REPORT

Title

CGL2 REVAMPING

Project
FileName
*

COMMISSIONING TEST REPORT

Title
Usage

C 0034*

IdACROUT time-lag of first order

TDDACR

1ms

Torque Curr Limiter Upper

LIMFLIM

1%

Torque Curr Limiter Lower

LIMRLIM

1%

Type

C 0035*

DC Volt.FB Gain
KEDC1

Control constant setting table (7/9) [HMD93*]

C 0036*
TOP FLUX Setting
FLUX

0.001Times

DC Volt.Detect Filter time lag

TEFB

0.1%

SPX1 FLUX SETTING

FLUXX

0.1ms

DC Under Voltage Detect Level

EDCLL

C 0037*

0.1%

TopTerritory FLUX
SpeedSetting1SPX1
1%

0.1%

SpeedDeviation

IM Temp. Detect TD
TD25MW

( 3.0s )

Average

0.1s

C 0038*

C 0039*

C 003A*

C 003B*

C 003D*

C 003E*

C 003F*

Precedence Communication Abnrmality TD

TDIFER

50ms

C
*

C 003C*

Issued by

PAGE

Measured by

REF-017

Date of issue

Project

CGL2 REVAMPING

FileName
*

COMMISSIONING TEST REPORT

Title
Usage

Control constant setting table (8/9) [HMD93*]

Type

C0060*

C0061*

C0062*

C0063*

(Control Bit setting)

(Control Bit setting)

Blank

Blank

(Control Bit setting)

(Control Bit setting)

Blank

Blank

(Control Bit setting)

(Control Bit setting)

Blank

Blank

(Control Bit setting)

(Control Bit setting)

Blank

Blank

C0080*
AO set address 1CH
LAOADRX1
AO Tracer 32bit Use( V C00600 1bit ON BAOTRC32=1 )

C0081*
AO mask setting 1CH
LAOMSKX1 (Upper limit)
AO Tracer 32bit Use( V C00600 1bit ON BAOTRC32=1 )

C0082*
AO set address 2CH
LAOADRX2
AO Tracer 32bit Use( V C00600 1bit ON BAOTRC32=1 )

C0083*
AO mask setting 2CH
LAOMSKX2 (Upper limit)
AO Tracer 32bit Use( V C00600 1bit ON BAOTRC32=1 )

AO output set value 1CH

LAOSETX1
AO Tracer 32bit Use( V C00600 1bit ON BAOTRC32=1 )

AO mask setting 1CH

LAOMSKX1 (Lower limit)
AO Tracer 32bit Use( V C00600 1bit ON BAOTRC32=1 )

AO output set value 2CH

LAOSETX2
AO Tracer 32bit Use( V C00600 1bit ON BAOTRC32=1 )

AO mask setting 2CH

LAOMSKX2 (Lower limit)
AO Tracer 32bit Use( V C00600 1bit ON BAOTRC32=1 )

AO vias calculation value 1CH

LAOBIASX1 (Upper limit)
AO Tracer 32bit Use( V C00600 1bit ON BAOTRC32=1 )

Blank

AO vias calculation value2CH

LAOBIASX2 (Upper limit)
AO Tracer 32bit Use( V C00600 1bit ON BAOTRC32=1 )

Blank

AO vias calculation value 1CH

LAOBIASX1 (Lower limit)
AO Tracer 32bit Use( V C00600 1bit ON BAOTRC32=1 )

Blank

AO vias calculation value 2CH

LAOBIASX2 (Lower limit)
AO Tracer 32bit Use( V C00600 1bit ON BAOTRC32=1 )

Blank

C0084*
AO set address 3CH
LAOADRX3
AO Tracer 32bit Use( V C00600 1bit ON BAOTRC32=1 )

C0085*
AO mask setting 3CH
LAOMSKX3 (Upper limit)
AO Tracer 32bit Use( V C00600 1bit ON BAOTRC32=1 )

C0086*
AO set address 4CH
LAOADRX4
AO Tracer 32bit Use( V C00600 1bit ON BAOTRC32=1 )

C0087*
AO mask setting 4CH
LAOMSKX4 (Upper limit)
AO Tracer 32bit Use( V C00600 1bit ON BAOTRC32=1 )

AO output setting 3CH

LAOSETX3
AO Tracer 32bit Use( V C00600 1bit ON BAOTRC32=1 )

AO mask setting 3CH

LAOMSKX3 (Lower limit)
AO Tracer 32bit Use( V C00600 1bit ON BAOTRC32=1 )

AO output setting 4CH

LAOSETX4
AO Tracer 32bit Use( V C00600 1bit ON BAOTRC32=1 )

AO mask setting 4CH

LAOMSKX4 (Lower limit)
AO Tracer 32bit Use( V C00600 1bit ON BAOTRC32=1 )

AO vias calculation value 3CH

LAOBIASX3 (Upper limit)
AO Tracer 32bit Use( V C00600 1bit ON BAOTRC32=1 )

Blank

AO vias calculation value 4CH

LAOBIASX4 (Upper limit)
AO Tracer 32bit Use( V C00600 1bit ON BAOTRC32=1 )

Blank

AO vias calculation value 3CH

LAOBIASX3 (Lower limit)
AO Tracer 32bit Use( V C00600 1bit ON BAOTRC32=1 )

Blank

AO vias calculation value 4CH

LAOBIASX4 (Lower limit)
AO Tracer 32bit Use( V C00600 1bit ON BAOTRC32=1 )

Blank

C
*

C
*

Issued by

PAGE

Measured by

REF-018

Date of issue

Project

CGL2 REVAMPING

FileName
*

COMMISSIONING TEST REPORT

Title
Usage

C00E8*
Ethernet IP Address (Upper)

Control constant setting table (9/9) [HMD93*]

Type

C00E9*

C00EA*
Ethernet Subnet mask (Upper)

Ethernet IP Address (Lower)

C00EB*

Ethernet Subnet mask (Lower)

C
*

C00EC*
Ethernet Gateway (Upper)

C00ED*

C00EE*

C00EF*

Ethernet Gateway (Lower)

Issued by

PAGE

Measured by

REF-019

Date of issue