June 2012

Function coverage brief

by Allen.pan
panwenrong2003@163.com

contents
Function coverage brief .................................................................................................................... 1
by Allen.pan .............................................................................................................................. 1
1. What is function coverage................................................................................................. 1
1.1
What is the test point ............................................................................................ 1
1.2
The features of test points .................................................................................... 2
1.3
The methods to make test points ......................................................................... 2
2. Why we use function coverage ......................................................................................... 2
3. Who write function coverage ............................................................................................ 3
4. Where add function coverage ........................................................................................... 3
5. When verification engineer write function coverage ....................................................... 4
6. How to write function coverage ........................................................................................ 4
6.1
covergroup ............................................................................................................ 4
6.2
coverpoint ............................................................................................................. 5
6.3
bin ......................................................................................................................... 5
7. How much time to kill for function coverage .................................................................... 5
8. Summary ........................................................................................................................... 5

1. What is function coverage

Function coverage is come from the RTL information and design spec information, it
can reflect each test points and verification progress objectively, and the function
coverage is born for measuring the test point verification degree.

1.1 What is the test point

The test point is sometimes called the function point, all of the test points set is called
verification space, test point is the minimum segment of the RTL function and design spec,

June 2012

do an image of the parable: the test point is the atomic, RTL function and design spec is a
molecular, verification space is higher biological.

1.2 The features of test points

When we analyze the test points we must pay attention to these suggestions:
1 Certainty :Test points must be analyzed from RTL function and design
specifications;
2 Uniformity : Each test point in a medium size, dont appear one big test point
include multiple small test points;
3 Completeness: The test points description should include input data, process,
output data;
4 Readability: Using professional language descripts test point and don't create
ambiguity.
Test point doesnt focus on the accidental error of RTL and non-reasonable doubts.

1.3 The methods to make test points

The test points analyze methods generally have the following kinds:
1 Equivalence partitioning: According to class, for example: interface, function,
architecture and performance;
2 Boundary value : Focus on the test point boundary value, such as the lower
bound, upper bound, and random boundary;
3 Flow chart : Focus on the realization of the function of RTL process;
4 Error backstopping : According to the experience that may cause chip
mistakes;
5 Scene analysisAccording to the application of the chip scene analysis test
points.

2. Why we use function coverage

Once upon a time, theres no function coverage verification method, then it is very
difficult to measure verification. On the one hand verification engineers based on the RTL
code coverage and RTL state machines coverage, on the other hand the verification
engineers based on success rate of the test cases, the two aspects are difficult to affirm
all test points have been covered, everyone don't know when to say verification should
been done, so there is one sentence from old engineer: validation is everlasting.

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Spec

?
Verification

Design

Figure-1 Relations among SpecVerificationDesign

The relationships among spec, design and the verification just like the three circles
above, function coverage can let these three circles into one circle.

3. Who write function coverage

Verification engineer analyzes/writes/uses the function coverage module.
Design engineer check the function coverage module.
Project manager track the function coverage.
Systemverilog supports function coverage grammar in the language itself, verification
engineer would be feeling easier to study them, Questa and VCS have visual analysis
GUI and function coverage can be back annotated to documents such as doc and xml,
convenient design engineer checking and project manager tracking function coverage
over the whole chip.

4. Where add function coverage

Function coverage module are generally write to a separate file, the verification
method based on Systemverilog such as VMM and UVM write function coverage into an
independent class, which define members and tasks for collecting function coverage.
Function coverage can be triggered by event, but its not be done in this way usually,
verification engineers are often suggested that function coverage be declare in the
reference model, and reference models method call methods of the function coverage
module to collect function coverage.
In fact not just in the reference model add function cover, as the chart shows, the
function coverage nearly can be added to any places, but it is strongly recommended that
using reference model for the main function coverage collection.

June 2012
scenaro coverage

protocal coverage

transaction coverage

env

sequencer

driver

monitor

agent

RM

scoreboard

RAL

monitor

agent

DUT

assertion state coverage

Figure-2 where can add function coverage

5. When verification engineer write function coverage

Writing function coverage throughout the whole verification work, it is a very important
link, the starting point is preliminary verification environment completed, which provide
design engineer to test some easy functions. The primary environment is called sanity
testbench and verification engineer also provide design engineer a test case which is
called sanity test case, the sanity test case should guarantee the RTL registers, memory
and the various input/output interface can be triggered, sanity test case can detect the
most basic function of RTL. Design engineer use these components to do preliminary test.
When the above things being done, the main energies of the verification engineer
should be throw into the work of analyzing and writing functional coverage.

6. How to write function coverage

Base on the function coverage of the Systemverilog, we should need to understand
the three basic concepts.

commnetdetail content refer toIEEE Standard for SystemVerilog

6.1 covergroup
Covergroup corresponds to the test point, the relationship is one-to-one usually, that
is one covergroup corresponds to one test point, covergroup be composed by
coverpoints.

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Figure-3 covergroup

6.2 coverpoint
Coverpoint be concerned by test points, the covergourp and coverpoint can be
one-to-one or one-to-many relationship, such as a test point: when A send ten
back-to-back packets to B continuous, then B will send back pressure signal to A and B, in
this example, the number of packet is one coverpoint, the range between packets is one
coverpoint and the back pressure signal is one coverpoint, finally these coverpoint should
be crossed to ensure cross validation of space can be overwritten to.

6.3 bin
Bin is the scope of the coverpoint, for the above example, the number of packets sent
to the B can do a range of constraints, which is bin.

7. How much time to kill for function coverage

The benefits of function coverage cant be seen in pre-verification, verification
engineer is difficult to write test cases and high-quality functional coverage at the same
time, but in post-verification we will clearly feel the benefits of function coverage.
We can write less test cases, construct a random situation as far as possible to hit
each test point, and then measure the test point by the function coverage, to write some
more targeted test cases for those test points which difficult to cover. Such method is
closer to the scene of reality chip (chip power-down is generally not occur in use, so if one
test case can cover all test points, then that is the closest to the reality of the scene) and
verification engineer is drawn out from the status of writing test cases endless, they pay
more attention to the functionality of the chip.

8. Summary
Verification engineers subjective factors influence the quality of the function
coverage, meanwhile RTL design scheme and chip spec have a great impact for
verification engineer, so must ensure that the RTL design scheme and chip spec are clear
enough, and the information passed to verification engineer is sufficient.

June 2012

Function coverage can't solve all problems; it is only one measure method for
verification. If someone wants a full range to guarantee chip quality then must use more
verification methods.