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6-1
CHUNG-YU WU
+VDD
RS
M1
Vi
Vi
Cgs1
Vo
CX
gds1
-gmb1 Vo
gm1(Vi-Vo)
Zi
Vo
gds2
Cdb2
Csb1
CL
Zo
M2
VBIAS
-VSS
AV(s)
Vo(s)
=
Vi(s)
Rs(C gs 1 CL eq
sC gs1 + g m1
g
+ Cgs1 Cgd 1 + Cgd 1C Leq )s 2 + ( m1 RsC gd1 + C Leq + C gs1 )s + g m1 / 1 + G Leq
1
G Leq + g m1 / 1
2( Cgs1 + C Leq )
LHP zero: fz =
In general,
* If
fpfz
gm1
2C gs1
CLeqCgs1
C Leq
G
1
= ( 1) + Leq , we have
Cgs1
1
gm1
fp = fz and Av(s)
C gs1
1 indep. of s.
Cgs1 + CLeq
1
Cx+Cgs1 =CLeq
G Leq
1
( 1) + g
1
m1
Zi(s)
6-2
CHUNG-YU WU
Cgs1 s + g m1
Vi (s ) 1
=
+
(C gd1 s)
Ii( s) C gs1s Cgs1 s( G Leq + g mb 1 + sC Leq )
||
C gs1 C Leq2
Thus oscillation is possible.
* If gmb1 +GLeq is neglected, the equivalent input capacitances
||
Cin=Cgd1 Cin'
Cin' CLeq
C
g
Leq + 1 + m1
C
C gs1s
gs1
For large gm1, Cin 'CLeq
The large load capacitance CL is well blocked or buffered from the preceding stage.
Zo(s)
Vo(s )
Io(s )
|Vi=0 =
* If s = 0, Zo = Ro =
1
g m1 + g mb 1
R s Cgd 1s + 1
R s ( C gd1s + Cgs1 s) + 1
1
, we have
g m1 + g mb 1
1
and Cgs1 >>Cgd1
G Leq + g m1
6-3
CHUNG-YU WU
|Zo|
Rs
1 /gm1
R s C gs1 s + 1
g m 1 / 1 + C gs1 s
R1 =Rs
L
R1
1
g m1
Zo
R2
1
g m1
C
L= gs1 1 (Rs 1 )
g m1
g m1
R2 =
RS
Vo
RS
M1
gmb2 Vo
gm2Vo
Cgs2
M2
V1
+
CL V_i
Cgd1
Cgs1
gm1V1
Cdb1
Csb2
Vi
-VSS
RS
V1
Cgd1
Vo
+
V
_i
Cgs1
gm1V1
GLeq
CLeq
CL
gds2
Vo
gds1
6-4
CHUNG-YU WU
Vo
RS
Vin
GLeq
Cin
(gm1-sC gd1 )V1
Gs (sC gd1 g m1 )
(sC in + Gs )[s(C Leq + Cgd 1 ) + C Leq ]
1
)Cgd 1 s
Cgs1 + (1 + g m1
G Leq
1+
(C gd1 + C Leq )s
G Leq
Zin Cgs1 s
1
1
C (1 + g
+
C Leqs)
m
gd1s
G Leq G Leq
||
If
1
1
1
( Cgd1 + CLeq )s <<1 and
Cgds1 s (1+gm
),
G Leq
G Leq
G Leq
CLeq+Cgd1
6-5
CHUNG-YU WU
Cdb2
+VDD
V1 Cgd1
RS
M3
Vin
Vo
VBIAS
M2
CL
RS
Vin
M1
Cdb1
gm1V1
Cgs1
RS
-gm2V2
Cgs2 +
Csb2
rds1
V1
C2
(gm1-sCgd1)V1
1/g2
gm2V2
gm1
) Cgd1
g m2
C 2 = C gd1 + C db1 + C gs2 + C sb 2
C 2 = Cgs1 + (1 +
Gs g m 2 ( sC gd 1 g m 1 )
(sC 1 + G s )(sC 2 + g 2 )( sC Leq + g m 3 )
RHP Zero: Sz =
g m1
Cgd1
gm3
Gs
g
; Sp 2 = 2 ; Sp 3 =
C Leq
C1
C2
usually is the dominant pole.
LHP Pole : Sp 1 =
Sp 1
f 3 dB
S p1
2
gm3V3
Cgd2
Csb3
CL
Vo
Vo
Vin
g2 = gm2 +
Cgs3
V2
C1
-VSS
+
V
_3
Gs
2C1
CLeq
1/gm3
6-6
CHUNG-YU WU
V1
Cgd2
gm2V1
gds2
Cgs2
M2
RS
RS
Vo
V1
Vin
M1
CL
Cdb2
Cgd1
Vo
gm1V1
Vin
Cgs1
gds1
Cdb1
-VSS
RS
Cgd1 + Cgd2
Vo
(gm1+ gm2)V1
Vin
Cgs1 + Cgs2
RS
GLeq
CLeq
V1
Vo
[g m 1+ g m 2-s(C gd1+Cgd2)]V1
Vin
GLeq
Cin
G Leq = g ds1 + g ds 2
Cin = Cgs1 + C gs 2 + (1 +
Av (s)
CLeq+Cgd1 +Cgd2
C Leq = Cdb 1 + C db 2 + C L
g m1 + g m 2
)( Cgd 1 + Cgd 2 )
G Leq
RHP Zero: Sz =
gm1 + gm2
Cgd 1 + Cgd 2
LHP Poleo: Sp 1 =
Sp 2 =
Gs
Cin
G Leq
C gd1 + C gd 2 + C Leq
CL
6-7
CHUNG-YU WU
Cgd1
+
1
V Cgs1
2 id
1
g V
2 m1 id
rds4 ||rds1 +
1
Vod
2
_
CLeq
_
CLeq CL + Cdb 4 + Cdb 1
+VDD
+VDD
M4
M3
VBIAS
VBIAS1
M4
1
V
2 id
CL
1
V
2 od
CL
M2
M1
M1
VBIAS2
-VSS
-VSS
Ad =
Vod
g m1
= H (s ) =
Vid
g ds 4 + g ds1
RHP Zero: f z =
Cgd 1
gm1
C Leq + Cgd1
1 + ( g + g )s
ds 4
ds1
gm1
2 Cgd1
fz >fp
|Ad|
-60db/Octave
g ds4 + g ds1
LHP Pole: f p =
2( Cdb 4 + Cdb1 + C L + C gd1 )
f u A0f p =
gm1
2 ( C db 4 + C db1 + C L + C gd1 )
fu fz
fp
6-8
CHUNG-YU WU
g ds 1 ( Vs Voc ) + Vs (
Vs [
C + Cdb 5 + Csb1
1
+ gd 5
s) g m1 ( Vic Vs ) Cgs1 s( Vic Vs ) = 0
2 rds5
2
1
1
+ ( Cgd 5 + C db5 + C sb1 )s + C gs1s ] = [ g ds 4 + sC M + sC gd1 ]Voc + (C gs1 s + C gd1 s) Vic
2 rds 5 2
Vs =
s + C gs1s
2r +
2
ds 5
+VDD
Vic
Cgd1
Voc
M4
VBIAS1
gm1(Vic-Vs)
Voc
gds1
gds4
CM
CL
M1
Vic
Cgs1
VS
VS
VBIAS2
2/gds5
2M5
CM=CL+Cdb4 +Cdb1
gmb1 is neglected
-VSS
C gd1 (
+ Cgs1 )s 2 + [(
+ C gs1 ) g m1
Voc
2
2
=
Cgd 5 + Cdb 5 + Csb1
C gd 5 + Cdb 5 + Csb1
Vic
(
+ Cgs1 )( C M + Cgd 1 )s 2 + [(
+ Cgs1 )
2
2
1
1
A c ( s) =
( g ds 4
C gd 5 + C db5 + Csb1
Solve the pole-zero position : 1 RHP zero, 1 LHP zero,2 LHP poles
fZR
fZL
fp1 fp2
dB Ad
fZR >> fZL
CM
(C gd5 +Cdb5 +Csb1 )/2
Ac
fp1
fZL
fp2
Load pole
CMRR
CMRR
degradation region
tail pole
6-9
CHUNG-YU WU
+VDD
M4
E
M3
CE
Load
M1
Vin
M2
Tail
Ro
g m 34
CE
Io
CS
-VSS
A0
s
1+
Wp1
Load path: A2 ( s) =
A0
(1 +
s
s
)(1 +
)
Wp 1
Wp 2
s
)
Wp 2
Ad ( s) = A1 (s ) As ( s) =
s
s
(1 +
)(1 +
)
Wp1
Wp 2
A0 ( 2 +
2 g m 34
= 2Wp 2
CE
Approximate analysis:
The dominant pole of Ad ( s) is Sp 1 =
Ad ( s)
sC Leq
g m1
+ ( g ds1 + g ds 4 )
g ds1 + g ds 4
(output pole)
CLeq
Vo
CLeq
g ds1
2g m 4
6 - 10
1
( ) + sC s
R0
sC Leq + ( g ds1 + g ds 4 )
CHUNG-YU WU
g ds1 + g ds 4
CLeq
1 1
( )
R 0 Cs
Ad
) is degradated by 20dB/decade at high frequency.
Ac
+VDD
Ml1
M l2
M g1
V1
Cd
M s1
gdsl+gdsi
CC
M i1
~
Mi2
vi1
gdsgl+gdsg2
V2
vi2
CL
M g2
M s2
VBIAS
-VSS
Without CC
SP 1 =
1
( g dsl + g dsi ) ,
Cd
SP 2 =
1
( g dsg1 + g dsg 2 )
CL
V2
V1
equivalent
circuit
g mi(vi1 -v i2)
=gmivd
CC
Cd
g dsl+gdsi
CL
g dsg1+gdsg2
gmg1+gmg2
vd vi 1 vi 2
6 - 11
CHUNG-YU WU
v2
vi1 vi 2
H(s ) =
+ g mi ( g mg1 + g mg 2 )R d Ro ( 1
=
sC C
)
g mg1 + g mg 2
where Ro
Sp1
1
g dsg1 + gdsg 2
1
'
Sz
'
Rd
Sp2
'
( g mg1 + gmg 2 ) RO Rd CC
gmg 1 + g mg 2
CC
1
g dsl + g dsi
CC ( g mg1 + g mg 2 )
CO CL + Cd C L + Cd CC
RHP Zero
gain
dB
RHP zero
f p1
'
fz
'
'
f p2
log(f)
phase
0
- 45 o
- 135 o
180 o
Feedforward effect on CC
How to solve this problem ?
If I C = ( gmg 1 + g mg 2 )Vd ,
C
I o = 0 and V2 = 0
A zero is formed.
IC
V1
V2
CC
Ro
Io
(gmg1+gmg2)v
6 - 12
CHUNG-YU WU
Unity Gain
Buffer
CC
V1
V2
CC
+
~ V
2
-
V1
V2
(g
mg 1
V1
+ Cd sV1 + ( V1 V2 )Cc s = 0
Rd
+ gmg 2 )V1 +
H( s ) =
=
Sp2
'
1
V2 + CL sV2 = 0
Ro
--------- (2)
V2
Vd
g mi( g mg1 + g mg 2 )
1 + s[RoCc + Rd ( Cd + Cc ) + Cc ( g mg1 + g mg2 )Ro Rd ] + ( Cc CL + Cd C L )Ro Rd s
S p1
'
--------- (1)
(g
mg 1
+ g mg 2 )Ro Rd Cc
Cc ( gmg 1 + gmg 2 )
C cC L + C d C L
(unchanged)
6 - 13
CHUNG-YU WU
Actual Circuits :
1
VDD
M1
VBIAS
M1
CC
CC
M2
V1
VDD
V2
M2
V1
V2
VBIAS or
connected to the
output
-VSS
-VSS
Cgs1
CC
V1
Rout
V2
Cout
CL+Cgd1
+
-
V2
-
Cgs1 may introduce a RHP zero. But usually this RHP zero is large.
Cgs1 is very small.
Rout (
g miVd +
If
1 1
)
g m1 gm 2
V1
1
1
+ Cd sV1 + ( V1 V2 )(
+
) 1 = 0
1
Rd
Cc s
+ Couts
Rout
1
Cout s
Rout
1
1
1
Cc s
+
Cc s
1
C c Rout s + 1
+
C
s
out
Rout
6 - 14
CHUNG-YU WU
The numerator of H ( s ) =
LHP Zero :
V2 ( s )
Vd ( s )
is g mi ( gmg 1 + g mg 2 )( Cc Rout s + 1 )
1
Cc Rout
If Rout is large , LHP Zero may form a pole-zero doublet with Sp1 or Sp2
very slow slew rate !!
If Rout is small , too large gm1 or gm2 is required.
(large area ,large power)
large Cout.
Freq. Resp.
H( s ) =
v2
can be solved.
vd
CC
V1
(g
mg 1
SP 2
SP 3
1
(unchanged)
+ g mg2 )Ro Rd Cc
(g
mg 1
+ g mg 2 )Cc
Cd CL + Cc C L + Cd Cc
Cd Cc + Cd CL + Cc CL
RC Cd CL Cc
g mg1 + g mg 2
LHP
Zero : SZ =
Cc [Rc (g mg1 + g mg 2 ) 1]
RHP
(unchanged)
RC
V2
6 - 15
CHUNG-YU WU
1. If RC =
1
1
or RC =
g mg1 + gmg 2
g m2
S Z
g m 2 : second-stage transconductance
S P 1 dominant pole Ad (s )
For >> S P1
Ad ( j ) =
Adm
A S
= do P1
s
+ 1 s + SP 1
S P1
Adm SP 1
A S
, Ad ( j ) = dm P1
j
At u , Ad ( j u ) = 1 u = Adm S P1 =
Large CL S P 2
gmg 1 + g mg 2
CL
SP2
C g + g mg 2
2 ~ 4, c mg 1
=2~4
u
CL
g mi
g mi
Cc
g mi
2 ~ 4 , C L C c stable
gmg 1 + gmg 2
Gain
dB
-6 dB/octave
1) NMOS Realization :
fu
0 dB
f p1
VDD
CC
MC
f p2
log(f)
-12 dB/octave
-VSS
V1
V2
phase
0o
- 45 o
- 90 o
log(f)
- 135 o
- 180 o
I DS
C W
2
= n ox
2( VDD V2 VTH )VDS VDS
2 L
I
RC = DS
VDS
=
V DS =0
6 - 16
CHUNG-YU WU
1
n Cox W
[2( VDD V2 VTH )]
2 L
RC
g mg 1
1
+ g mg 2
RCmax
RCmin
Nonlinear Rc
V2min
(negative)
0V
V2max
V2
1
1
(
)
gm 2 g mg1 + gmg 2
a.
b.
CC
c.
CC
CC
M cn
M cp
V2
V1
V1
-VSS
V2
V1
-VSS
I DSn =
R cn =
nCox Wn
2
[ 2( VDD V2 VTHn )VDS VDS ]
2 Ln
1
n C ox W n
[ 2 ( V DD V 2 V THn )]
2
Ln
V2
C W
2
I DSp = p ox p [ 2( V2 + VSS VTHp )VDS VDS ]
2 Lp
Rcp =
pCox Wp
[ 2( V2 + VSS VTHp )]
2 Lp
If
6 - 17
CHUNG-YU WU
p C ox W p
n C ox Wn
[ 2(V DD V2 VTHn )] +
[ 2( V2 + VSS VTHp )]
2 Ln
2 Lp
nCox Wn pCox W p
=
=
2 Ln
2 Lp
Rc = [ 2VDD 2VTHn + 2VSS 2VTHp ] nearly indep. Of V2
1
Rc
1
V 2 =0 V
= g mg1 + gmg 2
Rc-1
Rcn-1
V2min
2. If Rc =
Rcp-1
0V
V2max
V2
1 + ( Cd + CL ) / CC
g mg1 + gmg 2
6 - 18
CHUNG-YU WU
Vin
Vout
+
-A V2
Av 3 ( 0 )( 1 +
Av 3 =
(1 +
s
)
z3
s
)
P3
s
s
)( 1 + )
z1
z2
s
s
( 1 + )( 1 + )
P1
P2
Av 2 ( 0 )( 1
Av 2 =
1 LHP zero
1 LHP pole
2 LHP poles
1 RHP zero (C C)
1 LHP zero
6 - 19
CHUNG-YU WU
0. 1%V or 0.01%V
V
V Io g m1
TS
Slewing
Period
TP
TSET
Settling
Period
+ Input
- Stage
Io
differential-input
to single-ended
output converter
Gain
Stage
Vo
6 - 20
Slew rate:
CHUNG-YU WU
SR
dVo
I
|max = o
dt
Cc
u =
gmi
single-pole case
Cc
SR =
I o u
Io
= u
uC W
gmi
2 ox ( )i
2 L
g
I
1
ln[ 1 m 1 ( V o )
1
I o ao
g m1
Fig.2
a( s )
1 + a( s )
eq.(20)-(23)
two poles S = n 2 1 n
eq.(24)
1 + 2
2n
damping ratio
= 1 critically damped
< 1 underdamped
(complex conjugate poles)
=
gm 2 / c2
2
2
1 + 2
=
=
2 n
2 ao1 2 u 2 g m 1 / cc
> 1 overdamped
(real and negative pole)
(CC, C2 >> C1)
6 - 21
CHUNG-YU WU
=> CC
4(
g m1
)C2
gm 2
4 u 2 = 2 ~ 4
u
=> 2
max.overshoot: eq.(36)
settling time: eq.(40),(39)
Vo(t): eq.(41)
TSET : eq.(43)
V
0.001
TS
(3) Overdamped
underdamped
overdamped
TSET
TSET : eq.(47)
Further references:
(1) IEEE JSSC, vol. SC-18, pp.389-394, Aug. 1983
(2) IEEE JSSC, vol. SC-21, pp.478-483, June. 1986
6 - 22
CHUNG-YU WU
CC
Vout
=1
Vin
gm1Vin
Vout
CL
gmi
or CC = g mi / u
CC
max
= I o / CC =
IC u
Io
= u
gmi
2uC ox( W / L )i
u , I o ,( W / L )i SR
* I o / C L I o / CC or CL
dVout
dV
CC out ( = I o )
dt
dt
Vo
Vin
V1
degradation
enhancement
Vo
6 - 23
CHUNG-YU WU
off
M4
off
Io + iw
Io + iw
CC
-
vout
off
on
vw
M1
M2
Cw
Io
iw
CL
+
+
vin
-
V1
0
- VSS
i ( t ) = C
dv ( t )
dv ( t )
C in
dt
dt
t
1
I
C
vout ( t ) =
( I o + i )dt = o t +
CC 0
CC
CC
dvin
dt
dt
Io
C
t + V1u( t )
CC
CC
M3
on
Io + iw
Io - i w
CC
Io- iw
on
vw
M1
Cw
iw
off
+
M2
Io
- VSS
+
vin
-
V1
vout
6 - 24
vout v
CHUNG-YU WU
d
I i
dv
i
vout = o = =
dt
CC
dt
C
dvout
Io
=
dt
CC + C
i =
I oC
( CC + C )
slew degradation
Io
CL
CL
Vi
Vo
M6
M5
Io
Ip
VX
M1
off
M2
VY
Ip-Io
VBIAS2
M3
Ip
M4
V
Vs
VBIAS1
Io
Ip-Io
M7
M8
Io
VB
M9
M 10
- VSS
SR =
Io
CL
Vout
CL
6 - 25
CHUNG-YU WU
VBIAS1
M 11
VBIAS1
M12
M4
CC
Cgd
Vin
gain
stage
M1
M2
Cgs
Io
- VSS
CI
Vout
6 - 26
CHUNG-YU WU
Vout Cgs I o 1
V C
1 I o
+ GS 1 + gd
Io
-
-VSS
C
Vout
gd
CI
VDD
CI
Cgs
I o
1 C gs 1 I o
1 V 2 g + C 2 g
DD m3
I
m1 V DD
CI
VDD
M3
Cgd
M4
M6
CC
V1
Vi +
VBIAS
M1
M2
Vo
Rz
Vi -
M5
M7
- VSS
6 - 27
CHUNG-YU WU
Vo
Vi
* PSRR+
Vo
VDD
How to calculate
Vo
Vi
V
= io
VDD
Vo = 0
Vo
VDD V
Vo =0
=0
Vio
VDD
VDD
~ Vi
Vio
Vio
VSS
CC
V1
Rz =1/gm2
Go1
gm1Vio
Vio
Go2
gm2(V1-Vi )
C1
~
PSRR+ ( s )
s + Go 1Go 2 /( g m2 Cc )
s + g m1 / Cc
6 - 28
CHUNG-YU WU
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4) )
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4)
;
$
$D4?#D4
4) %2)
%2)
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8
2
2
$D?#D
"
8
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5
8
4
+ = = +
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2
2
8
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%
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5
8
4
"
8
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)3% $:% "$&&3
2
8
5
4
5
8
4
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4
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8
5 8 4
9
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!3!
,
5
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4
+ =
(
T
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+
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8-1
CHUNG-YU WU
+ GS1 + gd
V ss
C I V ss 2 g m1
Vss C I 2 g m3 V ss
P.6-26
Vout C gd
I o
1 C gs 1 I o
+
1
V DD
C I V DD 2 g m3 C I 2 g m1 V DD
If I o
==>
CI
V ss
V DD
Ref.: IEEE JSSC, vol. SC-15, pp.929-938, Dec. 1980
BIAS GENERATOR
OP AMP
+VDD
M9
M3
IREF
V+
V-
M10
M6
M4
M1
Vo
M2
Io
M8
M11
M12
M5
VBIAS
-VSS
M7
8-2
CHUNG-YU WU
*Tracking RC compensation
Conceptual circuits :
+VDD
+
VIN2
-
gm1VIN
+
Vos2
MB(M6)
Voltage
source
Mc
(M10)
CC
CL
MA (M8)
(RC)
KI
I
-VSS
In the quiescent case ,Vin2=VOS2
Cc
Cc + CL
Cc + CL
Rc
gm 2Cc
Cc
g m1
c 1c L
gm 2
8-3
CHUNG-YU WU
CMOS Design
+VDD
M1
M3
M5
VBIAS
M13
M8
M15
M9
M11
Vout
M6
Cc
M17
M2
M16
M7
M10
M14
M12
M4
-VSS
* M17,Cc : Tracking RC compensation.
* M9,M11:Sharing the separate n-well.
* VBIAS is not strictly independent of VDD and VSS.
8-1.2 Improved frequency compensation technique.
Ref.: IEEE JSSC ,vol.sc-18, pp 629-633, Dec.1983
Grounded gate cascode compensation
+VDD
M11
M5
2x
M12
M9
3x
VBIAS1
MB
+
M13
IBIAS
M1
VBIAS2
MC1
M16
M14
M15
M2
MC2
M4
M3
VBIAS1
M7
M8
3x
M10
3x
Cc
5pF
Vo
M6
8-4
CHUNG-YU WU
2Io
Cc
I1
A
_
gm1
-gm2
Vo
Vi
+
R1
CS2
R2
I1
-VSS
Net current in CC (C c
d
V ) enters the second stage.
dt o
M2
M1
M9
Vo
Rc
M1A
Cc
M2A
M7
M4A
M6
M3A
M4
M3
-VSS
M8
8-5
CHUNG-YU WU
M6
M7
OUT
Cc
M1 M3
M8
_
+
M9
M10
3. Cascoded CMOS OP AMP with high ac PSRR
Ref: (1) IEEE JSSC , vol. SC-19, pp.55-61, Feb. 1984
(2) IEEE JSSC , vol SC-19, pp. 919-925, Dec. 1984
1) Original version
+VDD
200/10
200/10
25/10
Mp3
Mp2
-VSS
Mp4
1125/10
A
Mp7
50/10
IBIAS
50/10
MN1
MN2
Mp5
100/10
Cc
Mp5
Vout
100/10
CL
5A
100/10
MN9
MN5
200/10
MN3
100/10
100/10
MN4
42.5/10
MN6
-VSS
Chrarcteristics:
VDD=VSS=2.5V
Input offset voltage
Supply current
Output voltage range
Input common mode range
CMRR @ 1KHz
Unity-gain frequency
Slew rate
5mV
100A
-VSS~VDD
-VSS+1.47V ~ VDD
99dB
1.0MHz
1.8 V/sec
42.5/10
MN8
MN7
500/10
8-6
CHUNG-YU WU
VBIAS1
M12
M6
M5
VBIAS2
M8
M3
M4
M13
-
Vout
+
Cc
M2
M1
VBIAS3
M14
M9
M11
M10
-VSS
VBIAS1
M8
M6
M5
M3
Vout
M4
Cc
M1
VBIAS2
M2
M5
-VSS
+
M9
* Good PSRR
* Reduced input common
range.
restrict its applications
to those which use a virtual
ground.
8-7
5.Single-stage cascode OTA
Ref.: IEEE JSSC , vol. SC-20 , pp.657~665 , June 1985
CHUNG-YU WU
+
T6
T2
T14
T8
T4
T12
In-
In+
T1
T3
T10
Out
CL
Io
T5
T9
T7
IBIAS
T11
T13
T15
T17
-
8-8
+VDD
M8
CHUNG-YU WU
M9
M5
M6
M13
M14
M7
M15
OUTPUT
M1
M2
M16
CL
M12
INPUT
IB1
M3
M11
M4
M10
-Vcc
TABLE I
Parameter
Measured Value
Unity-Gain
Bandwidth
DC-Open Circuit
Voltage Gain
DC-Power
Dissipation
25 A
50 A
100 A
50MHz
70MHz
100MHz
70dB
69dB
66dB
0.55mW
1.1mW
2.2mW
8-9
CHUNG-YU WU
+VDD
M8
M9
M6
M5
M17
M22
M13
M14
M18
M15
M7
M1
OUTPUT
CL
M2
M16
M12
INPUT
M19
IB1
M21
M11
M3
M4
M10
M20
-Vcc
+ VDD
VBIAS
Vout
Vin
- VSS
8 - 10
CHUNG-YU WU
MP
A
Vout
Vi
A
MN
- VSS
M16
C0
M8
M17
V OUT
M8A
M10
VBIASN
M9
A1
V IN
A2
M13
VBIASN
M12
M6A
-VSS
M11
8 - 11
*
CHUNG-YU WU
Vout
+
Vi
A1
M6
~
+ V DD
Vin V out
M 6 provides the negative feedback
A1 , M 6 and A2 , M 6 A form a class AB push-pull output stage.
I DM12 VGSM 8 A
VinA 2 +
and
Vout ,
i.e.
VCC
M4
M3
M6
MPC
CC
VIN
M1
VSS
M2
VBIASN
M5
VSS
VOUT
8 - 12
CHUNG-YU WU
VTHO1
VTH 1
+ VCC
MP3A
M3H
M4H
VIN
M16
M3
MP5
M4
MP3
C0
M9
M6
M8A
MRC
CC
M1
MRF
CF
M2
MP4A
M10
MN4
M5
M2A
M1A
MN3A
M8
M17
V BIASP
M5A
MP4
MN3
M5A
M13
M12 M11
MN5A
MN4A
M4A
M4HA
M3A
M3HA
V BIASN
- VSS
V OUT
88- -13
14
CHUNG-YU
CHUNG-YU
WU
WU
Simulation
Power dissipation( 5V )
Avol
Fu
Voffset
PSRR+(dc)
(1KHz)
PSRR-(dc)
(1KHz)
THD VIN=3.3Vp RL=300
CL=1000 pF
VIN=4.0Vp RL=15 k
CL=200 pF
Tsettling (0.1%)
Slew rate
1/f noise at 1KHz
Broad-band noise
Die area
7.0mW
82dB
500KHz
0.4mV
85dB
81dB
104dB
98dB
0.03%
0.08%
0.05%
0.16%
3.0us
0.8V/us
N/A
N/A
TABLE II
COMPONENT SIZES ( m, pF )
Measured
Results
5.0mW
83dB
420KHz
1mV
86dB
80dB
106dB
98dB
0.13%(1KHz)
0.32%(4KHz)
0.13%(1KHz)
0.20%(4KHz)
<5.0us
0.6V/us
130nV/Hz
49nV/Hz
1500mils2
MI6
MI7
M8
M1,M2
M3,M4
M3H,M4H
M5
M6
MRC
CC
M1A,M2A
M3A,M4A
M3HA,M4HA
M5A
M6A
MRF
CF
184/9
66/12
184/6
36/10
194/6
16/12
145/12
2647/6
48/10
11.0
88/12
196/6
10/12
229/12
2420/6
25/12
10.0
M8A
M13
M9
M10
M11
M12
MP3
MN3
MP4
MN4
MP5
MN3A
MP3A
MN4A
MP4A
MN5A
481/6
66/12
27/6
6/22
14/6
140/6
8/6
244/6
43/12
12/6
6/6
6/6
337/6
24/12
20/12
6/6
M5
M10
M11
M13
M1
M2
M8
M9
CC
M7
M3
M4
M6
M12
- VSS
8 - 15
*
CHUNG-YU WU
2 g m 6 g m8 g m13
C c g m6 g m13 + C 1 g m8 g m12
P1
g ds10 g o
g m13C c
LHP.
2
g g
g m8 (C O + C C )
g m8 (C c + C O )
m8 m13
P2 , P3
j
2C O C c
2
C
C
C O C1
O c
where
g o g ds12 + g ds13
C O = C L + C db12 + C db13
C1 = C gs13 + C db11 + C db 9 + C gd 9
Output stage
+ VDD
VBIAS
Vout
Vin
- VSS
1/ 2
8 - 16
8 - 17WU
CHUNG-YU
CHUNG-YU WU
+ V DD
A1
M1
Vin
Vout
A
- 2
M2
- VSS
M1 and M2 are turned off in the quiescent state by building a small offset
voltage into A1 and A2 M3-M6 control the output quiescent currents.
-AMP 1
M15
+
error amp.
M3
M5
M4
M6
Vos
VIN
+
AMP 2
M17
error amp.
- VSS
8 - 18
CHUNG-YU WU
+ VDD
M4
M6
M15
M13
M1
Vout
M2
M7
M14
M15
CC
M8
M5
- VSS
M13, M14 and M15 form a circuit to turn off M15 when Vout < VTP13
(negative)
Cc : compensation.
Z1
P1
g m7 + g mbs 7
Cc + Cgs 7
gL
C L + CC
g m15
g ds 6
1
2
g m 7 g ds6 (C L + Cc m15 )
2
g (C + C L )
g (C + CL )
g ds 6
j
m 7 c
P2 , P3 m 7 c
2Cc C L
C cC L C1
2C cC L
C1 = C gs 9 + Cdb 6 + Cdb 7 + C gd 7
where
8 - 19
+ V DD
CHUNG-YU WU
M L7
ML3
BIAS4
C C3
M5
M10
M L10
M11
ML11
M L6
BIAS3
M12
M H4
MH5
M15
M1
M2
M14
M L1
M L9
M8
M9
ML2
MH8
CC1
M H9
MH1
M H2
ML8
M16
M 17
M7
MH10
M3
M4
M6
MH6
BIAS2
M 13
MH11
BIAS1
M H3
- VSS
C C2
MH7
ML4
ML5
400/15
400/15
150/10
150/10
100/15
150/10
150/10
300/5
300/5
300/10
300/10
1200/10
600/10
200/5
200/5
600/6
600/6
MH1
MH2
MH3
MH4
MH5
MH6
MH7
MH8
MH9
MH10
MH11
Cc1
Cc2
Cc3
48/10
50/10
500/15
300/6
300/6
200/5
250/15
700/6
15/6
10/15
20/15
20pf
4pf
4pf
ML1
ML2
ML3
ML4
ML5
ML6
ML7
ML8
ML9
ML10
ML11
48/6
50/6
300/15
150/5
100/5
300/6
100/15
400/5
5/5
5/15
15/15
8 - 20
TABLE II
POWER AMPLIFIER PERFORMANCE SUMMARY
(First Revision)
parameter
Measured Results
Supplies
5V
Open-Loop Gain
93dB
Bandwidth
1.2MHz
Power Dissipation
12.7 mW
1.76mW
3.1V
PSRR+ at DC
93dB
PSRR-
kHz
91dB
10
kHz
76dB
100
kHz
60dB
at DC
102dB
kHz
89dB
10
kHz
75dB
100
kHz
53dB
Slew Rate
Input Common Mode Range
1.5V/s
+3.3V
-5.5V
1000 mils2
-73dB
HD3
-78dB
CHUNG-YU WU
8 - 21
CHUNG-YU WU
Bias stage
+ V DD
VDD
MX5
MA1 M A4
MX1
MB1
A
V B1
Vin+
MA2 MA3
Vout
Vin-
M A5
M B2
VB1
M X2
MR1
V B2
V B3
MX7
MX3
CL
MX8
MR1
V B2
M B3
VB3
MX6
MB4
MX4
- VSS
V SS
TABLE I
TRANSISTORS DIMENSIONS
TRANSISTOR
MX1, MX5
W (m)
225
L (m)
3
MX2
MX3
MX4, MX6
MR1
MA1, MA4
MA2, MA3
MA5
MX7
MX8
75
30
90
6
45
450
36
600
240
3
3
3
21
3
3
3
3
3
8 - 22
Provide a low-impedance level at node A and B. CHUNG-YU WU
The low-order poles created by the Miller cap. of MX7 and MX8 can be
avoid
*
If Vin << 0
MX3-MX6 are turned off and MX1 and MX2 are on
Node A has a high voltage MX7 off.
VB = VA because of MR1 MX8 on.
In the bias circuit, MR2 MR1, MB1 MX1, MB2 MX2, MB3 MX3, MB4
MX4.
In the quiescent case, VGSMX1 VGSMX7 and VGSMX4 VGSMX8
The current in MB1 and MB4 controls that in MX1 and MX4 and MX7 and MX8.
Characteristics:
3 m CMOS area: 100mils2.
CL 100pF and RL 10 k
: stable.
CL=5000pF f 100kHz.
TABLE II
BUFFERS PERFORMANCE
PARAMETER
MEASURED VALUE
SPICE
Supply Voltage
2.5 V
2.5 V
Supply Current
Voffset
Voltage Gain
F3dB (CL=100pF)
Gain Peaking
RoCL
CMRR
Input CM Range
SR (CL=5nF)
285 A
< 10 mV
+ 1.00 V/V
6 MHz
0.4 dB
270 A
5 mV
+ 1.00 V/V
8 MHz
0
330
80 dB
270
84 dB
1.8 V
0.9 V/s
1.7 V
1.0 V/s
3.9 s
4 s
8 - 23
CHUNG-YU WU
NA
270 V / H Z
F = 50 kHz
NA
70 V / H Z
1.
a. CDS method
VIN
Vn 2
Vn2
+
VOUT
S/H
f
V neq12
VIN
V neq12
VOUT
Noise reduction
8 - 24
CHUNG-YU WU
Vn2
SIN
+1
f
-1
f
Vn2
+
VIN
a1
a2
VOUT
Signal
f
Noise
Vneq 2
+
VIN
a1
a2
VOUT
Vneq 2
If the chopper frequency is much higher than the signal bandwidth, the 1/f
noise in the signal band will be greatly reduced.
Example: Fully differential class AB chopper stabilized OP AMP with DCMFB circuit.
Major advantage of fully differential OP AMPs:
1. Improvement of PSRR
2. Improvement of dynamic range
3. double the output swing
4. Reduction on the sensitivity to clock and supply noise.
Disadvantage:
M29
M9
M13
M25
M17
V+
M14
M10
M22
M21
M5
M43
M1
M2
M30
M18
M26
M44
M6
M46
M45
V-
Vo+
M7
M33
M3
M4
Vo-
M8
M48
M47
M39
M49
M35
M50
M53
C3
C2
M56
M55
M19
M41
M37
C4
M20
M28
M27
M24
M23
M31
M36
M54
C1
Vcm-
M40
M52
M51
V df
M34
M15
M16
M11 M12
M32
M38
M42
- VSS
Device
W(um)
L(um)
Device
W(um)
L(um)
M1
25
M19
3.5
M2
25
M20
3.5
M3
M4
25
25
3
3
M21
M22
17.5
17.5
3.5
3.5
M5
25
M23
3.5
M6
25
M24
3.5
8 - 25
CHUNG-YU WU
M7
25
M25
3.5
3.5
M8
25
M26
3.5
3.5
8 - 26
CHUNG-YU WU
M9
10
3.5
M27
M10
10
3.5
M28
M11
3.5
M29
12
3.5
M12
3.5
M30
12
3.5
M13
17.5
3.5
M31
16
3.5
M14
17.5
3.5
M32
18
3.5
M15
3.5
M33-M34
M16
3.5
M55
M17
17.5
3.5
M56
M18
17.5
3.5
2.
+VDD
IO
IO
IO
CC
M2
Vin
+VDD
VBIAS
V
+ O
CL
-
CGS
Vin
M1
-VSS
CL
M2
M1
CP
-VSS
TWO-STAGE
SINGLE-STAGE
CASCODE
1
ro C c g m ro
1
ro C L g m ro
Nondominant
pole location
gm
CL
gm
Cp
In general, the higher the 2nd pole frequency, the faster the settling response.
Single-stage cascode amp. has a faster settling behavior.
+VDD
VBIAS
+
Vin
-V
out +
CL
CL
CMFB
-V SS
CMFB: Common-mode feedback circuitry
3.
+VDD
M11
M17
M20
M14
BIAS3
BIAS1
M5
M1
M2
M6
Iin(+)
I in(-)
OUT(+)
OUT(-)
M7
M19
M18
M16
BIAS4
M8
M3
I1 I2
M4
I
I
M10
M9
A
BIAS2
M15
M13
-VSS
8 - 27
CHUNG-YU WU
+V DD
M17
M12
BIAS3
M20
I2
M5
M1
Iin(+)
M6
Iin (-)
OUT(-)
OUT(+)
4A
M4
M7
class AB
3A
class A
1A
-200
BIAS2
I2
2A
-400
M8
200mV 400mV
I
M9
V in
1A
M15
M13
2A
-VSS
Active portion of the amplifier for a positive input signal.
M14
M12
M17
M20
M22
M27
M26
M5
M1
M2
Iin(+)
OUT(+)
M19
OUT(-)
M8
I2 I1
M3
M24
M6
Iin(-)
M7
M16
M4
M30
M15
M 60A
M18
M25
M10
M21
M13
M9
-VSS
8 - 28
CHUNG-YU WU
OUT
I30
M30
M 15
40
10
10
10
I9
M9
M 13
40
10
40
10
- VSS
If I 9 = I 30 , VGS 9 = VGS13 = VGS15
V DS13 = VGS 30 V GS9
Set VDG13 = VTH VGS 30 = 2VGS 9 VTH
Design (
W
)30 , such that VGS 30 = 2VGS 9 VTH
L
DEVICE
Z(m)
L(m)
M1
180
M2
180
M3
140
M4
M5
140
150
6
6
M6
150
M7
200
M8
200
M9
22
10
M10
22
10
8 - 29
CHUNG-YU WU
M11
29
M12
29
M13
22
10
M14
29
M15
22
M16
29
M17
29
M18
22
10
M19
22
M20
29
M21
20
M22
12
M23
28
M24
14
M25
20
M26
12
M27
28
M30
14
AMPLIFIER SPECIFICATIONS
CORE AMPLIFIER SPECIFICATIONS
(0-5 Volts Supply)
100W Quiescent Power Dissipation
DIFFERENTIAL GAIN
>10.000
2 MHz
NOISE
OUTPUT SWING
AREA
300 mils 2
8 - 30
CHUNG-YU WU
4.
100A
M16
Vin -
MC1 MC2
Vout+
BIAS
M2
M8
MC5
M6
BIAS
MC7
M19
MC12 MC11
Vout-
M5
M3
M14
100A
Vin+
M1
M7
BIAS
MC6
M17
BIAS
M20
MC4
M15
5 A
M10
MC15 MC14
M4
BIAS
5 A
M9
M12
BIAS
M13
MC17
M11
- VSS
Characteristics:
Technology
: 1180
unity-gain freq
CMRR
: 61db
Area
: 290 mils2
power supply
: 10Mhez
: 5V
MC16
8 - 31
CHUNG-YU WU
Vo
Vref
+
Aadd
Vi
Cload
M2
M1
-VSS
Rout = [g m 2 ro2 ( Aadd + 1) + 1]ro1 + ro 2
Atot = g m1ro1 [g m 2 ro 2 ( Aadd + 1) + 1]
Aorig = g m1 g m2 ro1ro 2
2) Repetitive implementation of gain enhancement
+VDD
Vo
M2
M1
M6
M4
M5
M3
Vi
-VSS
2.High-frequency behavior
M8
M7
8 - 32
CHUNG-YU WU
gain (log)
3 : Upper 3-dB frequency of Aorig
Atot
gain enhancement
= Aadd(0) +1
Aadd
Aorig
(log)
6
3 4
1 2
We want 5
Aorig
= 5
Atot
Z out
g m1
Z orig
g m1
Pole-zero
doublet
1 2
(log)
3 4 5
8 - 33
CHUNG-YU WU
2 : Upper-3dB freq. Of Aadd
A zero is formed at
4 for Z out
1
, must be smaller than the main close-loop time
PZ
1
. where is the feedback factor.
unity
4 .
gain (log)
Aaddd
1/
Aclosed-loop
4 5 6
(log)
5 < 4 < 6
doublet
8 - 34
CHUNG-YU WU
+VDD
Vbp1
Vbp1
Vcm
Vin-
Vin+
Ib
Vout+
Vbn1
Vout-
Vbn1
-VSS
MAIN CHARACTERISTICS OF THE OP AMP
Gain enh.
on
Off
DC-gain
Unity-gain freq.
Load cap.
Phase margin
Power cons.
Output-swing
Supply voltage
Settling time
0.1% , V o = 1V
90dB
116MHz
16pF
64deg.
52mW
4.2V
5.0V
61.5ns
46dB
120MHz
16pF
63deg
45mW
4.2V
5.0V
-
8 - 35
CHUNG-YU WU
Dead region.
Both pairs are off.
Vi,n,cm=Vi,cm+IR
Vi,p,cm=Vi,cmi-IR
* The input resistance over the entire voltage range is infinite and no loading effect or
input current over the previous stage.
Usually mismatches cause negligible input current.
* The symmetrical topology ensures very high CMRR
1 R Gm 1
CMRR =
(
+
)
RG m R
Gm
where Gm = I / Vi ,cm
8 - 36
CHUNG-YU WU
Circuit implementation
400/5
200/5
400/2
200/2
400/5
500/5
M15
R1-R4
RM
CM
700/2
30 K
5 K
10pF
I bn = I bp
10A
40A
Io
8 - 37
CHUNG-YU WU
4. Input CM adapter
= 2A(Vref Vi,p,cm )
I = G m Vx
=> Vi,p,cm Vref +
Vi,cm
2RGmA
Vi,p,dm = Vi,dm
5. Very LV CMOS OP AMP with a single differential pair and the input CM adapter.
8 - 38
CHUNG-YU WU
Main transistor ratios(in m) and element values of the amplifier based on a single input pair
M1A M1B
1000/6
M6
1600/2
M2A M2B
600/4
M7-M10
300/4
MA1-MA4
50/2
M11
700/2
MA5-MA6
300/4
R1-R2
15K
M2D
150/2
RM
M1,M2
M3-M5
200/2
400/2
CM
Is=Ir/2
5K
5pF
10A
6.Measured results
Experimental performance of amplifiers(Vsupply=1V,technology:1.2m CMOS, CL=15pF)
Parameter
Dynamic-shifting amp
CM adapater amp
Ido(supply current)
0.81mm 2
410uA
0.26 mm 2
208uA
DC gain
unity-gain frequency
87dB
1.9Mhz
70.5dB
2.1Mhz
Phase margin
61
73
SR+
SR-
0.8V/us
1V/us
0.9V/us
1.7V/us
THD(0.5Vpp@1kHz)
THD(0.5Vpp@40kHz
-54dB
-32dB
-77dB
-57dB
Vni(@1KHz)
Vni(@10KHz)
Vni(@1MHz)
267nV/ Hz
91nV/ Hz
74nV/ Hz
62dB
-54.4dB
-52.1dB
359nV/ Hz
171nV/ Hz
82nV/ Hz
58dB
-56.7dB
-51.5dB
CMRR
PSRR+
PSRR-
8 - 39
CHUNG-YU WU
+VDD
1. Folded-mirror differential input stage
VBIAS2
M3
M4
OUT
IN+
M1
M2
IN-
VBIAS1
M7
M5
M6
CMR is independent of supply voltage.
For VDD=1.5V , CMR=0.6 ~ 0.7V
-VSS
CMR of the conventional NMOS-input differential pair is 0.3-0.5V
2. Output Stage
+VDD
IB1
M6A M8A
M1A M3A
IB2
OUT
IN
M4A
M5A M7A
M2A
-VSS
Input section : M1A-M4A , IB1 , IB2
Output section: M5A-M6A and M7A-M8A
M5A, M8A sat
M6A, M7A off.
For low input levels , M6A and M7A off Class A operation.
For large positive input signals,
ID1A=IB1 M3A and M5A OFF
VA -VSS
M6A is turned on to supply most of the output current.
But M7A remains cutoff.
The current of M8A is increased.
For large negative input signals, M7A supplies most of the output current.
(W/L) 5A,8A << (W/L) 6A,7A for low dc power dissipation and high drive.
8 - 40
CHUNG-YU WU
IBIAS
M3
M6
M7
M6A M8A
M18
M12
M4A M11
M8
INM14
CC3A
M1 M2
M4
M5
M9
M16
CC3B
CC1
MC CC2
IN+
OUT
M5A M7A
M1A
M13
M2A
M3A
-VSS
1
ro5,7{(gm8 ro8,9 )2[gm5A,8A(ro5A || ro8A )]}Cc
g m1, 2
C c1
sCc 2
g m1, 2
Cc 2
C g
Ain C 1 m1 A, 2 A 2 g m 5 A, 8 A (ro 5 A ro8 A )
CC 2 g m3 A , 4 A
Dominant pole : P1in
Second pole : P 2in
g m3 A ,4 A
g m5 A,8 A (ro 5 A || ro8 A )C C 3 A, B
2 g m5 A, 8 A
CL
CC1
.
CC 2
8 - 41
CHUNG-YU WU
C g
Gain-bandwidth product : GBWin 2 C1 m1A , 2 A
C C 2 C C 3 A, B
or the second pole of the
whole amplifier
Design consideration :
To obtain a maximally flat Butterworth response without gain peaking, we have the
unity-gain frequency equal to one half of the second-pole frequency.
GBWin = uin =
1
P 2 in
2
1
1
GBW = u = uin = GBWin
2
2
Reference : IEEE JSSC, vol.27, pp.1709-1716, Dec. 1992.
Setting 2C C 3 A, B = C C 2 , we have
C C1 = 2
g m1, 2
g m5 A,8 A
CL
C C 2 = 2C C 3 A, B = 2 g m1, 2 g m1 A, 2 A
CL
g m5 A,8 A
Component values :
M1,M2,M3,M9,M1A,M2A,M10
60/2
M4,M5,M11,M12,M13
20/2
M6,M7
15/2
M8
M3A
90/2
5/1.2
M4A
15/1.2
M5A
30/1.2
M7A
120/1.2
M6A
360/1.2
M8A
M14,M16
90/1.2
10/1.2
M15,MC
30/2
CC1
4pF
CC2
6pF
CC3A,CC3B
2pF
IBIAS
VTH
5uA
0.8V
8 - 42
CHUNG-YU WU
Experimental results:
MEASURED MAIN PERFORMANCE
Open-Loop Gain
68dB
GBW
1MHz
Phase Margin
65o
16dB
400ns
1 V/s
Gain Margin
Settling Time(0.1%), V = 200mV
Slew Rate
THD@1kHz Vout = 0.5V RL=500 -57dB
Closed-Loop Gain=20dB
PSRR+@1kHz
75dB
PSRR- @1kHz
75dB
CMRR @1kHz
Offset
95dB
< 8mv
280W
Power Dissipation
Technology
0.08 mm 2
1.2m CMOS
Loading
50pF || 500
Die Size
9-1
CHUNG-YU WU
Metal
n+
p
p+
n+
Metal
p+
p
n
9-2
Tolarance= 40% (absolute)
* Large depth and lateral
spreading narrow resistors are impossible.
3. Implanted resistor
CHUNG-YU WU
( metal-gate technology )
CVD SiO2
SiO2
n+
n+
Implanted N+
p-sub
Metal
Field oxide
9-3
CHUNG-YU WU
i
V1
i=
R
V1 V2
R
V2
V1
V2
C (V1 V2 )
,
T
R=
T
1
=
C fC C
6. Thin-film resistor
* Realizable by NMOS and CMOS, metal-gate and Si-gate
technologies.
* Need additional process steps.
* Si-Chromium resistor or Mo resistor.
* Laser trimming is possible.
* Non-conventional material may be involved.
9-2 Capacitors
1. PN junction capacitor
* Well known and understood.
* Nonlinear capacitance with a large VCR.
9-4
CHUNG-YU WU
thin oxide
p+
P-sub
CMOS
metal-gate
Metal
n+
n+
Heavy n+ implant
9-5
o
* TC 20-50 ppm/ C
* Tolerance 15%
4. Poly to field implant region capacitor
CHUNG-YU WU
poly-Si
field oxide
p+
n+
substrate
p-sub
poly
CThick
CB
Thick oxide
P-sub
*
*
*
*
*
9-6
CHUNG-YU WU
deposited
oxides
Poly 1
Co
CThick
CB
poly to substrate
parasitic cap.
Thin thermal
oxide
Poly 2
Field oxide
P
Co
CB
9-7
Matching or ratio tolerance 0.01% ~ 1%
CHUNG-YU WU
Resistors :
L
R L Rs L W
,
=
W
R
L
Rs
L
W
L
R W
If L is large
0
L
R
W
R = Rs
1/ 2
2 L 2 W 2 Xt 2
L
+ +
R=
, R =
+
Xt W
L W Xt
W
=
for
long
resistor
W
* Long resistor pattern is recommended in precise resistors.
Capacitors:
C W L si02 t ox
C = sio 2 WL
=
+
+
t ox
C
W
L
sio 2
t ox
edge effect Oxide effect
CASE I : Absolute tolerance
C W L
=
+
(if W and L are small or sio 2 and tox are
C
W
L
neglible)
If W and L are independent with l = w = l
C = l
C
1
1
+
(random variation)
W 2 L2
Assume L=W=d , C =
C
C
C
square( L=W )
2 l
is minimum
d
< C
non square( W L )
9-8
C1 W1 L1
d dC1 dC2
=
,
=
C2 W2 L2
C1
C2
d = dc + dc
2
c1
2
2
c2
For W2=L2=d, d
=2
min
= l
= l
d
CHUNG-YU WU
1
1
1
1
2 +
2 +
2 +
2
L1 W1
L2 W2
L + W1
2+ 1
( d )2
2
l
if L1 = W1 = d
d
(1)
L2=d
W2=d
W1
L1
actual =
C1 W1 L1
= 2
C2
d
W1 L1 P1x + 4x 2 W1 L1 P1x
2
d 2 P2 x + 4 x2
d P2 x
x
P
2 ( P2 1 )
P
2( W1 + L1 )
IF P2 = 1 0 i.e. 4d =
So
2( W1 + L1 ) = 4 d
W1 L1 = d 2
W1 = d( 2 ) L1 = d ( + 2 )
d =
l
2 >>1 l
6
6
d
(2)
9-9
CASE IV : Ratio tolerance under edge and oxide effects
Take = 1 unit capacitor array
D
CHUNG-YU WU
C1
=4
C2
D
C2
D
D
C1
D
: Dummy capacitor
pattern
R1
dummy
resistor
R2
R1
R2
dummy
resistor
9 - 10
CHUNG-YU WU
V
Mn
1
V1
2
V2
VBS
Example:
V1= 0V, V= 3V V2= 0
V1= 5V, V= 8V, VTN =1.5V V2= 5V
2) If V1 + VTHN > V > VTHN , M N on
V 2 = V VTHN
Example: V = 5V , V1 = 5V , VTHN = 1.5V (under substrate
bias), VBS = 0V
V2 = 3.5V
3) If V < VTHN , M N off
Node 1 or 2 may be floating
V1 or V2 will be gradually charged or discharged by the
leakage current in MOS or PN junctions.
V
n+
A
9 - 11
CHUNG-YU WU
Cgs
Cgd
C1
C2
Vout
V : VDD 0
V1 f V1i VDD
Cgs
Cgs + C1
V2 f V2 i VDD
C gd
Cgd + C1
error voltage
Example: C gd 0.02PF, C 2 = 2 PF, VDD = 10V , error voltage 0.1V
Compensation circuit:
1
2. The PMOS switch
V
1
VDD
VGS = 5V
9 - 12
* Cant pass low voltage completely.
CHUNG-YU WU
VDD
* Full transmission
* The clock feedthrough effect can be greatly compensated, if
the delay between V and V is zero.
complicated.
* If V1 = 5V = V ,V = 0V ,VDD = 5V ,VTN =| VTP |= 1.5V
_
10 - 1
CHUNG-YU WU
= Bn i 2 D
A : Area of a BJT
= B ' ni 2T
= CT n
C:Constant, indep. of T.
n:Temp. exponent.
E : Constant, indep. of T.
VGO : Energy gap.
dVout
dT
=0=
T =TO
mV thermo
[K + ln( FG )] mVthermo ( ) ln TO mVthermo ( ) + d VGO
TO
TO
TO
dT
TO
d
K + ln( FG ) = ( ) ln TO + ( )
VGO
..(2)
dT
mVthermo
Substituting (2) into (1) , we have
Vout
10 - 2
T
d
= V GO + mVtherm ( )(1 + ln O ) T
V GO
T
dT
CHUNG-YU WU
7.02 10 4 T 2
T + 1108
VGO = 1.16
14.04 10 4 TO 7.02 10 4 TO
=
+
TO + 1108
(TO + 1108) 2
7.02 10 4 T 2
TO
) + 1.16
T
T + 1108
14.04 10 4 TOT 7.02 10 4 TO2 T
+
(TO + 1108) 2
TO + 1108
If = 3.2, m = 1, = 1, TO = 25 O C
Vout (T ) T =25
= 1.16 + 2.2(0.0259)
= 1.093V
+Vcc
Q4
I3 =
I
I
V BE 1 V BE 2
1
=
mVtherm ln( 1 ) + ln( S 2 )
R3
R3
I S1
I2
R1 I2
I1
R2>>R1
+
I
+ ln S 2
I S1
Vtherm
+
-
VBE1
I1 / I 2 = R2 / R1 If V BE1 = V BE 3
Adjust R2 / R3 , R2 / R1 and I S 2 / I S 1 to give a suitable K
And Keep I I 2 to obtain I B 2 I B 3 and
Q3 Vout
Q2 VBE3-
Q1
R R
Vout = V BE 3 + 2 mln 2
R3 R1
R2
VBE2
-
R3
I3
I S 3 I3
=
to obtain V BE1 = V BE 3 .
I S1 I 1
10 - 3
CHUNG-YU WU
V2
R2>> R1
R1
R2
VBE(on)
V1
+
Q1
Q2
3
ON State
V2
Cut-in State
R3
-
V1
10-3
R1
I2
R2
- Vos+
I1
Version 2:
N-well CMOS, Negative VREF
R1
I1
I2
R2
-Vos +
+
CMOS
R3
VREF
R3
VREF
+
Q1
Q1
Q2
Q2
-Vss
-Vss
+
CMOS
OP AMP
OP AMP
R2
R
I
R + R2
Vtherm (ln 2 + ln s2 ) + VOS [ 3
]}
R3
R1
I s1
R3
10 - 4
CHUNG-YU WU
0.6V
R
60mV
= 75 K, R1 = 2 = 7.5K, R3 =
= 7.5K
8A
10
8A
Large resistanceuse well resistors
R1,R2,R3:
n+/p+ diffusion resistors
n+ - poly resistors
well resistors
VBE +
I1
Error analysis:
1. Error due to base resistances
I
1
rI
VBE 1 = Vtherm ln 1 + Vtherm ln
+ b 1
1
IS
A1
1+
1
I2
+ Vtherm
I1
1
Q1
rb/A
I2
rb
2
Q2
-Vss
1
1
I
I
+ rb ( 2 1 )
ln
1
2 A1
1+
2
1+
R3 + R 2
R
R
I
) + 2 Vtherm (ln 2 + ln s 2
R3
R3
R1
I s1
1
1
R
I
I
) + 2 rb ( 2 1 )}
+ ln
1
R3 2 A1
1+
2
1+
VOS :
1
VREF
d
VREF =
dT
R2
)VOS
R1
10 10mV
=
= 264 ppm / o C
VREF T0
1.26V 300 o K
(1 +
I1
V
ln A
= VThrem ln therm
(R3=R1)
I S1
R I S1
V
ln A
R (T )
= V therm ln therm
+ Vtherm ln 1 O
R1 (TO ) I S1
R1 (T )
If R1 is indep. of T V BE = V therm ln
If R1 depends on T V BE = V therm ln
V BE = V BE
ideal
1 dR
Vtherm
R dT
TO
TO
I1 = I 2
Vtherm ln A
R1 (TO ) I S1
V therm ln A
R (T )
+ Vtherm ln 1 O
R1 (TO ) I S1
R1 (T )
(T TO ) Vtherm 1 d R
2 R dT 2 T
PTAT 2
1 dR
+ V therm 2
2 R dT
10 - 5
CHUNG-YU WU
(T T )2
O
PTAT 3
PTAT
PTAT
(T TO )2 ......
PTAT 3
PTAT
R2 rb I 2
)
R1 Vref 2
1 drb 1 dI 2 1 d2
rb dT I 2 dT 2 dT
10 - 6
Version 1:
Version2:
+VDD
+VDD
IE
IB
I1
CHUNG-YU WU
IB
I1
IB
IB
IB
IB
-VSS
-VSS
Q2
R3
VBGR
+
+
R1
VREF=VBGR(1+R4/R5)
R2
R5
R4
VBIAS
N
M1
M2
*Better matching
KT
VR1 = VBE1-VBE2=
ln( )
q
KT
Vo=VBE3+
[ln( )] (1+R/R) =>Bandgap Reference
q
10 - 7
CHUNG-YU WU
2.
VBIAS
M4
M3
M2
M1
3.
M110
10 - 8
4.
CHUNG-YU WU
M110
+VDD
M105
M104
M111
M103
M109
M108
M110
M106 M107
M101 M102
M3
M1
-Vss
M2
M6
M4
M5
M112
10 - 9
CHUNG-YU WU
M101
M102
-Vss
*Low driving capability
Power supply limits:
Low Possible
Bandgap reference
Topology
Voltage
T=25C
PMOS Inputs
NMOS Inputs
VTP 1.0V
VTN 1.0V
1
2
1.5v
1.95v
2.2v
2.95v
1.90v
2.5v
1.5v
10 - 10
A.
CHUNG-YU WU
sub
B.
metal
sub
Symbol:
Q2
Q1
A:Current comparator
VCC:Voltage-controlled current source
G:A negative voltage is applied to cause
accumulation.
10 - 11
CHUNG-YU WU
+VDD
+VDD
+
+
1:A
Vref
Vref
_
-Vss
-Vss
* High supply voltage.
* Two source follwers+one emitter follower
in(A) current amp.=>higher current gain
R4,R3,T3:VCC
R3: To keep T3 from quasi-saturation
R4:To sense the output voltage and transform it into the collector current of T3.
* All resistor are polyresistors
* Low output impedance.
Measured results:
VREF mean :1.2285V ;
Minimal supply voltage
Supply current
Noise spectra
316nV
PSRR(100Hz)
Load regulation (Vout/Iout)
Chip area
60dB
3.6V/A
0.42 mm2
Hz
( white) ; 560nV
1
,1KHz )
Hz f
(
10 - 12
500nV
Hz
1V
CHUNG-YU WU
+VDD
( white)
1
( ,1KHz)
Hz f
PSRR(100Hz)
77dB
-Vss
Load Regulation
4.1mv/A
(Vout/Iout)
Chip area
0.18 mm2
Curvature-Compensated BGR:
Ref: IEEE J. Solid-State Circuits, vol. sc-20, pp.1283-1285, Dec. 1985
10-4
Ref: Int. J. of Analog ICs and Signal Processing, Kluwer, pp. 207-215, 1992
1. Type A structure
The circuit stricture of the proposed BVR (Type A)
10 - 13
Vout = VBE 3 + I 3 R2 = VBE 3 + r3
R2 kT
( ln A* + Vsg )
R1 q
2. Type A structure
Cst
3. Type B structure
CHUNG-YU WU
10 - 14
4. Type C structure
The cascode structure of BVR (Type C):
CHUNG-YU WU
10 - 15
CHUNG-YU WU
The simulated output voltages versus temperature in Type A and Type A BVR
10 - 16
CHUNG-YU WU
10 - 17
CHUNG-YU WU
I1
R3
Vf1
I2a
Vf2
I1a
I1b
I3
I2
R1
R2
I2b R4
10 - 18
CHUNG-YU WU
dV f
R3
Vf 1
V therm
Vf
R2
I 3 = I 2 = I 2a + I 2b
V ref = R 4 I 3 =
R
R4
V f 1 + 4 dV f
R3
R2
VDD
10 - 19
*V ref = 1.25V
conventional BGR
*V ref = 0.84V
proposed BGR
CHUNG-YU WU
3.Minimum V DD
min V1 V s Vb VTHI V f + VTHI V DD + VTHP = min V DD VTHP
min V DD = V f + VTHI + VTHP 0.8 ~ 1.0V
0.54
-0.2
-0.3
4.Measured results:
VDD
VDD
* TC 60 ppm / O C
27 O ~ 125 O C
Voltage drift (average) 600V /V
2.2V~4V
11-1
CHUNG-YU WU
Analog Signal
( Video, Audio,
Sensor.....)
Filtering
and A/D
Conversion
Digital
Processing
Analog
Output
D/A
Conversion
and Filtering
Control
Analog World
Digital World
Analog World
(Digital signal processing has better noise immunity than analog signal processing.)
Digital
Data
Input
Data
Latches
D/A
Converter
Output
Sample
and Hold
Control
Fig. 11.2
Analog
Output
11-2
CHUNG-YU WU
2. Ideal DAC:
Vout = Vref (b12-1+b22-2+ ---- +bN2-N)
1
2N
Vout
VLSB
0.... 0
( LSB)
Vout
VLSB
1.... 1
Vout
VLSB
0..... 0 ] (2
N 1)
(LSB)
Vout
VLSB
Ideal transfer
response
(LSB)
Gain error
Actual transfer
response
Offset
error o
0......0
Digital Data
Input Bin
11-3
CHUNG-YU WU
(4) Accuracy
absolute accuracy: The difference between the expected and actual
transfer response. It includes the offset, gain, and
linearity errors.
relative accuracy:
*Accuracy units:
% of full-scale value.
effective number of bits
fraction of an LSB
Vout
)
212
Vout
VLSB
(LSB)
Best-fit
straight line
(maximum) INL error
(best-fit)
Transfer response
without gain and
offset errors
1......1
Bin
11-4
CHUNG-YU WU
4. Types of DACs
(1) Decoder-based DAC
(2) Binary-weighted DAC
(3) Thermometer-code DAC
(4) Hybrid DAC
(5) Oversampling DAC
11-5
CHUNG-YU WU
REF+
S256
R
S255
255 RESISTORS R
S254
S253
+
_
DAC OUT
S4
R
S3
256 OUTPUTS
R
S2
R
S1
8 To 256
DECODER
REF0 1 2 3 4 5 6 7
(DAC INPUTS)
2. Practical realization
R0-R15 : To divide VREF + to VREF- into 16 voltage intervals
H0-H15
L0-L15: To divide each of those intervals into 16
a-p
subintervals
11-6
CHUNG-YU WU
REF+
H15
0
1
4:16
2
3
L0
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
L11
L12
L13
L14
L15
H14
H13
H12
H11
H10
H9
H8
0
1
4:16
2
3
H0
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
H11
H12
H13
H14
H15
H7
H6
H5
H4
n15
R15
n14
R14
n13
R13
n12
R12
n11
R11
n10
R10
n9
R9
n8
R8
n7
R7
n6
R6
n5
R5
n4
H15
p15
o
H14
p14
L0
L15
n
H13
H12
H11
H10
H9
H8
H7
H6
H5
p13
p12
p11
p10
p9
p8
p7
L14
L13
L12
L11
L10
L9
L8
DAC OUT
p6
L7
p5
L6
p4
L5
p3
L4
p2
L3
p1
L2
R4
H3
H2
H1
H0
n3
R3
n2
R2
n1
R1
n0
H4
H3
H2
H1
R0
H0
REF-
p0
L0+L1
11-7
CHUNG-YU WU
Subinterval Generation:
14R T's
o
Lo
L15
n
Transmissiongate resistor
L14
L13
L12
L11
L10
Hi
RT
L9
L8
L7
DAC OUT
Ri+1
Ri
200
RT
L6
L5
Ri-1
Hi
R T=3.2K
L4
L3
L2
L0+L1
* For 8-bit DAC, the jump in step size can be held to less than 1 LSB if
16R T R i
Ri
R i
R i +16R T
Ri
=
=
1N
16RT 2NRi.
Ri
Ri
R i +16 R T 2
2N R i 16R T occurs when L1=1
11-8
CHUNG-YU WU
11-9
CHUNG-YU WU
11-10
CHUNG-YU WU
11-11
CHUNG-YU WU
voltage injection.
* Switched-induced errors are
large.
* offset cancellation
LSB
MSB
sign bit
If
bo = 0
11-12
CHUNG-YU WU
If
b0 = 1
Vout = -Vin bi 2 i
i =1
1. Conventional structure
* Simple circuit structure without
decoding logic.
* At the mid-code transition 011---1
10---0, the MSB current source
needs to be matched to the sum of
all the other current sources to
within 0.5 LSB.
difficult for large bit number.
not guaranteed monotonic.
* Low-accuracy matching causes
inaccurate bit transition
typical DNL plot as shown
* The errors caused by the dynamic
behavior of the switches, such as
charge injection and clock feedthrough,
result in glitches which is most severe at the
midcode transition, as all switches are
switching simultaneously.
contains highly nonlinear signal
components
manifest itself as spurs in the frequency
domain.
maximum
Midcode glitches
Transfer
response
11-13
CHUNG-YU WU
2.
11-13
CHUNG-YU WU
11-14
CHUNG-YU WU
Improved Structure
CHUNG-YU WU
11-15
CHUNG-YU WU
11-15
CHUNG-YU WU
11-16
CHUNG-YU WU
I1 = K (W/L)(Va-Vth1)2
IN = K (W/L)(Va-VthN)2
(VthN-Vth1) may be as large as 80 mV
due to the oxide thinning effect.
11-16
CHUNG-YU WU
11-17
CHUNG-YU WU
I 2 = K W (Va Vth 2 )2
L
= K W ( VR1 + Vth c Vth 2 + LcIc ) 2
L
KWc
1. I2IC
2. M2 and MC are locally matched
VR1
I 2 K W VR1
L
11-17
CHUNG-YU WU
11-18
CHUNG-YU WU
11-19
CHUNG-YU WU
To Coax
YB
Y
D1
Driver
D5
YB
Vdd
Vdd
Vdd
VR2
VR2
VR2
Vb
Vb
Vb
VR3
ILSB
x1
VR3
x1
VR3
Vdd
Vdd
VB
To Dummy Load
ILSB
x16
Driver
Driver
D6
YB
Vdd
YB
IMSB-5
D10
Driver
Vdd
VB
VR2
VR2
c
Va
IMSB
Gnd
VR1
Va
IMSB-1
x16
VR2
Va
IMSB-4
x1
VR1
x1
VR1
11-19
CHUNG-YU WU
11-20
CHUNG-YU WU
CKs
D
Din
VB1
DB
VB1
Vdd
out
in
out
in
VB1
VB1
Vss
(a)
(b)
(a) The circuit; (b) The SPICE simulated output waveforms
of the input driver with high logic-threshold.
11-21
CHUNG-YU WU
16I
8I
4I
2I
I I
Compact
Symmetry
M2
M2
M2
M2
Mc
M2
Mc
M2
M2
11-22
CHUNG-YU WU
11-23
CHUNG-YU WU
4-Cell Unit(%)
5-Cell Unit(%)
1/2 LSB
28.6
21.4
1 LSB
82.1
67.9
2 LSB
93.9
89.3
10 bits
0.21 LSB
0.23 LSB
125 MS/s
8 ns
3 ns
40 psV
150 mWatts
5V
0.8um CMOS
1.8mm1.0mm
SUMMARY
1. Using threshold-voltage compensated current sources.
2. Two-step weighted current array 32 master, 32 slave unit current
sources.
3. 10 bits, 125MHz, INL0.21 LSB, DNL0.23 LSB,
150mW.
4. Few analog components & good performance.
11-24
CHUNG-YU WU
0 0 0 0 0 0 0
0 0 1
0 0 0 0 0 0 1
0 1 0
0 0 0 0 0 1 1
.
.
.
.
1 1 0
0 1 1 1 1 1 1
1 1 1
1 1 1 1 1 1 1
2. Conceptual circuit of thermometer-coded DAC
V DD
Vout,p
Binary
input
Vout,n
1024
Binary-to-thermometer decoder
10
+50%
Tolerance
-50%
4X
4 LSB
one step
1 LSB
1 SWITCH
4 SWITCHES
Advantages:
(1) Monotonicity is guaranteed.
(2) The matching requirement is much relaxed .
e.g. 50% matchingDNL0.5 LSB
(3) At the midcode transition the glitch is greatly reduced.
only 1 LSB current source is switched.
11-25
CHUNG-YU WU
R
Vout
4LSB
LSB
2LSB
* The two LSB bits D0 and D1 are fed to two parallel three-stage pipelined
latches directly.
* The six MSB bits are fed to the decoders. (D2, -----, D7)
11-26
CHUNG-YU WU
D4
D3
D7
D6
D5
Decoding scheme:
Column
D4
D3
D2
D4+D3+D2 = C1
D4+D3 = C2
D4+D4D3+D3D2+D4D2 = C3
D4 = C4
D4D3+D4D2 = C5
D4D3 = C5
D4D3D2 = C7
Row
D7
D6
D5
D7+D6+D5 = R1
D7+D6 = R2
D7+D7D6+D7D5+D6D5 = R3
D7 = R4
D7D6+D7D5 = R5
D7D6 = R6
D7D6D5 = R7
R1+C1
R2+R1C1
R3+R2C1
R4+R3C1
R5+R4C1
R6+R5C1
R7+R6C1
R7C1
R1+C2
R2+R1C2
R3+R2C2
R4+R3C2
R5+R4C2
R6+R5C2
R7+R6C2
R7C2
R1+C3
R2+R1C3
R3+R2C3
R4+R3C3
R5+R4C4
R6+R5C4
R7+R6C4
R7C3
R1+C4
R2+R1C4
R3+R2C4
R4+R3C4
R5+R4C4
R6+R5C4
R7+R6C4
R7C4
R1+C5
R2+R1C5
R3+R2C5
R4+R3C5
R5+R4C5
R6+R5C5
R7+R6C5
R7C5
R1+C6
R2+R1C6
R3+R2C6
R4+R3C6
R5+R4C6
R6+R5C6
R7+R6C6
R7C6
R1+C7
R2+R1C7
R3+R2C7
R4+R3C7
R5+R4C7
R6+R5C7
R7+R6C7
R7C7
11-27
CHUNG-YU WU
Buffers
Buffers
D5
D7
D5
D7
D7
D6
D7
D7
D6
master slave
First stage
Second stage
Logic diagram of the segmented column decoder is similar to that of the row
decoder.
Current cell circuit
Ci
Ri
Ri+1
Third stage
11-28
CHUNG-YU WU
Switching order
Switching order
C1 C3 C5 C7 C6 C4 C2
R1
R3
R5
R6
1
3
5
6
6
4
2
7
R4
R2
R7
Switching order
Switching order
Vcomp
M1
Vref
Vp
M2
Vref
Vp
M3
C
B
1 LSB current source
Vdd
Vcomp
Vref
Vp
11-29
CHUNG-YU WU
11-30
CHUNG-YU WU
1024 = 32
Area (INL=0.5-lsb)
Area (INL=1-lsb)
Area (DNL=0.5-lsb)
256*Aunit
64*Aunit
1024*Aunit
256*Aunit
64*Aunit
Aunit
Optimal point
Adigital = AINL = 1.0 lsb
THD
binary
segmentation [%]
thermometer
11-31
CHUNG-YU WU
Cell circuit
Digital: decoding logic + latch
Analog: differential switch +
cascoded current source.
Biasing scheme
Global biasing: common-centroid
layout
Local biasing: 4 quadrants
without direct connection between any two quadrants
DNL and INL
11-32
CHUNG-YU WU
Fs(MS/s)
100
300
500
Fsig(MHz)
8
100
240
11-33
CHUNG-YU WU
Summary
DNL
0.1 LSB
INL
0.2 LSB
(dB)
SFDR=
A I D3= N0 AN 0 ID1= N
11-34
CHUNG-YU WU
11-7 Summary
[16]
[15]
[14]
[9] [10]
[7] [6]
[13]
[12]
[3] [2]
[8] [5]
[11]
[14]
[4]
[1]
1. Kuang K. Chi et al, "A CMOS triple 100-Mbit/s video D/A converter with shift
register and color map," IEEE J. Solid-State Circuits, Dec. 1986, pp. 989-995.
2. T. Miki, Y. Nakamura, M. Nakaya, S. Asai, Y. Akasaka, and Y. Horiba, "An 80MHz 8-bit CMOS D/A converter," IEEE J. solid-State Circuits, pp. 983-988, Dec.
1986.
3. L. Lteham, B.K. Ahuja, K.N. Quader, R.J. Mayer, R.E. Larsen and G.R. Canepa,
" A high-performance CMOS 70-MHz palette/DAC," IEEE J. Soulid-State
Circuits, pp. 1041-1047, Dec. 1987.
4. A. Cremonesi, F. Maloberti, and G. Polito, " A 100-MHz CMOS DAC for videographic systems, " IEEE J. Solid-State Circuits, June 1989, pp. 635-639.
5. N. Kumazawa, N. Fukushima, N. Ono, and N. Sakamoto, "An 8 bit 150 MHz
CMOS D/A converter with 2 Vp-p wide range output," 1990 Symposium on
11-35
CHUNG-YU WU
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
12-1
CHUNG-YU WU
Latch
Vout
+
or
Vout
The latch provides a large and fast output signal, whose amplitude
and waveform are independent of those of the input signal. Well
suited for the logic circuits usually following the latch.
If no latch:
-A1
-A2
* Mostly dynamic
-A3
Vout
-An
Latch
or
Vout
12-2
CHUNG-YU WU
M9
M4
M8
Vbias
M15
M12
M11
M1
M2
Vout
M10
M6
M5
M13
M7
M14
-VSS
(10mV, 15PF)
* Power Dissipation:
~ 4mW
1.0s~2.8s
12-3
CHUNG-YU WU
+VDD
M4
M3
M7
Vbias
M10
M8
-
+
M1
Vout
M2
M5
M9
M6
M11
-VSS
M4
M14
M7
M11
Vbias
M
8
M12
+
M1
Vout
M2
M9
M10
M5
M6
M13
M15
-VSS
12-4
CHUNG-YU WU
Q5
Q6
Q8
Q10
input+
Q12
I
Q
Vo
inputQ1
Q2
Iset
Q11
Q9
Rext Q3
Q7
Q4
External
resistor
V-
* Quad comparators
* Open loop gain (IsetIQ50A): 96dB
* Propagation delay: ~1s
5. Fully differential OP-AMP Comparators.
1=1
Vin
- Vos +
C2
C1
Gain Stage
+V in -
* Vc1=Vin-Vos
+
_
* offset memorization
2=1
+V in -
* No compensation
C2
+
Vref
*Vc1Vref-Vin
Vout
Vos
C1
Vc1
+
_
Vos
* offset cancellation
1 , 2 :nonoverlapping
clocks
Gain Stage
+
Vout
12-5
CHUNG-YU WU
+VDD
C1
Vin
S1
Vout
+
_
S4
C2
2
Vbias
Vref
-Vss
S3
1a
* Practically, 1a must go low first in advance of 1 to avoid the clock
feedthrough effect of S1 by 1.
(2) Dynamic fully differential comparator
+V DD
Vin+
VinVbias1
1a
1a
+ Vout S1
C1
Vs
Vs
S2
2
C2
1
Vbias2
VinVin+
-V SS
12-6
CHUNG-YU WU
Q4
VC
S7
Vout
S8
Q1
Vin-
Q2
VB
C2
C1
S1
S5
Vin+
+
Q5
S4
Q6
Vin+
S6
S3
Vin-
Q7
VBIAS2
-Vss
* 2 1,
S5 short
2 1,
S6 short
12-7
CHUNG-YU WU
VT
VDD
Q2
VT
S3
VB
VA
Q1
-VSS
(a)
(b)
+VDD
Q2
C
+
Vin
A
S3
VB
2
VA
Q1
CA (stray)
-Vss
(a)
2 0,
CAC,
VA1Vin + VAo
VAVin
(2) CMOS Cascade Comparator.
* Q1 Q3, Q2 Q4
(b)
negligible feedthrough
12-8
CHUNG-YU WU
R = R 0 = rdsp rdsn
~ 100 k
CinCgs + Cgd(1+ A )
~0.5 pF
A ~ 10
VDD
Q2
1
Vin
S2
C2
VB
B
3
C VC
S8
C3 VD
Q5
Q1
6 (strobe)
Q6
S3
C1 VA
S1
Q4
LATCH
S5
Q3
5 (balance)
VSS
(a)
(b)
Vout
12-9
CHUNG-YU WU
1
Vin
S1
A
SA
1
LATCH
VSS
VDD
SB
2
VSS
12-10
CHUNG-YU WU
Vin +
C1
+
Vout
Vout
Vin -
C2
-VSS
C4
Q5
C3
Vout +
S3
S1
A
VA
VC
C1
3
Q6
D
S4
S5
Q1 Q2
VD
Q 3 Q4
S2
S6
B
VB
VinS8
S7
VSS
V in-
Vin +
(a)
C2
+
Vout
12-11
CHUNG-YU WU
H,
VD
L.
Vin- Vin+ : VC
L,
VD
H.
12-12
CHUNG-YU WU
input stage
flip-flops
S-R latch
VDD
1:2
M13
M3
M10
M6
M2
M1
M11
Q
IB
Vinp1
M7
M8
Vinp2
a
VSS
M9
M12
M4
b
M5
t1~t2: M12 ON (2 1)
M10-M11 ON, M8-M9 OFF (10)
VaVb, Vc=Va, Q= Q
Vinp1 and Vinp2 settles
t2~t3: Va Vb established with some regeneration of M4 /M5, M12 OFF
t3-t4: 1 1, 20 M12 OFF, M10, M11 OFF, M8, M9 ON
strong regeneration Vc Va, Va=Vc, Vb=Vd Q, Q
established
for input sampling
V
2e
t1
t2
t3
t4
12-13
CHUNG-YU WU
Performance:
Technology
1.5 um CMOS
Die size
Power supply
+2.5 / -2.5 V
2.5 V
Resolution
8 bits, 1LSB=9.8 mV
Sensitivity
Sampling rate
65MHz
Offset voltage
3.3 mV
Input capacitance
30 fF
13-1
CHUNG-YU WU
Analog
Input
Sample
and
Hold
A/D
Converter
Digital
Output
Output
Latch
Control Logic
01
10
11
ref
ref
ref
ij
ref
Vin
Vref
13-2
CHUNG-YU WU
Overloaded ADC: When Vin > Vin ideal + Vx or Vin < Vin ideal Vx , the
quantization error is greater than 1/2 VLSB.
3. Quantization noise
Quantization error Quantization noise.
V1 = Vin + VQ
V in
ADC
VQ = V1 - Vin
DAC
V1
VQ
VQ(rms) = 1
T
T/ 2
T /2
1/ 2
2
VQ
VLSB3 t 3
=
3 3
T
dt
=1
T
T /2
T /2
T /2
T/ 2
1/ 2
2
VLSB ( t )2
T
1/2
dt
VLSB
12
VQ
Vin
V1
+
1
VLSB
2
0
1
VLSB
2
V1
T
2
T
2
t
( time )
VQ ( rms ) =
= 1 2
VLSB
2
x 2 f Q ( x ) dx
x 2 dx
VLSB /2
V LSB /2
High =
V LSB
1/ 2
f Q (x)
dx =1
1/2
VLSB
12
1
2
V LSB
1
2
V LSB
13-3
CHUNG-YU WU
V / 12
= 20 log ref
V / 12 = 20 log 2 = 6.02 N dB
LSB
Vin( rms )
V /2 2
= 20 log ref
= 20 log 3 2 N = 6.02 N +1.76dB
VQ ( rms )
VLSB / 12
2
The above SNR is the best possible SNR for an N-bit ADC
Vinpp = Vref ( 0dB) SNR = 6.02 N +1.76 dB
Vinpp 20 dB SNR = (6.02 N +1.76 )dB 20 dB
5. Performance specifications
(1) Missing codes (equivalent to monotonicity in DAC)
Maximum DNL < 0.5 LSB or maximum INL < 0.5 LSB
Vref
sin (2 f in t )
2
13-4
CHUNG-YU WU
dV
dt in
max
= f in t
zero-crossing point
VLSB
= N1
f in Vref 2 f in
f in t < 5 ps
f in t < 5 ps
High speed:
13-5
CHUNG-YU WU
VREF
3R
2
B B
R
R
R
Comparator
_
Output
VIN
R
2
Resolution
100 /
Nonlinearity
Conversion time
8 bit
1 LSB
2
1 LSB
10
20 s
Input resistance
>1000 M
<1/4 LSB
DNL
Error Sources:
1. Resistor matching accuracy.
* Dividing the string into several equal lengths and locating them in close
proximity.
13-6
CHUNG-YU WU
2. The reverse bias junction voltage of the diffused resistors causes nonlinearity.
Bit capacity /
3. The small on resistance of the switches can decrease the settling time and
reduce the feedthrough effect from the gate voltages. Similary, the switch
feedthrough only effects the settling time.
4. Major error source: The feedthrough in the switch transistor Q2.
1 MHz clock 2 mV error.
5. Comparator offset error.
3rd
MSB
MSB Vin
2-bits +
A
E
T1
T1
T2
Sample
data
Comparator
T1
A
F
H
B
D
2 nd
MSB
T2
R/4
LSB
T2
R/4
R/4
D
R/8
R/8
T1
C/16
1/2 LSB
Shift
T2
8-bit ADC
C/16
C=20pF
Linearity
1/4LSB
Supply Voltage
4.5 - 6.3 V
Conversion Time
100 s
Current Drain
1.8mA
VREF Range
0-5V
0 - VDD
13-7
CHUNG-YU WU
Linearity
1/2 LSB
Conversion Time
50 s
Analog input
Vss ~ Vcc
0.1 ~ 3MHz
Supply voltage
4.5 ~ 6.3V
Current drain
5mA
13-8
CHUNG-YU WU
Final Configuration:
Vx = Vin + Vref ( +
Vx = Vin +
b 4 b 3 b 2 b1 b 0
+ + + + ) 0
21 2 2 2 3 2 4 2 5
Vref 4
( 2 b 4 + 2 3 b3 + 2 2 b 2 + 21 b1 + 2 0 b 0 ), Vin > 0
5
2
13-9
CHUNG-YU WU
Measured Results:
Resolution
10 bits
Gain error
0.05 %
Linearity
1 LSB
2
Sample mode
acquisition time
2.3s
Input Voltage
0-10 V
Total conversion
time
22.8 s
Input offset
2mV
13-10
CHUNG-YU WU
R1
SF
R2
Ck+1
Ck
C3
2 k-1C 2 k-2C
R3
2C
C2 C1
C
+
Comparator
SA
R2 M-1
CLOCK
B
SB
R2M
SWITCH
CONTROL
VIN
START
* SAMPLE
* HOLD
* CHOOSE Vref
VREF
R1
S5
Vin
S4
Larger
Vref
4
Smaller
Vref
2
discharge
set-up
ON ON
redistribution 2
ON ON
3/4 V REF
R2
S3
S2
1/4 V REF
R4
SA
2
2
SB
S1
SB
S1
S2
S3
S4
ON ON
1/2 V REF
R3
Voltage A- SA
B
ON ON
ON
S5
13-11
CHUNG-YU WU
Implement:
16 R, 8 ratioed capacitor, 37 MOS
, 16 R= 9000
Resolution
12 Bits
Area
Monotonicity
12 Bits
DNL
1 LSB
2
Input. Offset
50s
5 mV
Operational Principle:
Vref
SX
S5
R1
2k-1C
S4
R2
C
SLK
SL2
C
SL1
+
Vx
-
+
Comparator
1
SA
S3
R3
2
S2
R4
SB
S1
1
VIN
SA
SB
S1
S2
S3
S4
Sample
Hold
Vin
1
B
B
.
.
B
B
Choose Vref
Sx
Vx
B
B
ON
OFF
OFF V + Vref
in
-Vin
(0)
2
(Vref/4)
(Vref/2)
2
(3Vref/4)
Discharge
1
(0)
4
OFF V + 2Vref
in
4
OFF V + 3Vref
in
4
OFF
-Vin
13-12
CHUNG-YU WU
Set up
OFF
Vin +
OFF
3V
Vin + ref
4
+ 1 Vref
8
(Vref) (3Vref/4)
Redistribution
1
3Vref
4
13-13
CHUNG-YU WU
LATCH, DECODER,
DISPLAY MULTIPLEXER
SEQUENCE COUNTER
/ DECODER
CONTROL
LOGIC
ANALOG
SECTION
CREF
REF HI
DE
REF LO
DE
INT1
IN HI
X10
CINT
RINT
C2
<10>
COMPARATOR 1
+
DE-
DE+
DE+
DE-
BUFFER
ZI , X10
COMMON
INT
IN LO
INT1,IN2,INT
REST
C3
INTEGRATOR
<100>
COMPARATOR 2
+
TO DIGITAL
SECTION
13-14
CHUNG-YU WU
DE1
INT1
X10
RESET
DE2
V'
INT(ZI)
INT2
Operational principles:
1. INT1
REF HI
REF LO
CINT
CREF
RINT
IN HI
IN LO
Comparator 2
+
+
COMMON
Comparator 1
C3
100p
+
-
13-15
CHUNG-YU WU
2. DE1
REF HI
REF LO
+ -
R INT
CINT
+ -
COMMON
+
-
C3
100p
+
-
3. REST (INT2)
REF HI
REF LO
CREF
CINT
R INT
+V -
+
+
C3
100p
COMMON
V
+
+
-
IN LO
V Residual Voltage
4. 10 (INT2)
RINT
+
COMMON
IN LO
10 V
+
C INT
10 V
+
C2 10p
C3 100p
+
-
+
-
13-16
CHUNG-YU WU
C INT
C3
100p
+
-
+
-
IN LO
13-17
CHUNG-YU WU
Vin
Sample/Hold
Comparator
S/H
Comp.
V(i)
multiplier
B(i)
x2
+ Vref
- Vref
13-18
CHUNG-YU WU
3+4+6+7
C3
C7
S4
C2
8*1
S2
1+2
Vin
C1
(A)
(C)
Vref
OP1
3+4+5+6+7
+
4
C5
3+4+7
3+6
C6
3+7
6+7+1
Latch
S7
C8
(D)
7+1
S5
b8(1+2)
3+6
OP2
3+4+6+7
b8*1
S3 3+4+6+7
S1
C4
S6
(B)
1+2+3+4
comp.
+
bBit
Bit
switch
Clock waveforms:
13-19
CHUNG-YU WU
Operational principles:
Step 1:
C2
8*1
C1
C3
Vin
C7
C4
-
OP1
OP2
+
+
C5
b8*1
Vy(1)
C6
b8*1
13A + 27 Vx ( 3) 1 7 A + 8 + 7A + 9
Vy (1) 2 13A + 20
+
( A + 2) 2 ( A + 3) 2
2
( A + 3) 2
( A +2)
Vref
Step 2:
C2
C1
C3
Vin
C4
C7
-
OP1
+
OP2
+
Vx(2)
C5
C6
b8*2
to Comp.
C4
C1
C3
-
C7
OP2
OP1
+
Vx(3)
+
C5
C6
Vy(2)
13-20
CHUNG-YU WU
Step 4:
C2
C4
C3
C7
C1
OP2
OP1
+
Vy(4)
+
C5
C6
Vref
Vy ( 4 ) C5 ( Vx ( 3) Vref )(1+ 3/ A )
C6
Step 5:
C2
C4
C1
C3
C7
OP1
OP2
+
Vref
+
C5
C6
C2
C4
C1
C3
-
C7
OP2
OP1
+
+
C5
C6
Vy(5)
13-21
CHUNG-YU WU
Step7:
C2
C4
C1
C3
C7
OP2
OP1
+
Vy(7)
+
C5
C6
( 2 2 ) Vx ( 3) (1 2 ) Vref
A +3
A+ 3
Vy ( 7 )
1+ 3 / A
Vin+
Latch
-+
OP1
+-
Vref+(-)
Vref-(+)
-+
-+
OP2
comp.
+-
+-
Vin-
+ -
bBit
- +
Bit
13-22
CHUNG-YU WU
m13
m4
m5
m6
m7
VB1
VB2
Vo+ VoVin-
Vin+
m1
m3
m8
m2
m9
m10
m11
m14 m15
VSS
VB3
VB4
13-23
CHUNG-YU WU
13-24
CHUNG-YU WU
Table I
14 bits
Differential nonlinearity
1/2 LSB
Integral nonlinearity
1 LSB
Sampling frequency
10 KHz
Gain of op amp
60 dB
Power dissipation
50 mWatts
Supply voltage
2.5 V
Process
0.8 m CMOS
2.1mm 0.8mm
13-25
CHUNG-YU WU
Table II
Performance
[4.4]
[4.5]
This work
12
14
<= 1.5
<= 0.5
<= 1
92
84
60
6n
3n
7n
10
17
50
Resolution
(bits)
Absolute
INL (LSB)
OP amp dc
Gain (dB)
Clock cycles
for n bits
Sampling rate
(KHz)
Power dissipation
(mW)
13-26
CHUNG-YU WU
+
-
2N-1
2N-1
2N-2
2N-2
+
-
Encoder
2N-1 to N
binary code
+
2
+
comparator
VREF-
Latch
Clock
generator
bN-1
bN-2
bN-3
b2
b1
b0
13-27
CHUNG-YU WU
6-BIT
BINARY
OUTPUT
13-28
CHUNG-YU WU
13-29
CHUNG-YU WU
Major source of error is the loading of the reference resistor ladder by the
comparator bank.
Resistor ladder loading errors are of two types:
(1) "Transient error" associated with instantaneous ladder loading during a
single measurement;
(2) Long-term "recovery error" associated with errors at a new input level
after the ladder has been loaded for a long period by inputs at another
level.
If the capacitor bypassing is performed at the externally accessable ladder
midpoint tap,
transient impedance by a factor of more than 4.
Worst-case static loading which can't be bypassed makes recovery errors
the significant error source.
* All the errors considered above are of this type.
Typical 6-bit A/D converter Performance:
Power dissipation at 15 MHz clock, 20 pF/output.
5V
8V
convert mode
50mW
145mW
Tracking mode
45mW
130mW
3.2V reference
9mW
9mW
Input Cap.
8 pF
8 pF
Recom. Vref
3.2V
6.4V
3.2V
6.4V
75
75
Accuracy 15MHz
1 LSB
2
1 LSB
2
20MHz
---
1 LSB
25MHz
---
1.5 LSB
13-30
CHUNG-YU WU
VREF
TOP
D-Type
Output
Latch
Comparator
R/2 Banks
Latches
Overflow
127
R
D6
D5
R
64
R/2
Mid
Decouple
Cext
Capacitor
Bypassing
R/2
128 to
7 bit
Encoder
Logic
D4
D3
D2
D1
R
0
VREF
Bottom
D0
R/2
Analog
Input
Clock Buffer
13-31
CHUNG-YU WU
Load
Bias
OUTPUT
Q10
Q11
Q12
Q 13
Q14
Q16
Q3
Vbias
Q4
Q5
Analog
Input
Vbias
Reference
Input
Q6
Q1
Q2
Latch
I2Bias
Latch
Q8
Q9
I2Bias
IBias
Q7
Q15
-VSS
Gain: 18dB
Bandwidth: 40 MHz
enable
the
comparator to recover
much faster from the
latched state.
The secondary latch is of the hysteresis type, because
(1) it can convert the limited logic swing of the primary latch to correct
CMOS logic levels.
(2) it can reduce the amount of hysteresis to ~ 100mV by setting "Latch"
13-32
CHUNG-YU WU
0.5 LSB.
- 1 LSB 5 MHz
2
: > 22 MSPS, 30 MSPS typically
: 5V 0.5V
: 1.5V~3.5V
: 350 mW
: - 40 o C to + 85 o C
Analog bandwidth
: -3dB 42 MHz;
VDD
1
S1
S5
VDD
A
CA
S7
LATCH
S2
Sampling
Clock
S6
VDD
VDD
B
S3
S8
S4
CB
13-33
CHUNG-YU WU
VA < V REFi+1 0
0
0 i+1
1 i
1
VA > V REF 1
0
VA < V REFi+1
0
i+1 0
Metastable
i X
VA ~ V REFi
state
i-1 1
1 VA > V REFi-1
13-34
CHUNG-YU WU
+
SAMPLE
&
HOLD
VIN
COARSE
FLASH
ADC
FINE
FLASH
ADC
DAC
ANALOG
ADDITION
LATCH
DIGITAL
OUTPUT
Vin
MSB'S
TGS2
COARSE
COMPARATOR
NO. 16
COARSE
COMPARATOR
NO. 15
COARSE
COMPARATOR
NO. 14
TGC16
VREF
15
TGC15
15
TGC14
R15
15
"COARSE"
DECODER
/ENCODER
COARSE
COMPARATOR
NO. 1
LSB'S
R16
R14
COARSE
COMPARATOR
NO. 2
SAMPLE
TGS
SAMPLE
TGC2
TGC1
FC #14
R3
15
R2
15
R1
FC #15
15
*FINE*
DECODER
/ENCODER
FC #2
CLEAR
FC #1
VREF
"FINE"
COMPARATOR
13-35
CHUNG-YU WU
13-36
CHUNG-YU WU
Subranging
256
31
Clock cycles/conversion
Relative speed
0.5
0.12
0.2
0.4
Total comparators
0.4 LSB
0.3 LSB
0.7 LSB
0.5 LSB
* High accuracy is required only for the S/H circuit and the D/A subconverter.
(S/H is to reduce the effect of signal delay differences in the large-area
chip.)
* Very difficult to develop a high-speed (video) and high-accuracy MOS S/H
circuit.
13-37
CHUNG-YU WU
13-38
CHUNG-YU WU
13-39
CHUNG-YU WU
13-40
CHUNG-YU WU
13-41
CHUNG-YU WU
13-42
CHUNG-YU WU
13-43
CHUNG-YU WU
2. New structure
* No OP amps.
* No gain block
13-44
CHUNG-YU WU
3. Circuit implementation
13-45
CHUNG-YU WU
4. ADC Performance
13-46
CHUNG-YU WU
13-47
CHUNG-YU WU
13-48
CHUNG-YU WU
13-49
CHUNG-YU WU
13-50
CHUNG-YU WU
The layouts and their equivalent circuits (a) with and (b) without separated
unit resistors.
(a)
Experimental Results:
Chip photograph of the fabricated A/D converter.
(b)
13-51
CHUNG-YU WU
13-52
CHUNG-YU WU
13-53
CHUNG-YU WU
0.8m CMOS
8bits
-0.4 to + 0.4 LSB
-0.6 to + 1 LSB
46.8 dB
50 MHz
0.5V to 2.5V
3V
100 mW
4950 um 3790 m
13-54
CHUNG-YU WU
13-55
CHUNG-YU WU
Pipelined ADCs
13-7.1 A Pipelined 5-Msps 9-bit ADC
Ref.: IEEE JSSC, vol. 22, no. 6, pp. 954-961, Dec. 1987.
1. General pipelined ADC
3. Prototype
13-56
CHUNG-YU WU
13-57
CHUNG-YU WU
OP AMP:
13-58
CHUNG-YU WU
Comparators:
4. Measurement results:
13-59
CHUNG-YU WU
DAC + +
SHA MDAC
13-60
CHUNG-YU WU
13-61
CHUNG-YU WU
* Transfer characteristic:
The output residue voltage Vout
Vout = 2Vin + D Vref
D = +1 for 0 < Vin < Vref
= -1 for -Vref < Vin < 0
* Digital correction technigue:
Very attractive for submicron
CMOS (small chip area)
13-62
CHUNG-YU WU
Transfer characteristic:
Vout = 2Vin + 2 D Vref
D = +1
=0
= -1
13-63
CHUNG-YU WU
Code_l=0
Vout = -Vref
Code_h=0
13-64
CHUNG-YU WU
* op amp
(telescopic op amp)
13-65
CHUNG-YU WU
4. Measurement results
DNL:
INL:
13-66
CHUNG-YU WU
Spectrum:
13-67
CHUNG-YU WU
13-68
CHUNG-YU WU
* Transfer response of V1, V2a, V2b, V2c , V2 vs. Vin: Logic 1 = 5V, Logic 0 = 0V
Gain of input amplifier = -10
Latch threshold = 2.5V
More reference levels between V1 and V2: V2a, V2b, V2c .
13-69
CHUNG-YU WU
13-70
CHUNG-YU WU
13-71
CHUNG-YU WU
13-72
CHUNG-YU WU
A 4-bit folding A/D converter with a folding rate of four and an interpolate-by-two. (The
MSB converter would usually be realized by combining some folding-block signals.)
* Folding rate: 4;
Interpolation: 2
13-73
CHUNG-YU WU
13-74
CHUNG-YU WU
* Folding rate: 4
Interpolation: 2
* 16 comparators and 16 folders cyclic thermometer 5 LSBs.
* 5 amplifiers are used
* Two stages higher gm.
* Resistor load better transient performance.
* Output current mode speed .
13-75
CHUNG-YU WU
5. Practical folders:
(a)
(b)
* Vx1 and Vx2 are fixed voltages generated by a single preamplifier shared
by all folders.
* Power dissipation .
6. Interpolation with current-mode folder signals
Fig. 8. Interpolation can be used to eliminate half or more of the folder blocks
Fig. 9. Interpolation with current-mode folder signals. A current split-infour block is shown on the right.
13-76
CHUNG-YU WU
* Improved circuit:
Merge the current division within the folder.
Fig. 10. The folder is modified to include current division. The modified amplifier
is on the right. A block diagram for a modified folder is also shown.
Fig. 12. The comparator core (a) tracking and (b) latching.
13-77
CHUNG-YU WU
* Advantages:
(a) Currents are summed to drive the latch (i.e. Iin L + Iin R) The input
signal has very little effect after latching begins.
(b) Iin L and Iin R always flow from tracking to latching The folders are
little disturbed.
* Need the second-stage buffer and latch.
(2) Second stage:
13-78
CHUNG-YU WU
SR
latch
Fig. 16. (a) ADC block diagram with detail of coarse ADC. (b) Coarse ADC
waveforms
13-79
CHUNG-YU WU
9. Measurement results:
13-80
CHUNG-YU WU
13-81
CHUNG-YU WU
13-9 Summary
16
[7]
[5]
Resolution (Bits)
15
[8]
[4]
14
[3]
13
[2]
12
[6]
[9]
11
10
9
8
[1]
10
30
600
620
13-81
CHUNG-YU WU
320 330
210
190
Conversion Rate (KHz)
Resolution versus sampling frequency plot of
recently reported CMOS audio A/D converters
50
13-82
13
12
11
Resolution (bits)
(35mW) (135mW)
T3, [20] [18], T2
(85mW)
T3 & T6,
[21]
*
[35] (195mW),*T2
[36] [22]
T2, T2,
(75mW) (135mW)
[17]
(350mW,
T2)
: 3.3V
: 3V
: 2V
: 2.5v
(900mW)
[19], T3
*
(76mW, T6)
[11]
T4&T5
T5
(135mW) (80mW) (1.1W, T3)
[23]
[25] [10]
*
[13]
(250mW, T1)
*
[16]
(200mW, T2)
*: 5V
*[34] (250mW), T3
[24], T3
(135mW)
10
CHUNG-YU WU
* [30] (166mW), T3
(200mW, T2)
[15] [33] (335mW), T3
[14]
(600mW, T2)
*
T4
(160mW)
[27]
T1, [28]*
(307mW)
(225mW)
[29], T5
T1
(110mW)
[26]
*[12]
[31]
(200mW)
T4&T5
(400mW, T1)
5
10
20
30
40
50
60
70
80
Conversion Rate (MHz)
90
T1
T3&T7
(190mW) (225mW)
[32]
[37]
125
175
200
400
500
13-82
CHUNG-YU WU
Resolution versus sampling frequency plot of recently reported CMOS video A/D converters
300
13-83
CHUNG-YU WU
[1]
H. Ondera, T. Tateishi, and K. Tamaru, "A cyclic A/D converter that does not require ratiomatched components," IEEE J. Solid-State Circuits, vol. 23, pp. 152-158, Feb.1988.
[2]
P. W. Li, M. J. Chin, P. R. Gray, and R. Castello, " A ratio-independent algorithmic analog-todigital conversion technique," IEEE J. Solid-state Circuits, vol. SC-19, pp.828-836, Dec.
1984.
[3]
H. S. Lee, " A 12-b 600Ks/s digitally self-calibrated pipelined algorithmic ADC," IEEE J.
Solid-Dtate Circuits, vol. 29, no. 4, pp. 509-515, Apr. 1994.
[4]
Shu-Yuan Chin and Chung-Yu Wu, "A ratio-independent and gain insensitive algorithmic
analog-to-digital converter," 1993 IEEE International Symp. on Circuits and Systems,
Chicago, U.S.A., pp.1200-1203, May 3-6, 1993.
[5]
M. de Wit, K. S. Tan, R. K. Hester, " A low-power 12-b analog-to-digital converter with onchip precision trimming," IEEE J. Solid-State Circuits, vol. 28, no. 4, pp. 455-461, Apr. 1993.
[6]
G. Yin, F. Stubbe, and W. Sansen, " A16-b 320-KHz CMOS A/D converter using two-stage
thrid-order noise shaping," IEEE J. Solid-State Circuits, vol. 28, no. 6, pp. 640-647, June
1993.
[7]
B. Ginetti, P. G. A. Jespers and A. Vandemeulebroecke, " A CMOS 13-b cyclic RSD A/D
converter," J. Solid-State Circuits, vol.27, no. 7, pp.957-964, July 1992.
[8]
H. S. Lee, D. A. Hodeges, and P. R. Gray, " A self calibrating 15-bit CMOS A/D converter,"
IEEE J. Solid-State Circuits, vol. SC-19, pp.813-819, Dec. 1984.
[9]
T. Ritoniemi et al, " A stereo audio sigma-delta A/D converter," IEEE J. Solid-State Circuits,
vol. 29, no. 12, pp.1514-1523, Dec.1994.
[10] C. S. G. Conroy, D. W. Cline, and P. R. Gray, " An 8-b 85-Ms/s parallel pipeline A/D
converter in 1-um CMOS," IEEE J. Solid-State Circuits, vol.28, no. 4, pp.447-454, Apr. 1993.
[11] Shu-Yuan Chin and Chung-Yu Wu, "A 3 V 8-bit 50-Msample/s A/D Converter," submitted to
IEEE J. Solid-State Circuits.
[12] H. Reyhani and P. quinlan, " A 5V 6-b 80Ms/s BiCMOS flash ADC," IEEE J. Solid-State
Circuits, vol. IEEE J. Solid-State Circuits, vol. 29, no. 8, pp.873-878, Aug. 1994.
[13] M. J. M. Pelgrom, A. C. J. V. Rens, M. Vertreg, and M. B. Dijkstra, " A 25-Ms/s 8-bit CMOS
A/D converter for embedded application," IEEE J. Solid-State Circuits, vol.29, no. 8, pp.879886, Aug. 1994.
13-84
CHUNG-YU WU
[14] M. Ishikawa and T. Tsukahaara, "An 8-bit 50-Mhz CMOS A/D converter," IEEE J. SolidState Circuits, vol. 24, no. 12, pp. 1485-1491, Dec. 1989.
[15] B. Razavi and B. A. Wolley, "A 12-b 5-Msample/s two-step A/D converter," IEEE J. SolidState Circuits, vol. 29, no. 12, pp.1667-1678, Dec. 1992.
[16] A. G. F. Dingwall and V. Zazzu, " An 8-MHz CMOS subranging 8-bit A/D converter," IEEE J.
Solid-State Circuits, vol. Sc-20, no. 6, pp. 1138-1143, Dec.1985.
[17] J. Doernberg, P. R. Gray and D. A. Hodges, " A 10-bit 5-Msample/s CMOS two-step flash
ADC," IEEE J. Solid-State Circuits, vol. 24, no. 2, pp. 241-249, Apr.1989.
[18] M. Ito et al., " A 10bit 20 Ms/s 3V supply CMOS A/D converter," IEEE J. Solid-State
Circuits, vol. 29, no. 12, pp.1531-1536, Dec. 1994.
[19] M. Yotsuyanagi, T. Etoh, and K. Hirata, " A 10-b 50-MHz pipelined CMOS A/D converter
with S/H," IEEE J. Solid-State Circuits, vol. 28, no. 3, pp. 292-300, Mar. 1993.
[20] T. B. Cho, P. R. Gray, "A 10 b, 20 Msample/s, 35 mW pipelined A/D converter," IEEE J.
Solid-State Circuits, vol. 30, no. 3, pp. 166-172, Mar. 1995.
[21] K. Nakamura, M. Hotta, L. R. Carley, and D. J. Allstos, "An 85 mW, 10b, 40 Msample/s
CMOS parallel-pipelined ADC," IEEE J. Solid-State Circuits, vol. 30, no. 3, pp. 173-183,
Mar. 1995.
[22] M. Yotsuyanagi et al., "A 2 V, 10 b, 20 Msample/s, mixed-mode subranging CMOS A/D
converter," IEEE J. Solid-State Circuits, vol. 30, no. 12, pp.1533-1537, Dec. 1995.
[23] B. Nauta and A. G. W. Venes,"A 70-Ms/s 110mW 8-b CMOS folding and interpolating A/D
converter," IEEE J. Solid-State Circuits, vol. 30, no. 12, pp. 1302-1308, Dec. 1995.
[24] P. C. Yu and H. S. Lee, "A 2.5-V, 12-b, 5-Msample/s pipelined CMOS ADC," IEEE J. SolidState Circuits, vol. 31, no. 12, pp. 1854-1861, Dec. 1996.
[25] A. G. W. Venes and R. J. van de Plassche, "An 80-MHz, 80-mW, 8-b CMOS folding A/D
converter with distributed track-and-hold preprocessing," IEEE J. Solid-State Circuits, vol. 31,
no. 12, pp. 1846-1853, Dec. 1996.
[26] S. Tsukamoto et al., "A CMOS 6-b, 200 Msample/s, 3 V-supply A/D converter for PRML
read channel LSI," IEEE J. Solid-State Circuits, vol.31, no. 11, pp. 1831-1836, Nov. 1996.
[27] R. Roover and M. S. J. Steyert, "A 175 Ms/s, 6 b, 160mW, 3.3 V CMOS A/D converter,"
IEEE J. Solid-State Circuits, vol.31, no. 7, pp. 938-944, July 1996.
13-85
CHUNG-YU WU
[28] C. L. Portmann and T. H. Y. Meng, "Power-efficient metastability error reduction in CMOS
flash A/D converters," IEEE J. Solid-State Circuits, vol. 31, no. 8, pp. 1132-1140, Aug. 1996.
[29] M. P. Flynn and D. J. Allstot, "CMOS folding converter with current-mode interpolation,"
IEEE J. Solid-State Circuits, vol. 31, no. 9, pp. 1248-1257, Sep. 1996.
[30] D. W. Cline and P. R. Gray, "A power optimized 13-b 5 Msamples/s pipelined analog-todigital converter in 1.2/spl mu/m CMOS," IEEE J. Solid-State Circuits, vol. 31, no. 3, pp.
294-303, Mar. 1996.
[31] M. P. Flynn and B. Sheahan, "A 400-Msample/s, 6-b CMOS folding and interpolating ADC,"
IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 1932-1938, Dec. 1998.
[32] S. Tsukamoto, W. G. Schofield, and T. Endo, "A CMOS 6-b, 400-Msample/s ADC with error
correction," IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 1939-1947, Dec. 1998.
[33] J. M. Ingino and B. A. Wooley, "A continuously calibrated 12-b, 10-Ms/s, 3.3-V A/D
converter," IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 1920-1931, Dec. 1998.
[34] I. E. Opris, L. D. Lewicki, and B. C. Wong, "A single-ended 12-bit 20 Msample/s selfcalibrating pipeline A/D converter," IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 18981903, Dec. 1998.
[35] H. van der Ploeg and R. Remmers, "A 3.3-V, 10-b, 25-Msample/s two-step ADC in 0.35-um
CMOS," IEEE J. Solid-State Circuits, vol. 34, no. 12, pp. 1803-1811, Dec. 1999.
[36] B. P. Brandt and J. Lutsky, "A 75-mW, 10-b, 20-MSPS CMOS subranging ADC with 9.5
effective bits at nyquist," IEEE J. Solid-State Circuits, vol. 34, no. 12, pp. 1788-1795, Dec.
1999.
[37] I. Mehr and D. Dalton, "A 500-Msample/s, 6-bit nyquist-rate ADC for disk-drive readchannel applications," IEEE J. Solid-State Circuits, vol. 34, no. 12, pp. 912-920, Dec. 1999.
14-1
CHUNG-YU WU
Ampt.
Input x(t)
Ampt.
Input x(kt)
Loss
Ampt.
Input x(kt)
Loss
t
Output y(t)
Output y(kt)
Output y(kt)
continuous-time system
e.q.: analog Filter
k: integer
sampled-data system
e.q.: SCF
discrete-time system
e.q.: digital filter
difference equations
differential equations
H(s)=
K p
H ( j )
dB
-N*20dB/decade
N: order
S 2 + ( p / Q p ) S + p2
Ideal
(biquad)
Two complex poles (LHP)
14-2
CHUNG-YU WU
(2) High-Pass(HP)
KS 2
H(s)= 2
S + ( p / Q p ) S + p2
Two complex poles(LHP)
Two zeros at S=0
H ( j )
3) Band-Pass(BP)
H(s)=
K ( p / Q p ) S
p
Qp
dB
-N*10dB/decade
N: order
-3dB
S 2 + ( p / Q p ) s + p2
+N*10dB/decade
N: order
s1
p1
p2
s2
H ( j )
4)Band-Reject(BR)
K ( S 2 + z2 )
H(s)= 2
S + ( z / Q p ) s + p2
dB
p=z
Two complex poles(LHP)
Two imaginary zeros
H ( j )
dB
dB
0dB
0dB
p z
14-3
CHUNG-YU WU
S 2 ( p / Q p ) S + p2
S 2 + ( p / Q p ) S + p2
0dB
Gain
-180o
phase
p
multiplier
x(t)
S (t k )
xd(t)
k =
: sampling period
xd(t)=x(t)S (t)=x(t)
remember:
(t k )=
K =
x(t ) (t k )
k =
(t k )dt = 1 (t k ) =0 for t k
Where Ck
s(t) e jk st dt=
>xd(t)=x(t)SF(t)= Ck x(t )e jk t
s
k =
F[xd(t)]=F[ Ck x(t )e
jk s t
k =
= C k X(j-jks)
]=
C F [ x(t )e
k =
jk s t
k =
base-band spectrum
14-4
CHUNG-YU WU
X(j)
Aliasing:
introduces an
ambiguity into
X(j-jks)
and prevents
the eventual
recovery of
X(j)
sc
c
X(j-jks)
c s
X(j-jks) no
s<2c
2c
s>2c
aliasing
s 2
c
2c s
Sampling Theorem:
A function x(t) that has a Fourier spectrum X(j) such that X(j)=0 for
Transition
band
Stop
band
Pass
band
s+c c
s-c
s-2c
14-5
CHUNG-YU WU
a
2
a
2
Sp(t)= [u (t k ) u (t k + )] a>0
k =
Ck=
a
2
a
Sp(t) e jk st dt
e jk t dt =
s
a Sin(k s a / 2
k s a / 2
2 3 4
xd(t)
k s a / 2
3 4
14-1.3 Z-Transformation
xd(t)= x(k ) (t k )
k =
Let z=es
j
S=j z=e
X(z)= X (k )z k
one-sided z-transform
k =0
1
1 z 1
z >1
1
1 e
z 1
for z >e-a
n =1
n =0
14-6
CHUNG-YU WU
n =1
n =0
Y(z)(1+ bn Z n ) =X(z) a n z n
M
Y ( z)
H(z)=
=
X ( z)
a
n =0
N
z n
1 + bn z
n =1
ao (1 1 Z 1 )(1 2 Z 1 )......(1 N Z 1 )
=
(1 1 Z 1 )(1 2 Z 1 )........(1 N Z 1 )
z=i: poles
z=i: zeros
=>
z=e ej
s
s / 2 is
2
s
s / 2 , << => all Z-plane Z =
2
3
s s , << => overlap on Z-plane Z = 3
2
2
s
3
s , << => overlap on Z-plane Z = 3
2
2
*<0
14-7
CHUNG-YU WU
* S=0
z=1
1
Z=a is the pole
1 az 1
stable region
ImZ
(5)a=1
(6)a<1
unstable
z=ej
2
1
Ro Z
Z =1
G()=20log[ H (Z ) z=ej ] dB
Im H ( Z )
stable <0, =
k=k
unstable
()=tan-1 Re H ( Z )
rad
magnitude
phase
The magnitude and phase can be determined graphically in the same way as
those determined from the s-plane poles & zeros.
1 e s
s
sin( / 2)
Ho(j)=e-j/2 / 2
14-8
CHUNG-YU WU
h0(t)
X d ( j )
2 S
1/
H 0 ( j )
X r ( j )
+ C
2 S
Impulse response
H O ( jw)
S
2 S
2 S
x(t)
xr(t)
x(k)
xr(t)=x(t) h0(t)
14-9
CHUNG-YU WU
Block diagram:
(S/H)i
Continuous
Anti-aliasing
Filter
SwitchedCapacitor
Network
Continuous
Reconstruction
Filter
(S/H)o
Switched-Capacitor Network
(Two-phase clock) (can be multi-phase)
General symbols:
e
V1 ( kT )
V2 ( kT )
V1 (kT )
V2 (kT )
V1 (kT )
V2 ( kT )
even clock
Tc
Tc
Tc<T
to avoid overlapping
of e and
1T
2T
3T
odd clock
Tc
: sampling period
Tc
=2T
* Generally, SCN is time-variant since the network topology is different in the case of
e and . However, if we separate the input/output sampled-data voltage into one
even component and one odd component and separate the whole SCN into one
even part and one odd part, then we have two time-invariant networks coupled
together. Analysis thus can be performed.
14-10
CHUNG-YU WU
Sampled-Data Waveforms
1. Return-to-zero waveforms
va
va
1T
0T
V (t )
2T
e
4T
3T
5T
0T
va
1T
2T
3T
4T
5T
1T
2T
3T
4T
5T
Va (t )
Vb (t )
0T
V (t )
Va0 ( z ) =0
Vbe (z ) =0
vc
vc
vc (t)
1T
2T
3T
4T
5T
V (z)=Z
1
2
2T
3T
4T
5T
1T
2T
3T
4T
5T
1T
14-11
CHUNG-YU WU
e
d
1
2
V (t )
or
vc , vd
TransitionBand
TB
Gain
dB
Start
S : PB _ ripple
Specification
S
Stopband
SB
Passband
PB
SB
attenuation
No
O S
Cutoff frequency
Stopband frequency
Satisfied
?
Yes
Approximation
Satisfied
?
No
Yes
Realization
delay
sec
Satisfied
?
Yes
Stop
actual delay function
No
14-12
CHUNG-YU WU
SB H
SP
TB L
SL
CL
PB
TB H
CH SH
2.Approximation
(1) Classical approximation
a. Butterworth
b. Chebyshev
c. Elliptic
d. Bessel
(2) Modern approximation
3.Realization
Two methods:
(1) Realization of the biquad (2nd order filter)and the first-order filter>cascade
or couple them to form a high-order filter.
(2) Realize H(s) using LC network>replace L by some integrated-circuit
simulator or simulate the LC network using integrators.
* Low-sensitivity, high-performance
14-13
CHUNG-YU WU
o(e): Vc1=0
e(o): Vc1=V1 -V2
Q=C1(V1-V2)
e ( o )
V1
V V2
V V2
Q
i = C1 1
= C1 f (V1 V2 ) 1
T
T
R
1
f: clock frequency
>R=
C1 f
VC1
e ( o )
V2
C1
o ( e )
o ( e )
f=100KHz, C1=10PF
> R=1M
Switch realizations:
o ore
o ore
o ore
or
+ V DD
VSS
VSS
o ore
E/D NMOS
vin
Operation:
(1)o phase
vout
vin
e
o
C1
C2
vout
14-14
CHUNG-YU WU
C2
+
+
vin
C1
vout
(2)e phase
+
+
+
+
+
+
vin
C1
C2
vout
e
n 1
n +1
t
vin
+ 1V
t
vout
0V
vout (Tn )
{
vout (Tn 1 )
{
C1
(1V )
C2
vout (Tn+1 )
t
{
14-15
CHUNG-YU WU
"Ideal OP AMP"
Vout(Tn)=Vc2(Tn)=Vout(Tn-1)=>
=>
C1
Vin(Tn)
C2
C2 1
C1 f
Z-domain Expression:
Vout (z)=Vout(z)Z-1
>H(z)
C1
Vin(z)
C2
Vout ( z )
(C C )
= 1 21
(1 Z )
Vin ( z )
1 Z 1
T
1
1
=
(C 2 / C1 )TS
R1C 2 S
Parasitic-Free structure:
vin
C P1
C1
C P 2 C P3
e
CP4
C2
C P5
vout
C P6
14-16
CHUNG-YU WU
i
e ( o )
CV
+V
If V2=0 >i= 1 1 = 1
T
R
1
T
> R= =
C1
C1 f
VC1
V1
o ( e )
V2
C1
o ( e )
e ( o )
vin
vout
vin
e
o
o
C1
Operations:
(1)e phase
C2
vout
(2) o phase
C2
vin
+
+
C1
Vout (Tn)=Vout(Tn-1)+
>
>
vout
vin
C1
Vin (Tn1 )
C2
d
1
Vout =
Vin
dt
R1C 2
Vout
1
1
=
(s) H (s) =
Vin
R1C 2 S C 2 1
S
C1 f
+
+
C1
C2
+
+
vout
14-17
CHUNG-YU WU
Z-domain expression:
C1
)
Vout ( z )
C2
=
H(z)
Vin ( z ) 1 Z 1
Z 1 (
H(s) +
(
C2
)TS
C1
=+
1 Z 1
TZ 1
1
R1C 2 S
e
V BIAS
vin
V BIAS
vin
C
+
vout
vout
C
C
14-18
CHUNG-YU WU
Vin
Vout
Inverting:
o
C
Vin
C1
Vout(Tn)=Vout' (Tn)=
>H(z)=
V'out
Vout
C1
[Vin (Tn ) Vin (Tn 1 )]
C
C1
(1-Z-1)
C
Backward-Euler Transformation: S
H(S)=-S
C1
C 1
T = S 1 = SRC1
C
C f
1 Z 1
T
1
R=
cf
Noninverting:
Vin
C1
CC
CC
Vout
14-19
CHUNG-YU WU
o
2
C1
v out
v out
H(z)=+
C1
(1 Z 1 )
C
o
Differential-Type SC Differentiator:
o
vin
vin
e
e
C1
C1
C
+
vout
v out
o
Characteristics of SC differentiators:
1. Parasitic-free structure.
2. No dc instability problem as in SC integrators.
3. No high-frequency-noise problem as in continuous-time differentiators.
4. Can be used to design filters as SC integrators.
Ref: IEEE JSSC vol.sc-24, pp.177-180, 1989.
14-20
CHUNG-YU WU
(K 2 S 2 + K 1 S + K o)
o
S + 02
Q
S2 +
Vout (s)
Vin (s)
>Vout=- [(K1+K2S)Vin+(
S
2
+ 0 ) Vout
Q
Wo
) Vout+ o V1)
Q
1
S
Vin
K0
0 Q
1
S
Vout
V1
0
K1 + K 2 S
CA = 1
Vin
K0
Q 0
0
1
+
1
K1
K2
CB = 1
Vout
14-21
CHUNG-YU WU
Step 3: SCF
C2
CA=1
2
Vin
C4
C1
C3
OP1
+
C1'
CB=1
OP2
+
Vout
C1"
1
x
Adc
Ko
C2 = C3=o * T=
1
x
C4 = (o * T/Q)=
C
1
Q
= A (not suitable for high Q)
>
Qx
oT C 4
C1'= K1 * T =K1
C1" = K2
1
CA/C2=
oT
X=
1
oT
o x
> fo=
fs
fo: center (cutoff) frequency
2x
Step 4: refinement
Z-domain block diagram (If the accuracy is not good, change to Z-domain diagram)
-C2Z-1
C4
Vin
-C1Z-1
-1/CA
C3
1-Z-1
C1'+C1"(1-Z-1)
-1/CB
1-Z-1
Vout
14-22
CHUNG-YU WU
C1" = a0
C1' = a2-a0
C1 = 1/C3 * (a0+ a1+ a2)=
1
(2C1"+C1'a1)
C3
C4 = b2 -1
C2 * C3 = b1 + b2 + 1
C2=C3
In this diagram, each op-amp and its feedback capacitor (CA or CB) is replaced by
its voltage-to-charge transfer function.
Qout ( z )
V ( z) C
1 / Cf
=
= out
1
1 z
Vin ( z )
Vin ( z )
Here Cf is the feedback capacitor.
Similarly,
C * (1-z-1) for an unswitched capacitor (e.g. C1")
C
for a non-inverting capacitor (C1', C3, C4)
-1
for an inverting capacitor (C1, C2)
-C * z
From the block diagram, the exact transfer function is
Vout ( z )
(C1 '+C1 " ) z 2 + (C1C3 C1 '2C1 " ) z + C1 "
=
Vin ( z )
(1 + C 4 ) z 2 + (C 2 C3 C 4 2) z + 1
As compared to H(z) specifications, the capacitances can be determined.
a 2 * z 2 + a1 * z + a0
H(z) = b2 * z 2 + b1 * z + 1
TYPES
L-P CASE
B-P CASE
H-P CASE
NOTCH CASE
COEFFICIENTS
C1'=C1"=0
K1=K2=0 a0=a2=0
C1=C1"=0
K0=K2=0 a0=0,a1=-a2
C1=C1'=0
K0=K1=0 a0=a2= C1'=0
K1=0
a2=a0
a1
2
14-23
CHUNG-YU WU
Vin
S Q
-1 S
K0
0
-0
1
Vout
1
S
Vout = [K2SVin0V1]
V1
K2S
-1 S
1
S
Where V1= [(
2. Active-RC design
K0
K1
S )Vin + ( 0 +
S
)Vou t ]
Q
1
Q
K1
Vin
CA = 1
0
CB = 1
K0
OP1
Vout
OP 2
K2
3. SCF
C2
1
C1
C4
'
CA = 1
vin
C1
CB = 1
C1
''
C3
vout
14-24
CHUNG-YU WU
C1=K0 T/0 = (
K0
) oT = Adc 0T
C2 C3 0T
C4 1
(instead of
Q
)
0T
C1' K1/0
C1" K2
4. Z-domain block diagram of a high-Q biquad:
C2
+
''
C1 (1 Z 1 )
Vin
C1
C 4 (1 Z 1 )
+
C 3 Z 1
1 CA
1 Z 1 V1
1 CB
1 Z 1
''
C1 (1 Z 1 )
a2
b2
C1'=(C1"-
ao
a ao
) / C3 = 2
b2
b2 c3
C1=(a1/b1-C1'C3+2C1")/C3=(a0+a1+a2)/(b2c3)
C4=(1-
1
) /C3
b2
C32=C22=(b1/b2-C3C4+2)=(b1+b2+1)/b2
Vout
14-25
CHUNG-YU WU
C2
C4
CA
vin
C1
CB
H (S ) =
CA=CB=6.3 C1=4
C3
vout
4
S 2 + 1.2 S + 1
f
s
f =
c 2 C
C2
C4
CA
vin
CB
C3
'
1
vout
CA=CB=6.3 C1'=2
H (S ) =
4
S 2 + 1 .2 S + 1
f
s
f =
c 2 C
14-26
CHUNG-YU WU
1
2
C1
Vin
CB
C3
2
1
C4
CA
H (S ) =
CA=CB=6.3 C1=4
Vout
4
S
S2 +
+1
5.25
f
s
fc =
2 C
A
fc: CENTER FRE.
fs: SAMPLING FRE.
Vin
1
2
C'1
C4
CA
2
1
CA=CB=6.3 C '1=2
CB
C3
2
1
1
2
Vout
H (S ) =
2S
S 2 + 1.2 S + 1
f
s
fc =
2 C
A
fc: CENTER FRE.
fs: SAMPLING FRE.
14-27
CHUNG-YU WU
CENTER FREQUENCY: 1K Hz
SAMPLING FREQUENCY: 39.6 Hz
CALCULATED
14-28
CHUNG-YU WU
CALCULATED
CENTER FREQUENCY: 1K Hz
SAMPLING FREQUENCY: 39.6 Hz
COMPUTED BY SWITCH CAP EXPERIMENTAL
14-29
CHUNG-YU WU
CALCULATD
CENTER FREQUENCY: 1K Hz
SAMPLING FREQUENCY: 39.6 Hz
COMPUTED BY SWITCH CAP EXPERIMENTAL
14-30
CHUNG-YU WU
CALCULATED
CENTER FREQUENCY: 1K Hz
SAMPLING FREQUENCY: 39.6 Hz
COMPUTED BY SWITCH CAP EXPERIMENTAL
14-31
CHUNG-YU WU
K1 S + K 0
S + 0
H(z)=
a1 z + ao
b1 z + 1
1. Flow diagram
0
Vin
K0
-1/S
Vout
K1S
2. Active-RC design
1/0
CA=1
1/K0
Vin
Vout
K1
3. SCF
1
C2
C1 K1
C1' TK0
C2 0T
fc=
fs
2x
C'1
1
2
2
CA
Vin
C1
Vout
14-32
CHUNG-YU WU
Vout
(C + C1 ' ) z C1
= 1
Vin
(1 + C 2 ) z 1
C'1
Vin
C1(1-Z-1)
C2
-1 / CA
1 - Z-1
Vout
-V1=
-I2=
1 Vin V1
(
I2 )
SC1
RS
1
(V1 V3 )
SL2
V3=
Loss
Vin
I2
C1
V3
3
C3
+
RL
Vout
-
V
1
( I 2 + 3 )
SC 3
RL
(no loss)
transmission zero
=>
L2
V1
Vin
1/RS
-1
SC1
-V1
-1
+1
-1
SL2
-I2
p
Loss response
+1
+
-1
-1
SC3
1/RL
Flow diagram
+V3
14-33
CHUNG-YU WU
RS
RS
Vin
1
-I2
Active-RC realization
C1
-V1
-1
L2
-
CS
Vin
1
C3
CS
-1
C1
1
Vout
+
C
1
C
RL
L2
SCF
C
C3
1
1
Vout
T
R
=> Cs
T<<1
CL
T
Rs
CT
CL T / RL
Due to the approximation made in finding C values, error still exists which may be
refined by the z-domain analysis.
14-34
CHUNG-YU WU
-V1=
-I2=
1
L2 C 2
Vin V1
1
+
sC
V
I
2 3
2 ,
s (C1 + C 2 ) Rs
1
[V1 V3 ],
sL2
+V3=
V3
1
sC 2V1 I 2 +
s (C 2 + C 3 )
RL
RS
Vin
V1
C2
IC2
L2
I2
C1
V3
3
C3
+
RL
Vout
-
1/RS
Vin
1/RS
-1
-V1
s(C1+C2)
Flow diagram:
SC2
-I2
-1
-1
SL2
-1
SC2
-1
S(C2+C3)
1/RL
+V3
Vout
14-35
CHUNG-YU WU
RS
Active-RC
Realization:
CA=C1+C2
RS
Vin
-V1
-RI2
C2
-R
CB= L2/R2
C2
+
R
CC=C2+C3
-R
Vout
V3
RL
CS
Vin
CS
2
1
SCF:
CA
1
1
C
CB
1
C2
C2
Cs T / Rs,
CA=C1+C2,
CC
C T,
2
CB=L2,
Cc=C2+C3,
CL T / RL .
CL
Vout
14-36
CHUNG-YU WU
RS
Vin
V1
I2
L2
V3
I1
I3
L3
L1
C1
+
C3
Vo
RL
Vin
1/RS
-1
-V1
s(C1+C2)
-V1=
-I1-I2
-I1
-1
-1
-V1
SL1
-I2
-I1=
V1
,
sL1
-I2=
V1 + V3
,
sL2
SC2
VB
VA
VC
-I2
-1
-1
SL2
+
VD
I3=
I3
-1
SL3
-1
-1
S(C2+C3)
V3
V3
I3-I2
1/RL
V3
,
sL3
V3=
SC2
-I2
Vin V1
1
+ sC 2V3 I 1 I 2 ,
s (C1 + C 2 ) RS
Vout
V3
1
sC 2V1 + I 3 I 2 +
s (C 2 + C 3 )
RL
14-37
CHUNG-YU WU
HAB
VB
VA
HCD
VC
VD
sL1
S L1 (C1 + C 2 ) + SL1 / Rs + 1
sL3
S L3 (C 2 + C 3 ) + SL3 / RL + 1
14-38
CHUNG-YU WU
-V1=
Vin V1
1
+ sC 2V3 I (11) ,
s (C1 + C 2 ) Rs
-I(1)
1 ( I1 + I 2 ) =
V3=
1
sL12
L1V3
V1
,
L1 + L2
V3
1
,
sC 2V1 I (33) +
s (C 2 + C 3 )
RL
-I(3)3 I3-I2=
1
sL12
L1V1
,
V3 +
L1 + L2
Where L12 L1 L2 = L1 L2 /( L1 + L2 )
14-39
CHUNG-YU WU
14-40
CHUNG-YU WU
SCF:
14-41
CHUNG-YU WU
(1 z )
(z 2 z 2 )2
Ton z=ejT
> H(ejT)=
+K
4 sin 2 (T / 2)
1 12
T
If
is used > Sa= ( z z 2 )
2
T
1
T
> a=
Sin( )
T /2
2
2.The state equations of the LCR circuit are found. The
signs of the voltage and current variables must be chosen
such that inverting and noninverting integrators alternate in
the implementation. If inductor loops exit, the inductive node
currents can be used.
14-42
CHUNG-YU WU
2
T
z 1
z +1
(1)jaaxis>unit circle
(2)preserves the flatness of PB and SB
T 2
4L2
V1 + Vin
s
C
V
I
a 2
3
2 ,
'
Rs
S a (C1 + C 2 )
1
-I2= s a C L 2
[V1 V3 ] ,
s
L
a 2
V3=
V
1
s a C 2 V1 I 2 + 3 .
s a (C 2 + C 3)
RL
14-43
CHUNG-YU WU
Flow diagram
1 S a L2 C L 2
1 ( S a T / 2) 2
1
=
=
H(Sa)=SaCL2S a L2
S a L2
S a L2
14-44
CHUNG-YU WU
Qin (Sa)=
Qin (z)=
1
1
Vin
Rs
Sa
T z + 1 Vin ( z )
2 z 1 Rs
> (1-z-1)Qin =
T
(1+z-1)Vin(z)
2 Rs
qin(tn)-qin(tn-1)=
SC realizations:
Cs
[Vin(tn)+Vin(tn-1)]
2
CS/2
2
Vin
CS
CP
Virtual
ground
Cs Cs
:
[V in (t n ) V in (t n 1 )]
2 2
Cs : Cs Vin (tn-1)
-CS/2
2
CS
Virtual
ground
Cs
C
: s [Vin (t n ) Vin (t n 1 )]
2
2
Cs: CsVin(tn)
Cs
[Vin(tn)+Vin(tn-1)]
2
* Stray insensitive.
(c)The branches SaC
Q
1
= CS a
=C
V
Sa
(d) The blocks -
Only a C is required.
1
SaC
Q
= C
V
14-45
CHUNG-YU WU
Q(z)=(1-z )Q(z)=
4C L 2
(V3 V1 )
z 1
4C L 2 / C 2
Q( z ) 4C L 2 z 1
1
)(C )
=
= (Cz )(
V3 V1 1 z 1
1 z 1
Realizations:
-V1
1
Virtual
ground
C2/4CL2
C
2
C
1
2
Q
Virtual
ground
V3
14-46
CHUNG-YU WU
SCF:
2
CS / 2
Vin
CS
CS
CA
2
2
C
CB
C
2
+
C'2
C
CC
1
2
2
C'2
CL
Vout
14-47
CHUNG-YU WU
C3
2
LC prototype
Circuit:
V
I2
L1
C2
V2
V3
IL2
L2
IL3
L3
C2
I2
-V2
I2=(SC1+
V
1
1
) (V1-V2)+(SC3+
) (V3-V2)- 2
SL1
SL3
SL2
Note that
1 ( S a T 2) 2
is realizable !
Sa L
>I2(S)=S[(C1+CL1)V1+(C1+C3+CL1+CL3)(-V2)+(C3+CL3)V3]
1
S
+(
T 2s
) [1V1+(1+2+3)(-V2)+ 3V3]
4
1
T2
, i=
Where CLi
Li
4 Li
First Term:
Q2'(S)=(C1+CL1)V1+(C1+C3+CL1+CL3)(-V2)+(C3+CL3)V3
Can be realized by unswitched capacitors.
Second Term:
T z +1 2 T 2
) ] [1V1+(1+2+3)(-V2)+ 3V3]
Q2"(Z)=[(
2 z 1
4
T 2 z 1
=
[1V1+(1+2+3)(-V2)+ 3V3]
(1 z 1 ) 2
14-48
CHUNG-YU WU
-V2
C4
C5
V3
LC prototype circuit:
C1
C6
C3
V2
V3
V1
L1
C2
L2
L3
C8
C7
Q2"(z)
Vitrual
ground
SC realization:
Design equations:
CL1=T2/(4Li)
c1=C1+CL1
c2=C1+C2+C3+CL1+CL2+CL3
c3=C3+CL3
c4= 4
c3
V1
c2
c8
C L1
c7
c
c5= 4 8 (C L1 + C L 2 + C L 3 )
c7
c6= 4
c1
Vt=-V2
c5
c4
c8
CL3
c7
c7, c8 arbitrary
c7
c8
Vb
V3
c6
14-49
CHUNG-YU WU
RS
C1
Vin
L1
V2
L2
SC realization:
c1
Vin
c2
c8
c3
c4
-V1
c5
V2
c9
Design equations:
C Li
c7
c6
T2
4 Li
, Cs
T
Rs
Cs
,
c2=c3=C9
2
c4=C1+C2+CL1+CL2-CS/2
c1=
c5=4
c6
(C L1 + C L 2 )
c7
c8=C2+CL2
c9=4
c6
CL 2
c7
c6, c7 arbitrary
14-50
CHUNG-YU WU
LC prototype
circuit with RL:
C1
VN
VL
C2
L1
L2
RL
SC realization:
c1
c3
c4
-VL
VN
Design equations:
CL1
T2
T
, CL
RL
4 Li
c5
c2
c1=C1+CL1
c2=4
c6
C L1
c7
c3=CL
c4=C1+C2+CL1+CL2-CL/2
c
c5= 4 6 (CL1+CL2)
c7
c6, c7 are arbitrary
c7
c6
14-51
CHUNG-YU WU
Z-domain verifications:
Upper OP AMP:
C1(1-z-1)V1+C3(1-z-1)V3+C2(1-z-1)Vt+C7Vb=0
Lower OP AMP:
-C4z-1V1C6z-1V3-C5z-1Vt+C8(1-z-1)Vb=0
Vt=-
>
N 1V1 + N 3V3
D
C 4 C7 1
z ]
C1C8
N3(z)=C3C8[(1-z-1)2+
C6 C7 1
z ]
C 3 C8
D(z)=C2C8[(1-z-1)2+
C5C7 1
z ]
C 2 C8
* All poles and zeros of the transfer functions Vt/V1, Vt/V3, Vb/V1, and Vb/V3
are located on the unit circle.
After the bilinear s-to-z transformation,
Vt=
1 S
S ( )[(C 2 C 4 C1C5 )V1 + (C 2 C6 C3C5 )V3 ]
Vb= T 2
(C 2 C8 C5C7 / 4) S 2 + C5C7 / T 2
* The phase shift between Vt and V1, as well as between
Vt and V3 are either 0 or 180 for s=j
>The same as for the LC prototype regardless of the
element values Ci.
>Can simulate a lossless LC with the same low
sensitivity.
14-52
CHUNG-YU WU
* It can also simulate the behavior of any LC ladder section which has a T
configuration.
V1
V2
C1
High-pass
V3
C3
L2
C2
L1
Low-pass
L3
L2
C2
Vt=-V2
> V2=
* High-Pass Case :
c 2 / T
=
2
2
If the loss is zero (i.e. passband),
At Z=ejT =-1
, i.e. =
=>(1-z-1)Qin(z)=
T
(1+z-1)Vin(z)
2 Rs
=0
Qin(z)=0, but loss is zero
>The other part of the circuit
should have an infinite gain.
>unstable.
Rs input (i.e. input termination) is a problem!
* Inductor loop is O.K.
14-53
CHUNG-YU WU
14-10.3 Comparisons
LDI Realizations of Ladder Filters using SC Integrators
(1) Prewarping is required
(2) Inductor loop exists
>Modified design
>Component sensitivity
Bilinear Realizations of Ladder Filters using SC Integrations
(1) Prewarping is not required.
(2) Low-pass, band-pass ladder filters are O.K.
But they are not fully stray insensitive.
(3) Can't realize high-pass or band-reject filters.
> Instability exists.
(4) Some modifications are proposed.
But they are not fully stray insensitive.
V1
F1
Q1
F7
V2
F2
Q2
Q4
F4
Vj
F5
Q5
V3
F3
OAj
Vi
F8
Q3
OAi
F6
A
Q6
SC filter section.
OAk
Vk
14-54
CHUNG-YU WU
Let all branches connected to the output terminal of OAi be modified such that
their Q / V transfer functions F4, F5, and F6 are multiplied by a positive real constant
factor k. This can be achieved simply by multiplying all capacitors in these branches
by ki.
Since the input branches and their voltages were left unchanged, the change
flowing in the feedback branch is
Q4(z)=- Q1(z)- Q2(z)- Q3(z) remains at its original value.
> V2.'(z)= Q4(z)/[kiF4(z)]=Vi(z)/ki
The old output voltage of OAi
Vi ( z)
=F5(z)Vi(z)= Q5 ( z )
ki
Voltage scaling does not change charge flowing from the scaled branch
to the rest of the circuit.
>Only Vi/ki, all other voltages or changes are not affected.
Optimization of the dynamic range using scaling
V1
V2
V3
F1
F4
F2
Vj
F5
OAn
F3
OAi
Vin
F6
A
Vn
Vn
Vout
14-55
CHUNG-YU WU
since VP5/VP2<1
k2=VP2/VP5
14-56
CHUNG-YU WU
Let the transfer functions Fj(z) Q j / V j of all branches connected to the input
terminal of OAi be multiplied by a positive real constant Mi => CimCi
Qn
Vi'=
Q4 ' mi Q4 Q4
=
=
= Vi
F4 '
mi F4
F4
Vi unchanged!
14-57
CHUNG-YU WU
op-amp i.
(b) Multiply all capacitors in Si by mi=Cmin/Ci, min.
(c) Repeat for all sets Si.
* Scaling for optimum dynamic range may also reduce the sensitivity to finite
op-amp gain effects.
Y
V1
V2
V3
Y1
Y2
Y3
vout
Y0
(a)
(Y+Y0+Y1+Y2+Y3+...)/A
Y
V2
V3
Y2
Y3
vout
V1
Y1
(b)
The influence of finite op-amp gain: (a) actual circuits; (b) equivalent circuits.
3. The block diagram or signal flow graph (SFG) is constructed from the state
equations. It is then transformed (directly or via the active-RC circuit) into the
SCF.
4. If necessary, additional circuit transformations can be performed to improve the
response of SCF.
14-58
CHUNG-YU WU
Stopband:
0 to fp=1kHz
passband ripple p 0.05dB
(Maximum allowable passband gain variation)
fs 1.5KHz to fc/2
Minimum stopband loss s 38dB
(Maximum allowable gain value)
Sampling frequency:
1
T
fc= =50KHz
Design Procedures:
1.S-domain transfer function H(s)
Frequency prewarping
ap=
T
2
tan p =6291.4667 rad/s
T
2
as= 2 tan T
s
Selectivity parameter
k
ap
0.6656
as
S 2 a + 1
0.068
)(
)
(Sa)=(
S a + 0.78140011 S a 2 + 0.96934556S a + a1 2 + b1 2
(-2 a1 )
(- a 0 )
2
S a + 2
)
2
2
2a 2 S a + a 2 + b2
2
Sa
14-59
CHUNG-YU WU
1
H(ejT)
fc/2
fp
1
vs. f
H(ejT)
0ffc/2
14-60
CHUNG-YU WU
1
H(ejT)
vs. f
0 f f p
fp
3. SC realization
(1) H0(z)=
z +1
z 0.9063
CD
Vin
+
CS
2
H0(z)=-
-1/CE
Vout
1-Z-1
(1+Z-1)
1
CS/2
Vin
CS
Cs / 2
z +1
C D + C E z C E /(C D + C E )
CD
CE
A1
z 2 + C1 z + 1
(2) H1(z)=
(1 / f1 ) z 2 + (e1 / f1 ) z + 1
Vout
(a + b1 )
Q1= 1
2 a1
0.99 Low-Q
14-61
CHUNG-YU WU
C1=(a0+a1+a2)/C3 0.30358,
C4=b2-1=1/f1-1 0.12939,
CA=CB=1.
(3) H2(z)=
z 2 + C2 z + 1
( 1 ) z 2 + ( e2 f 2 ) z + 1
f2
(a + b2 )
Q2= 2
2 a2
4.33 =>High-Q
C1 ' = (a1 a 0 ) / b2 c3 = 0,
C 2 = C 3 = (1 + b1 + b2 ) / b2 =
f 2 + e2 + 1 0.13795,
C1=(a0+a1+a2)/b2C3=(2+c2)f2/C3 0.58645,
C4=(1-1/b2)/C3=(1-f2)/C3 0.22873.
(4)Overall SCF
* Ho (low-pass linear section) is placed first
=>High-frequency out-of-band signals and input noise can be attenuated.
The antialiasing filter preceding the SCF has a lower requirement.
* H2 (high-Q section) is placed to the center=>good signal-to-noise ratio
CD
CS/2
Vin
1 CS
2
CE
2
C4
2 C1
A1
C2
CA
A2
CB
C3
2
A3
C1"
SECTION 1
SECTION 2 (HIGH Q)
C2
2
A
1
C4
CA
C1
C3
A4
CB
C 1"
SECTION 3 (LOW Q)
A5
2
2
Vout
14-62
CHUNG-YU WU
4. Scaling
1) Vp1=occurs at dc where H0(1)=-CS/CD=-21.345
(1)We want an overall passband gain of 1. =>Ho(1)-1
=> CD=CS=2, CE 19.345, C1"20.672, C2 12.518
(Multiplying all capacitors connected or switched to the output node
of op-amp A1 by 21.345)
(2)All capacitors at the input node of A1 should be scaled so that the
smallest ( Cs 2 ) equals 1. (O.K.)
2) Vp2 (peak output voltage of op-amp A2) occurs around fp2=1.10kHz
(1) Vp2 177.05 for Vin=1
Reducing Vp1/Vin to 1
=>CA and C3 are multiplied by 177.05=> CA 177.05, C3 24.424.
(2) Vp3 180.80 at 1.07kHz
=>CB,C2, and C4 are multiplied by 180.80=>CB 180.80, C2 24.941,
C4 41.354.
(3) Minimize total capacitance=>C1, C2, C4, and CA at the input
node of op-amp A2 are scaled to make C1=1
=>C1=1, C2 1.9926, C4 3.3036, CA 14.144
(4) Similarly, C1"=1, C3 1.1815, CB 8.7466. (The input of A3)
3) Vp4 503.57 and Vp5 230.14
Thought the same procedures, we have
C A 17.666, C B 7.7286
C1 1.9926, C 2 = 1
C3 2.1116, C 4 = 2
C1 6.3085
"
5 Final Design
Cmin is chosen as 0.5pF => C=1
op amp: gain 70dB bandwidth 3 MHz
passband sensitivity to capacitance variation 0.2dB/1%
14-63
CHUNG-YU WU
L2
L4
RS
Vin
C1
C2
C4
C3
C5
RL
T
f
2
tan p = 2 f c tan p 6291.4667rad / s
T
fc
2
ap
and L0=
1
2
ap
1 1
( (Vin V1 ) I 2 + sC ' 2 V3 ),
sC '1 RS
1
sC L 2 ) (V1V3),
sL2
1
( I 2 sC ' 2 V1 sC 4 'V5 + I 4 ),
sC ' 3
14-64
CHUNG-YU WU
I4=(
1
sC L 4 )(V3 V5 ),
sL4
-V5=
V
1
( I 4 + sC ' 4 V3 5 ),
sC ' 5
RL
1/RS
Vin
-1/sC'1
1/RS
where
CL2=
T
= 0.003278,
4 L2
I4
1-(sT/2)2
sL4
sC'4
T2
CL4=
= 0.0044082,
4 L4
sC'4
-1/sC'5
C'4=C4+CL4=0.46706,
C'3=C3+C'2+C'4=2.10839,
C'5=C5+C'4=1.10408.
Vin
1
2
arbitrarily chosen
Cs=
C
CA=C1+C2+CL2- s = 0.94938,
2
CB=
2
1
CA
A1
Co2
C21
C22
CB
A2
Co3
C
C
= L 2 = 0.0008195,
4C L 2
4
Co4
CC
A3
Co5
Co6
C
C '2
= L 4 = 0.001102,
4C L 4
4
C
CE=C'5- L = 1.041165,
2
T
CL= = 0.12583.
RL
2
Co1
Cc=C'3=2.10839,
CD=
C2
C'=CL4=0.004408
T
= 0.1258293,
Rs
-V5
1/RL
C1
C=CL2=0.003278
V3
-1/sC'3
C'2=C2+CL2=0.15695,
C'1=C1+C'2=1.01230,
SCF:
sC'2
1-(sT/2)2
sL2
-I'2
sC'2
-V1
1
C41
C42
2
Co7
CD
A4
Co8
CE
2
A5
CL
Vout
14-65
CHUNG-YU WU
4.Scaling
Vin=1V, we have:
A1: CA,C2,C21, and C02
multiplied by Vp1
A2: C3,C01, and C03
multiplied by Vp2
Vp1 0.92V,
Vp2 34V,
Vp3 0.764V,
Vp4 28.86V,
Vp5 0.5V,
C1=1.00000
C2=1.83854
C3=2.00000
CA=13.87171
C01=1.77112
C02=1.20275
C03=1.00000
C04=1.00000
CB=11.11901
Cc=14.46156
Cs
=13.87171
C05=1.14172
C06=1.52861
C07=2.02212
C08=1.00000
CE=8.27441
CD=14.43078
CL=1.00000
C41=2.09575
C42=5.67396
C21=1.29480
C22=1.90667
5.Final design
Cmin , OP amp: 70dB 3 MHz
=>Passband ripple: 0.06dB minimum stopband loss 39.5dB
Maximum sensitivity: 0.05dB %
(2 10 )
3
F, L0=
1
H
(2 10 3 )
I4=
V3 V5
,
sL4
-V5=
V
1
( I 4 + sC 4V3 5 ).
s (C 4 + C 5 )
RL
14-66
CHUNG-YU WU
3.SCF design
The flow diagram is shown on P.14-? whereas the active-RC
circuit is given on P.14-?.
The SCF is shown on P.14-? where T=20s is chosen and the component values
are
C2+C3+C4=334.34F,
C1+C2=160.59F,
CS=
T
=20F,
Rs
T
1
C= =20F,
C4+C5=175.018F,
CL=
T
=20f
RL
4.Scaling
Dynamic range scaling with Vpi listed:
followed by minimum-capacitance scaling
Element values:
C1=8.03214, C3=12.97271,
C3A=1.08390,
C1A=1,
C1B=1.07930, C3B=1,
C1C=1.29263, C3C=1.02540,
C1D=1.13212, C3D=1.66885,
C2=13.42236, C4=15.76379,
C2A=1.08053, C4A=1.71203,
C4B=1,
C2B=1,
C5=8.75121,
C5A=2.20614,
C5B=1,
C5C=6.29664.
5.Final design
Cmin Passband ripple: 0.095dB>0.044dB
Minimum stopband loss: 40.5dB
OP amp: 70dB, 3MHz
Maximum passband sensitivity: 0.08dB %
14-67
CHUNG-YU WU
Ron=
uco w
(VG S VT )
2 L
Vin
signal voltage -Vss
* Nonlinear behavior
2
1
Vin
C1
Vout
2
t=nT
t=(n+1)T
C2
1
R1
R2
+
-
Vout
Vin
V1
C1
At t=nT , V1(t)=V1(nT)=Vin(nT)(1-e T 2 R C )
1 1
Let R1=R2=R
(1 e T 2 RC ) 2 C1 C 2
=> H(z)=
z 1
C C
Ideal: H(z)=- 1 2
z 1
1
14-68
CHUNG-YU WU
=1-(1-e T / 2 RC ) 2 2e T / 2 RC
Error:
=>
RC1
1
0.05
=RC1fc
T
2 ln 20000
or RC1 T (= 1 )
20
20 fc
n
T
14-69
CHUNG-YU WU
+
ideal op amp
+
-
pratical op amp
Voff
Voff = 5~20mv
C2
2
2
Vout
C1
+
+
-
Voff
* Vout=(1+
C1
) Voff
C2
C2[Vc2(nT)-Vc2(nT-T)]
+C1[Vin(nT)+
1
Vout(nT)]=0
AO
2
C1
Vout
+
A0
14-70
CHUNG-YU WU
H(ejT)=Hi(ejT)
1
1+ ( 1
AO
(C1 / C 2 )
z 1
1
F()=
1 m( ) + j ( )
Hi(z)=
F()
m()=
C1 / C 2
C
1
(1 + 1 ) ()=
AO
2C 2
2 Ao tan(T / 2)
C1 / C 2
AoT
relative magnitude error
F ( ) =
1
(1 m) +
2
1
1 m
1+m
<<1
F()=-tan 1 m tan-1
-1
m<<1
Ao>1000=>0.1%
f
1
= s
AoT Ao
=> m and are very small.
But for <2/AoT , is large.
>>
Ao>100=>1%
<0.1%
1
1 / Ao + S / o
single-pole response
Similarly
C2
C1 + C 2
m()=-e-k1[1-KcosT]
k=
()=e-k1KsinT
k1 K woT/2
14-71
CHUNG-YU WU
o vs c:
(1) Given o, c should be chosen low enough so that the OP AMPs have
enough time to settle.
But c should not be too low, or the noise aliasing effect becomes serious
the antialiasing and smoothing filters must be too selective and too
complex.
(2) Given c, o should be just high enough to assure that the stage can settle
within each clock phase. Any higher value worsens unnecessarily the
noise aliasing effect, and raises the dc power and chip area requirements
of the op-amps.
(3) Ao=1000 (60dB), fo=10MHz, fp1=10KHz
choose fc=2MHz, and f<40 KHz
Typically f/fc 48 i.e. oT
1
4
C1C 2
1
+ C L ) T1 < T 2=1
C1 + C 2
7
14-72
CHUNG-YU WU
(3) Thermal and flicker ( 1 f ) noise generated in the switches and op-amps.
Thermal and flicker ( 1 f ) noise:
* Internal sampling and holding=>If 1 f noise has no
aliasing=>It can be eliminated.
* Thermal noise will be sampled and held with the OP AMP as
a frequency limiting element.=> o>>c is not suitable.
* The circuit noise if the circuit cap.
15-1
CHUNG-YU WU
Voltage OP AMP AV
Current OP AMP AI
Finite-gain voltage amp
Finite-gain current amp.
Infinite-gain Operational Transconductance
Amp. (OTA) Gm
Finite-gain OTA or gm amplifier
Infinite-gain Operational Transimpedance
Amp. Rm
Finite-gain Transimpedance Amp. or Rm
amplifier
Mixed Gm and Rm Amplifiers
Mixed AV, AI, Gm, and Rm Amplifiers
RF amplifier
:
:
:
:
:
Integrated LC filters
well developed
less developed but with great potential
much less developed
not explored
to be developed with potential
15-2
CHUNG-YU WU
Ideal characteristics:
gm=hIABC or h'VABC
Io=gm(V+-V-)
Ri , Ro=0
h(h') is a constant.
V+
Io
V-
IABC or VABC
V+
Nonideal characteristics:
gm is not linearly proportional
to IABC or VABC.
Ri and Ro are finite.
gm
Ri
V-
Io
gm(V+ - V-)
Ro=0
Ri
V-
Ro
gm(V+ - V-)
Io
V+
15-3
CHUNG-YU WU
15-4
CHUNG-YU WU
15-5
CHUNG-YU WU
(f) FDNR
(d) Variable Impedance Inverter (VIC) or Gyrator
* ZL is a capacitor=> Zin is a inductor=>active inductor.
* Can be used in voltage-controlled oscillator (VCO)
(h) FDNR (Frequency Dependent Negative Resistance)
R
S=j Zin(j)= 2
3. Integrators
Gm or OTA + R or C
(a) Simple
(b) Lossy
15-6
CHUNG-YU WU
gm1
Vo/Vi=gm1/(sC+gm2)
Vo
gm2
(b) Adjustable
H(s)=
|H|
gm
Vo
Vo
gm
=
Vi sc + g m
1
gm
gm/C
Vi
H(s)=
Vo
gm
Vo
gm
=
Vi sc + 1
R
gm
1/RC
H(s)=
Vi
gm
Vo
Vo
sc
=
Vi sc + g m
gm
gm/C
15-7
CHUNG-YU WU
(d) Shelving equalizer, fixed high-frequency gain, fixed pole, adjustable zero
|H|
Vi
Vo
gm
gmR>1
H(S)=
Vo R( sc + g m )
=
Vi
sRC + 1
gmR=1
gmR<1
1/RC
(e) Shelving equalizer, fixed high-frequency gain, fixed zero, adjustable pole
|H|
Vi
Vo
gm
gmR<1
H(s)=
Vo g m (1 + sRC )
=
Vi
sc + g m
gmR=1
gmR>1
1/RC
|H|
C2
Vi
gm
Vo
gm
Vo
sc2 + g m
=
Vi s (c1 + c2 ) g m
C1
gm/(C1+C2)
|H|
Vi
Vo
gm1
1
gm2
H(s)=
gm1>gm2
gm1<gm2
Vo sC + g m1
=
Vi sC + g m 2
gm1=gm2
15-8
CHUNG-YU WU
(h) Lowpass or highpass filter, adjustable zero and pole, fixed ratio or
independent adjustment
|H|
C2
gm1/(gm1+gm2)
Vi
Vo
gm1
C1
gm
C2/(C1+C2)
gm1/(gm1+gm2) > C2/(C1+C2)
gm2
|H|
C2/(C1+C2)
gm
g m1 + sC 2
V
H(s)= o =
Vi s (C1 + C 2 ) + g m1 + g m 2
gm1/(gm1+gm2)
gm1/(gm1+gm2) < C2/(C1+C2)
C
H
Vi
Vo
gm1
gm2
R
180o
Vo
sC g m1
=
Vi sC + g m1 g m 2 R
gm2R=1
gm
90o
0o
gm1/C
V01=
15-9
CHUNG-YU WU
If gm1=gm2=gm
o Q (fixed)
g m1 g m 2
Vi=VA
o Adjustable
2
Lowpass VB and VC Grounded s C1C 2 + SC1 g m 2 + g m1 g m 2
gm
C1C 2
C2
C1
sc1 g m 2
Vi=VB
o Adjustable
Bandpass VA and VC Grounded s 2 C1C 2 + SC1 g m 2 + g m1 g m 2
gm
C1C 2
C2
C1
s 2 C1C 2
Vi=VC
o Adjustable
Highpass VA and VB Grounded s 2 C1C 2 + SC1 g m 2 + g m1 g m 2
gm
C1C 2
C2
C1
s 2 C1C 2 + g m1 g m 2
s 2 C1C 2 + SC1 g m 2 + g m1 g m 2
gm
C1C 2
C2
C1
o Adjustable
Notch
Vi=VA=VC
VB Grounded
(b)
o=
g m1 g m 2
C 2 g m1
1
, Q=
C1C 2
g m3 R C1 g m 2
g m1 g m 2
g g
C
, Q= ( 2 ) m1 m 2
C1C 2
C1
g m3
15-10
CHUNG-YU WU
gm 1
VA
gm 2
C1
gm 3
C2
Vo4
VC VB
o=
g m1 g m 2
1
, Q=
g m3
C1C 2
g m1 g m 2 C 2
C1
x x'
VA
gm1
gm2
C1
C2
Vo
C3
Vo
S 2 + g m1 / C1C 2
C2
)(
)
H(s)= = (
Vi
C 2 + C3 S 2 + Sg m 2 /(C 2 + C3 ) + g m1 g m 2 / C1 (C 2 + C3 )
* Can be applied to the realization of high-order voltage-controlled elliptic
filters.
=>Cascading these second-order blocks with interstage unity-gain buffers.
All gm's are made equal and adjusted simultaneously.
* The voltage-controlled amplifier of Fig. (g) on p.15-3 can be
inserted between x and x'. The transconductance gain of the two OTAs in the
15-11
CHUNG-YU WU
amplifier can be used as the control variable to adjust the ratio of the zero
location to pole location.
(g) General biquadratic structure
H(s)=
H(s)=
Vout K1 S + K o
=
Vin
S + o
SCx + Gm1
=
S (C A + C X ) + Gm 2
=>Cx=(
S(
Gm1
Cx
)+
C A + Cx C A + Cx
Gm 2
S+
CA + CX
K1
)C A , Gm1=Ko(CA+CX), Gm2=0(CA+CX)
1 K1
15-12
CHUNG-YU WU
1/S
1/S
Vout(S)
K1+K2S
H(s)=
H(s)=
Vout ( s ) K 2 S 2 + K1 S + K o
=
2
Vin ( s )
S 2 + ( o )S + o
Q
Vout ( s )
=
Vin ( s )
S2(
Design equations:
G m 2 Gm 4
Gms
GX
) + S(
)+
C X + CB
C X + CB
C A (C X + C B )
Gm 3
Gm1Gm 2
)+
S 2 + S(
C X + CB
C A (C X + C B )
CX=CB(
K2
) where 0 K 2 <1
1 K2
Gm1=oCA
Gm2=o(CB+CX)
Gm3=
o (C B + C X )
Q
Gm4=(KoCA)/o
Gm5=K1(CB+CX)
15-13
CHUNG-YU WU
1
1
where rds3=rds4=
rs1 + rs 2 + (rds 3 || rds 4 )
2 K 3 (VGS 1 Vtn )
rs1=rs2=
I
1
1
=
VGS1-Vtn= 1
g m1 2 K 1 (VGS1 Vtn )
K1
15-14
CHUNG-YU WU
Real circuit:
(iD1-iD2)= 4 K eq I B (V1 V2 )
Gm=4 K eq I B
* 30~50 dB linearity.
(i1-i2)=2KVB(V1-V2)
Gm=2KVB
*30~50dB linearity
15-15
CHUNG-YU WU
M1
keff =
Vout
Vin
M3
VG4
kn k p
( kn + k p )2
1
W
kn,p= (u eff cox ) n , p
2
L
M4
VL
VB
C1
C2
VH
V2
6
Vo
V3
C1 g m SN BP + C1 g m S 2 N HP + g m N LP + (C1C 2 g m S 2 + g m L g m ) N BR
H(s)=
3
C1C 2 g m S 2 +C1 g m ( g mQ g m ) S + g m
2
NBP: VB 0 , VL=VH=0
NHP: VH 0 , VL=VB=0
NLP: VL 0 , VH=VB=0
NBR: VL=VH=VBR, VB=0
15-16
CHUNG-YU WU
Automatic
1 dB
>60 dB
800 KHz
40dB
1 MHz
40%
* Smaller speed
The load of op amps is resistive
1.5 MHz
unlimited
1mV @ Gain 50
75dB
0.5%
1.2 Vpp
Manual
0.5 dB
15-17
CHUNG-YU WU
1. Two-transistor integrators.
Vdiff Vpo-Vno=
R 2 R p 2 = Rn 2
ino i po
SC1
=
=
(i p1 + i p 2 ) (in1 + in 2 )
SC1
1
1
(V p1 Vn1 ) +
(V p 2 Vn 2 )
SR1C1
SR2 C1
15-18
CHUNG-YU WU
GG
C1 2 G2
)S + ( )S + 1 3
V ( s)
C
CB
C AC B
= B
H(S)= o
GG
G
Vi ( s )
S 2 + ( 1 )S + 3 4
GB
C AC B
(
3. Four-transistor integrators
Vdiff Vpo-Vno
=
(V pi Vni ) +
srDS 1c1
srDS 2 c1
(Vni V pi )
where rDS1=
u n cox (
rDS2=
W
)1 (Vc1 V x Vt )
L
1
W
u n cox ( ) 2 (Vc 2 V x Vt )
L
1
srDS c1
(V pi Vni )
1
where rDS=
u n cox (
W
)(Vc1 Vc 2 )
L
16-1
CHUNG-YU WU
x(n)
x(n)
y(n)
Quantizer
y(n)
fs
2
fs
S e2 ( f )df =
=>Kx=(
Se(f)
2
2
2
K x df = K x f s =
12
Height Kx
1
)
12 f s
fs
2
2. Oversampling Advantage
fs
2
H( f )
x(n)
fo
quantizer
N-bit
y(n)
y (n)
2
H(f)
filter
fs
2
-fo
fo
fs
2
f
2 fo
fs
16-2
CHUNG-YU WU
Assume that the input signal is a sinusoidal wave between 0 and 2N.
The signal power Ps is
2 2 2
) =
Ps=(
8
2 2
2 N
With H(f), Ps remains the same since the signal's frequency content is below fo,
but the quantization noise power Pe becomes
fs
2
fs
fo
Pe= S ( f ) H ( f ) df = fo K x df =
OSR 2 => Pe
SNRmax=10log(
2
e
2 f o 2 2 1
= (
)
f s 12 12 OSR
1
or -3dB, or 0.5 bits
2
Ps
3
) = 10 log( 2 2 N ) + 10 log(OSR)
Pe
2
=6.02N+1.76+10log(OSR)
=>SNR enhancement obtained from oversampling: 10log(OSR).
SNR improvement of 3 dB/octave or 0.5 bits/octave
3.The advantage of 1-bit D/A converter
* Oversampling improves the SNR, but it does not improve linearity.
* Theoretically, 1-bit converter with fo=25 KHz can obtain a 96-dB SNR(16 bits)
if the sampling frequency fs=54,000 GHz!
* The advantage of a 1-bit DAC is that it is inherently linear.
Vout
always linear
Bin
16-3
CHUNG-YU WU
fs >> 2fo
Decimation Filter
1-bit
stream
Delta-Sigma
Delta-Sigma
A-to-D Converter
A-to-D Converter
(Modulator)
(Modulator)
Analog Signal
DSP
DSP
Decimation
Decimation
Chip
Chip
fs >> 2fo
2 fo =
Minimum
Anti-Aliasing
Filter
Analog
Delta-Sigma
Modulator
.
.
.
1
(OSR)T
Digital
Low-Pass
Filter
f0
Multi-Bit
Output
Nyquist
Rate PCM
OSR
Down Sampler
e(n)
2. Noise-shaped modulator
u(n)
X(n)
1-bit
Quantizer
H(Z)
-
y(n)
u(n)
H(Z)
X(n)
DAC
1-bit
DAC
1-bit
Y ( z)
H ( z)
=
U ( z) 1 + H ( z)
Y ( z)
1
=
E( z) 1 + H ( z)
=>Y(z)=STF(z)U(z)+NTF(z)E(z)
If H (z ) for 0<f<fo => S TF ( z ) 1 and N TF ( z ) 0
=> Quantization noise and signal unchanged.
3.First-order noise shaping:
y(n)
16-4
CHUNG-YU WU
z 1
(Noniverting Forward-Euler SC integrator)
1 z 1
H ( z)
= z 1
=>STF(z)=
1 + H ( z)
H(z)=
NTF(z)=
1
jT
j2f/fs
= (1 z 1 ) z=e =e
1 + H ( z)
NTF(f)=1-e-j2f/fs=sin (
N TF ( f ) = 2 sin(
f
) (2 j ) (e j f / fs )
fs
f
)
fs
2
e
fo
f
f
)
fs
fs
2 2 2 f 3 2 2 1 3
=> Pe ( )( )( ) =
(
)
12 3 f s
36 OSR
P
3
3
2 2 2 N
Ps=
=> SNRmax=10 log( s ) = 10 log( 2 2 N ) + 10 log[ 2 (OSR) 3 ]
8
Pe
2
=> SNRmax=6.02N+1.76-5.17+30 log(OSR)
Double OSR => SNRmax by 9dB or 1.5bits/octave
Without noise shaping: SNRmax by 3dB/ octave or 0.5bits/ octave.
Y=Z-1U+E(1-Z-1)
Block diagram:
U
E
z 1
H ( z) =
1 z 1
+
-
Y = UZ 1 + E (1 Z 1 )
16-5
CHUNG-YU WU
SC implementation:
C
2
+
_
1
1
2
Comparator
Y
1
phase 2
Reset
Quantizer(1-bit ADC )
H(Z)
Latch
(2)
+
_
.5
0
-. 5
1-bit DAC
0. 5
-0 . 5
-1
Control signal
z 1
1 z 1
2-bit
A/D
2-bit
D/A
0. 5
+
0
.5
+
-0. 5
MUX
-1
Control line
16-6
CHUNG-YU WU
H2
1
+
1
1 z
z 1
1 z 1
Y
Quantizer
DAC
STF(Z)=Z-1
NTF(Z)=(1-Z-1)2
N TF ( f ) = [2 sin(
Y=Z-1U+(1-Z-1)2E
f 2
)]
fs
2 4 1 5
(
)
=> Pe
60 OSR
SNRmax=10log(
Ps
3
5
) = 10 log( 2 N ) + 10 log( 4 ) + 10 log(OSR) 5
Pe
2
=6.02N+1.76-12.9+50log(OSR)
OSR2 => SNRmax by 15dB/Octave or 2.5 bits/Octave
General formula of SNRmax with k-order noise shaping:
2k + 1
) + (2k + 1) 10log(OSR)
SNRmax=6.02N+1.76- 10log(
4
TF
(f)
Second-order
First-order
No noise shaping
f
s
2
16-7
CHUNG-YU WU
linearity.
* The capacitor and switches in the feedback path to OP2 can be reduced as
shown on page 16-5.
SC implementation: Single-Ended type circuit diagram
V+
C
2
Control
signal
1
V-
1-bit
DAC
2
1
U
2
1
C
1
2
-OP
+1
COMP-1
2
-OP
+2
Preamplifier
Latch
(2)
16-8
CHUNG-YU WU
in
x (t )
(t )
Antialiasing
filter
Sampleand-hold
sh
(t )
dsm
(n)
Mod
Analog
Digital
low-pass
filter
x
dsm
sh
f
s
(f)
(n) = 1.000000K
3
12 4...
lp
OSR
x (f)
X sh (t )
x (n)
(n )
Decimation filter
Digital
(t )
lp
f
s
dsm
( )
2(f0/fs)
/6
(n)
123.....
lp
x ( )
3...
Ts
( )
/6
2(f0/fs) =
OSR OSR=6
x (n)
12
Ts
T0
2 4 6 8 10 12
2 T
6
* The decimation process does not result in any loss of information, since the
bandwidth of the original signal was assumed to be fo. The spectral information is
spread over 0~
16-9
CHUNG-YU WU
x (n)
s
OSR
2
(n )
Interpolation
(low-paaa)
fs
filter
(n )
s2
OSR
f
2f
lp
Mod
dsm
(n )
da
x (t )
(t )
Analog
low-pass
filter
1-bit
D/A
s
Digital Analog
s
()
x (n)
s
s2
(n )
x ( )
s
(2)
(3)
123...(1)
x
x
lp
s2
( )
(2
lp
dsm
(n )
da
( )
( )
dsm
( 2f )
0
x
c
da
( 2f )
(t )
n,t
Ts
(n)
123.....
T0
2 4 6 8 10 12
Ts
Ts
(f)
(t )
t
Time
f
s
x (f)
c
Frequency
f
s
16-10
CHUNG-YU WU
Q1
z
1 z
= UZ
+ Q (1 Z
z 1
+
Q1
Q1
z
1 z 1
(1 z 1 )
YZ 1
= Q1 Z 1 + Q (1 Z 1 )
= UZ
Q (1 Z
)2
16-11
CHUNG-YU WU
B. Nonlinear effects
R&C nonlinearities
Amplifier nonlinearities
Finite op-amp slew rate
Signal-dependent clock feedthrough noise
Signal-dependent sampling aperture noise
Internal A/D and D/A nonlinearities
Linearity of 1-bit DAC:
1. The two output levels somehow become functions of the low-frequency
signals=> Linearity limitation
Power supply voltage are changed for different low-frequency signals to
cause distortion.
=> must be well-regulated.
The clock feedthrough of the input switches is also dependent on the gate
voltage and thus the supply voltage.
=> low-frequency input signal dependent
The clock jitter could be a function of the low-frequency input signals.
2.The memory between output levels also causes severe linearity limitation.
Typical
Ideal
V2
V1
Binary
1
1
1
1
1
1
1
Area for
A1
A0 + 2 A 0 A1 + 1 A0 + 2 A1 + 1
A1 + 1
symbol
1, 2: The area difference of the present binary state with different past states.
1-1: 2
-11: 1
Average 0 : 1, -1,1, -1,- - 1
: 1, 1, -1, 1, -1, 1--3
1
Average - : -1, -1, 1, -1, -1, 1, -1--3
Average
Va (t ) =
A1 + AO 1 + 2
+
2
2
Vb(t ) =
2 A1 + AO 1 + 2
+
3
3
Vc(t ) =
A1 + 2 AO 1 + 2
+
3
3
16-12
CHUNG-YU WU
Typical
Ideal
V2
V1
Binary
Area for
symbol
1 : -11 and 11
-1 : -1-1
=> Better linearity.
-1
-1
1
A
-1
A
3. Basically, SCF or SC circuits are memoryless if enough time is left for settling
on each clock phase.
Idle tones phenomena
1-bit DAC
dc level
1
=> y(n)={1, 1, -1, 1, 1, -1..}
3
fs
.
3
1 1 3
+
= => y(n)={1, 1, -1, 1, 1, -1, 1, 1, -1, 1, 1, -1, 1, 1, 1, -1, 1, 1, -1,
3 24 8
1,}
16-13
CHUNG-YU WU
periodic pattern with 16 cycles and some power at dc and f s .
16
3
and f s tone
8
16
(fo= f s is assumed and lowpass filter will not attenuate fs/16 signal)
16
=> Low-frequency tones cannot be filtered out by the lowpass filter and can lead
to annoying tones in the audible range. They exist even in high-order modulators.
There tones might be a signal varying over some frequency range in a random-like
fashion.
Dithering technique to reduce idle tones.
To add the dithering signal to the modulator just before its quantizer.
The dithering signal has a white-noise type spectrum and is a random
(psuedo-random) signal.
The dithering signal breaks up the tones so that they never occur.
Add about 3-dB extra in-band noise
Require rechecking the modulator's stability.
16-14
CHUNG-YU WU
16-7 Examples
2nd-order modulator implemented by fully differential SC circuit.
16-15
CHUNG-YU WU
Testing Environment:
Digital-to-Analog Converter
Precision
Function
Generator
.
.
Low-noise cable
Pure test
Pattern
Good
Transmission Line
ADC
Mearurement
17-1
CHUNG-YU WU
+
-
Phase
detector
Vpd
Low-pass
filter V
Hlp(s)
Gain
lp
Klp
Output
voltage
Loop filter
Vcntrl
VCO
Voltage-Controlled Oscillator
If the phase detector is of analog-multiplier type, its output voltage Vpd can be written
as
Vpd=KMVinVosc=KM Ein Eoscsin(t)cos(t-d)
where d is the phase difference between the input
signal Vin and the output Vosc of the VCO.
Vpd=KM Ein Eosc [sin( d ) + sin( 2t d )]
2
Since the lowpass filter is to remove the high-frequency (2) term, the signal Vcntl is
given by
E E
Vcntl=KlpKM in osc sind
2
E E
E E
KlpKM in osc d=KlpKpdd
where Kpd K M in osc
2
2
The frequency of VCO can be expressed as
osc=KoscVcntl+fr
where fr is the free-running frequency of the VCO with its control voltage Vcntl=0.
=> Vcntl=
i n f r
K osc
17-2
CHUNG-YU WU
=> d=
in f r
Vcntl
=
K l P K pd K l P K pd K osc
in ( s )
Kpd
KlpHlp(s)
Vcntl
osc ( s )
Kosc
1/s
Vcntl(s)=KpdKlpHlP(s)[in(s)-osc(s)]
osc(s)=Kosc(Vcntl(s)/s) ((t)=
=>
d (t )
dt
( s) =
( s)
s
SK pd K lP H lP ( s )
Vcntl ( s )
=
in ( s ) S + K pd K lP K osc H lP ( s )
1 + s z
1 + s p
z<<p
1
S (1 + s z )
Vcntl ( s )
K osc
=
=> (s)
s 2 p
in ( s )
1
1 + S(
+z) +
K pd K lp K osc
K pd K lp K osc
* H(s)=0 as s0 => in=0 leads to Vcntl=0
17-3
CHUNG-YU WU
1
S (1 + s z )
Vcntl ( s )
K osc
=
s 2 p
in ( s)
1
1 + S(
+z) +
K pd K lp K osc
K pd K lp K osc
*
Vcntl ( s )
in ( s )
s =0
1
K osc
Q=
K pd K lp K osc
K pll
P
1
+ Z K pd K lp K osc
K pd K lp K osc
P
1
+ Z K pll
K pll
1
2
1
3
1
2
* Usually Q=
1
is recommended in PLLs
2
1
2
K pll
=> Q
=> Z =
z K pll o Z
1
2
2 P 2
=
K pll o
The transient time constant pll of the complete loop for small phase or frequency
changes can be expressed as
pll
17-4
CHUNG-YU WU
Design considerations:
K pll
Q
K pd K osc
Q
(Klp=1)
Q( i n osc ) 2
* If a PLL is designed to have a narrow loop bandwidth o, tacq can be quite large and
lock is attained too slowly.
Solution: 1. To add a frequency detector that detect when in-osc is large. Then drive
the loop toward lock much more quickly. When in-osc is small, the
frequency detector and the driver are disabled.
2. To design the lowpass filter with a programmable pole frequency o.
Initial acquisition: o speed up acquisition.
Lock
: o increase noise rejection.
3. To sweep the VCO's frequency range during acquisition with the PLL
disabled. When oscin, sweeping is disabled and PLL is activated.
5. Lock range
Lock range: Once lock is attained, the PLL remains in lock over a range as long as
the input signal's frequency in changes only slowly. This range is the
lock range, which is much larger than the capture range.
Vcntl-max=Klp KM Ein Eosc =KlpKpd
2
=> lck = KoscKlpKpd
17-5
CHUNG-YU WU
17-2.1 Multiplier PD
Vpd =KMEinsin(1t+1)Eosccos(2t+2)
=KM Ein Eosc {sin[(1-2)t+1-2]+sin[(1+2)t+1+2]}
2
At phase lock, 1=2
=> Vpd= KM Ein Eosc [sin(1-2)+sin(2t+1+2)]
2
After the lowpass filter, we have
Vpd=KlpKM Ein Eosc sin (1-2)=KM Ein Eosc sind d if d is small.
2
2
* The multiplier PD is especially useful in applications where the reference
frequency is too high and where the loop bandwidth is sufficiently narrow so
that the filtering of the undesired components can be effective.
* The loop could lock to harmonics of the input signal.
=>False lock
* 1=2 is required.
17-2.2 EXOR PD
(a)
A
B
(b)
A
B
C=A B
17-6
CHUNG-YU WU
(c)
Average
value of C
-1
-0.5
0.5
* when A(Vin) and B(Vosc) are 90 out of phase, the output Vpd(c ) has =2in
and 50% duty cycle. This is a reference point. Vpd d for 0o<d<180.
* False lock could occur
* 1=2 is required.
17-2.3 Flip-Flop PD
(a)
(b)
A
B
C
(c)
Average
value of C
-1
-0.5
0.5
* The average value of Vpd or C has the shape of a saw tooth, with a linear range
of a full cycle.
* At the center of the linear range of Vpd average, the most important harmonic is
situated at the fundamental of the reference frequency as compared to the twice
of reference frequency in the EXOR PD.
17-7
CHUNG-YU WU
(a)
(b)
EXOR PD
Flip-flop PD
Phase
0
0.5
0.5
Average
Fundamental
2nd
Harmonic
17-2.4 Charge-pump PD
VDD
Ich
Vin
Vosc
Sequential
phase
detector
Pu
Pd
S1
Vlp
S2
C1
Ich R
C2
-VSS
Charge-pump phase
comparator
Low-pass filter
17-8
CHUNG-YU WU
Vosc
in
Pu
2
Pd
Time
Iavg= in Ich
2
Iavg=Kpd(in-osc)=Kpdin
I
=> Kpd= ch
2
For the lowpass filter R, C1 has a transfer function Hlp(s) as
Hlp(s)=
Vin ( s )
1 + SRC1
1
=R+
=
I avg ( s )
SC1
SC1
=> o =
Q=
S (1 + SRC1 )
S 2 C1
1 + SRC1 +
K pd K osc
K pd K osc
C1
1
1
1
2
=
=
RC1 o R C1 K pd K osc R C1 I ch K osc
Vlp ( s )
in ( s )
17-9
CHUNG-YU WU
3. Design Considerations:
(1) Choose Ich based on practical consideration like power dissipation and speed.
(2) o is chosen according to the desired transient settling-time constant pll as
o=
pll
(3) C1 is chosen from the equation of o whereas R is chosen using the equation of Q.
The chosen Q value is slightly less than what is eventually desired. R => Q
(4) Add C2 to minimize glitches.
C2 => Q => chosen Q value is smaller => Exact Q.
1
of
8 10
C2 1 ~
=> lp(s)=
C1
R
1
+
1 + SRC 2 SC1
Pu
Pd
FF1
Vin
FF2
Reset
set1
set2
Pu-dsbl
Pd-dsbl
FF3
FF4
set3
set4
Vosc
17-10
CHUNG-YU WU
Vin1
Vosc1
=> Pu=1 => Charge pumping starts and Vlp => osc
=> Reset nor gate inputs: 00010000 => Reset 01
=> Pu=0 and Pd=0 after one gate-delay ; Pd 010
Pu-dsbl=1 and Pd-dsbl=1 after two gate-delays.
=> Reset 10 after one gate-delay of Pu-dsbl1 and Pd-dsbl1
or after three gate-delays of Vosc1.
=> eeping Pu=0 and Pd=0 => charge pumping.
=> FF3 is reset and Pu-dsbl=0
It is only when Vin 10
Vosc 10 => FF4 is reset and Pd-dsbl=0
Vin
Vosc
Pu
Pd
Pu-dsbl
Pd-dsbl
in>osc => Pu=1 => Charge pumping to increase osc until lock is achieved.
(a)
Up
Ref
Div
I
IC
PFD
Dn
Zlf
17-11
CHUNG-YU WU
(b)
Ref
Div
IC
(c)
Average
value of C
-1
-0.5
0.5
1
s
log GH ( )
1
s
GH ( )
0
-90
17-12
CHUNG-YU WU
=> GH ( s ) =
1
1 + S / p
p K pd K lp K osc
S (1 + S / p )
S 2 + pS
K pd K lp K osc
log GH ( )
GH ( )
0
-90
-180
=> GH(S)=
(1 + S / z )
(1 + S / p )(1 + S / a )
K pd K lp K osc (1 + S / z )
S (1 + S / p )(1 + S / a )
Bode plots of GH(S):
z c
If a=0
=> Third-order type-2 PLL.
GH ( )
0
-90
-180
17-13
CHUNG-YU WU
Loop filter:
1 + s z
s (C Z + C p )[1 + s p ]
Rz
z= RzCz
p=Rz(Cz-1+Cp-1)-1
=> GH(s)=
Cp
Cz
K pd K lp K osc (1 + s z )
S 2 (C z + C p )(1 + s p )
: offset frequency
1Hz
VCO output
17-14
CHUNG-YU WU
constant.
4. Frequency pushing (MHz/V)
The dependency of the center frequency on the power supply
voltage.
5. Frequency pulling
The dependence of the center frequency
6. Low cost
+ +
- -
+ +
- -
17-15
CHUNG-YU WU
Gm
Gm
Gm
17-4.3
LC-oscillator as VCO
* Typically a 20dB better phase noise obtained over ring and relaxation oscillators.
* High-speed operation is possible due to the simple working principle.
* The realization of the inductor is the key point.
Design example: 0.7m CMOS planar-LC VCO.
M4
M3
L1
L2
Vc
Ibias
Vout+
M1
C1
C2
VoutM2
17-16
CHUNG-YU WU
Measurement results:
1. Measured output spectrum for a carrier frequency of 1.81 GHz.
17-17
CHUNG-YU WU
* At Vc=0.5V, the diode varactors C1 and C2 have a larger leakage current => Phase
noise 3dB.
17-18
CHUNG-YU WU
0.1
30
100
-118 @1MHz
-90
[Dobos
9-GHz Bip
CICC94]
Ring oscillators
[Kwasn
1.2-um CMOS
CICC95]
[Razav JSSC96] 0.5-um CMOS
0.4
100
-110 @1MHz
-92
0.74
6.5
- 89 @100kHz -97
Comparison of 3 designs
2.2
NA
NA
-94 @1MHz
-91
[vd Tan
9-GHz BiCMOS 2.0
ISSCC97]
LC-tuned oscillators
[Nguye JSSC92] 10-GHz Bip
1.8
NA
95
-106 @2MHz
-96
70
10
-88 @100kHz
-104
1.0
16
-95 @100kHz
-105
[Soyue
12-GHz
JSSC96a]
BiCMOS
[Ali ISSCC96] 25-GHz Bip
2.4
50
-92 @100kHz
-110
0.9
10
N.A.
17-19
CHUNG-YU WU
Reference
Technology
[-]
LC-tuned oscillators(cont'd)
0.9
10..40 14
12
1.8
15
40
10
2.2
43
11
[Parke CICC97]
0.6-um CMOS
1.6
NA
12
[Steya EL94]
6-GHz Bip
1.1
-75 @ 10kHz
[Crani JSSC95]
0.7-um CMOS
1.8
24
[Crani JSSC97]
0.7-um CMOS
1.8
14
[Crani CICC97]
0.4-um CMOS
1.8
11
20
Presented designs
-106
17-20
CHUNG-YU WU
[Banu JSSC88] M. Banu, "MOS oscillators with multi-decade tuning range and
gigahertz maximum speed", IEEE Journal of Solid-State Circuits,
vol. 23, no. 6, pp. 1386-1393, December 1998.
[Sneep JSSC90] J. G. Sneep and C. J. M. Verhoeven, "A new low-noise 100-MHz
balanced relaxation oscillator", IEEE Journal of Solid-State Cir cuits,
vol. 25, no. 3, pp. 692-698, June 1990.
[Dobos CICC94]
pp. 8.4.1-4.
[Kwasn CICC95]
1996.
[vdTan ISSCC97]
17-21
CHUNG-YU WU
[Soyue JSSC96a]
[Ali ISSCC96] A. Ali and L. Tham, "A 900-MHz frequency synthesizer with
integrated LC voltage-controlled oscillator", in ISSCC Digest of
Technical Papers, San Fransisco, USA, February 1996, pp. 390-391.
[Rofou ISSCC96]
392-393.
[Soyue JSSC96b]
1.5-GHz
voltage-controlled
oscillator
with
an
integrated
for 1.1 to 2.2 GHz with fully integrated tank and tuning circuits, in
ISSCC Digest of Technical Papers, San Fransisco, USA, February
17-22
CHUNG-YU WU
[Parke CICC97] J. Parker and D. Ray, "A low-noise 1.6-ghz CMOS PLL with
on-chip loop filter", in Proc. of the IEEE 1997 Custom Integrated
Circuits Conference, Santa Clara, USA, May 1997, pp. 407-410.
[Steya EL94]
[Crani JSSC97] J. Craninckx and M. Steyaert, "A 1.8-GHz low-phase noise CMOS
VCO using optimized hollow inductors", IEEE Journal of
Soild-State Circuits, vol. 32, no. 4, pp. 736-744, May 1997.
[Crani CICC97] J. Craninckx and M. Steyaert, "A fully integrated spiral-LC CMOS
VCO set with prescaler for GSM and DCS-1800 systems", in Proc.
of the IEEE 1997 Custom Integrated Circuits Conference, Santa