08r059210203 Switching Theory and Logic Design

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Code No: R059210203 Set No. 1

II B.Tech I Semester Supplimentary Examinations, February 2008
SWITCHING THEORY AND LOGIC DESIGN
( Common to Electrical & Electronic Engineering, Electronics &
Instrumentation Engineering, Bio-Medical Engineering, Electronics &
Control Engineering, Electronics & Computer Engineering and
Instrumentation & Control Engineering)
Time: 3 hours Max Marks: 80
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Answer any FIVE Questions
All Questions carry equal marks
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1. Convert the following to Binary and then to gray code.
(a) 234516
(b) 123416
(c) 23458
(d) 12578
(e) 77710
(f) 99910 [2+2+2+2+4+4]
2. (a) Simplify the following expressions and implement them with NAND gate cir-
cuits. [8]
i. AB’ + ABD + ABD’ + A’C’D’ + A’BC’
ii. BD + BCD’ + AB’C’D’
(b) Obtain the Dual of the following Boolean expressions.
i. AB + A(B + C) + B’(B + D)
ii. A + B + A’B’C [4]
(c) Obtain the complement of the following Boolean expressions.
i. A’B + A’BC’ + A’BCD + A’BC’D’E
ii. ABEF + ABE’F’ + A’B’EF [4]
3. Minimize the following function using tabular

P minimization and verify the same
with K-map minimization F (A, B, C, D) = m(0, 1, 2, 5, 7, 8, 9, 10, 13, 15). [8+8]
4. (a) Design a circuit to convert Excess-3 code to BCD code Using discrete Logic
gates.
(b) Design a 3 to 8 decode using 2 to 4 decodes and other required gates. [8+8]
5. Write a brief note on:
(a) Architecture of PLDs

(b) Capabitation and the limitations of threshold gates. [8+8]
6. (a) Compare synchronous & Asynchronous circuits

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(b) Design a Mod-6 synchronous counter using J-K flip flops. [6+10]
7. A clocked sequential circuit is provided with a single input x and single output Z.
Whenever the input produce a string of pulses 1 1 1 or 0 0 0 and at the end of the
sequence it produce an output Z = 1 and overlapping is also allowed.
(a) Obtain State - Diagram.
(b) Also obtain state - Table.
(c) Find equivalence classes using partition method & design the circuit using D
- flip-flops. [4+4+8]
8. For the ASM chart given 8:
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(a) Draw the state diagram.
(b) Design the control unit using D flip-flops and a decoder. [8+8]
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1. (a) Perform the following using BCD arithmetic. [2 × 4 = 8]

i. 712910 + 771110
ii. 812410 + 812710
(b) Convert the following. [4 × 2 = 8]
i. AB16 = ( )10
ii. 12348 = ( )10
iii. 101100112 = ( )10
iv. 77210 = ( )16
2. (a) Draw the NAND logic diagram that implements the complement of the fol-
lowing function. [8]
F(A,B,C,D) = Σ (0,1,2,3,4,8,9,12)
(b) Obtain the complement of the following Boolean expressions.
i. AB + A(B + C) + B’(B + D)
ii. A + B + A’B’C [4]
(c) Obtain the dual of the following Boolean expressions.
3. Minimize the following

P function using Quine ?Mc cluskey minimization.
F (A, B, C, D) = m(13, 1, 5, 17, 18, 19, 20, 21, 23, 25, 27, 29, 31) + d(1, 2, 12, 24)
[16]
4. (a) Design a 32:1 Multiplexer using two 16:1 and 2:1Multiplexers.

(b) Design a circuit to convert Excess-3 code to BCD code Using a 4-bit Full
adder. [8+8]
5. (a) Derive the PLA programming table for the combinational circuit that squares
a 3 bit number.

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(b) For the given 3-input, 4-output truth table of a combinations circuit,tabulate
the PAL programming table for the circuit. [8+8]
Inputs Output
x y z A B C D
0 0 0 0 1 0 0
0 0 1 1 1 1 1
0 1 0 1 0 1 1
0 1 1 0 1 0 1
1 0 0 1 0 1 0
1 0 1 0 0 0 1
1 1 0 1 1 1 0
1 1 1 0 1 1 1
6. Design a 4 bit universal shift register which can be used as a parallel in- parallel
out register, serial in serial out register, serial in - parallel at and parallel in serial
out register with a shift option to wards left or right. Explain each of the behavior
with timing waveform. [16]
7. A clocked sequential circuit is provided with a single input x and single output Z.
Whenever the input produce a string of pulses 1 1 1 or 0 0 0 and at the end of the
sequence it produce an output Z = 1 and overlapping is also allowed.
(a) Obtain State - Diagram.

(b) Also obtain state - Table.
(c) Find equivalence classes using partition method & design the circuit using D
- flip-flops. [4+4+8]
8. (a) Draw the ASM chart for the following state transistion, start from the initial
state T1 , then if xy=00 go to T2 , if xy=01 go to T3 , if xy=10 go to T1 , other
wise go to T3 .
(b) Show the exit paths in an ASM block for all binary combinations of control
variables x, y and z, starting from an initial state. [8+8]
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1. (a) Express the Decimal Digits 0 - 9 in BCD, 2421, 84-2-1 and Excess-3.
(b) Convert the Hexadecimal number 1010 to Decimal and then to Binary. [12+4]
2. (a) Convert the following expressions in to sum of products and product of sums
[8]
i. (AB + C) ( B + C’D)
ii. x’ + x(x + y’)(y + z’)
(b) Obtain the Dual of the following Boolean expressions. [8]
i. (AB’ + AC’)(BC + BC’)(ABC)
ii. AB’C + A’BC + ABC
iii. (ABC)’(A + B + C)’
iv. A + B’C (A + B + C’)
3. (a) Explain ,the determination of all possible minimal expressions from a reduced
prime implicant chart. [8]
(b) Make a K-map of the following expression and obtain the minimal SOPand
POS forms. (AC̄) + (AB) + (C) + (AD) + (AB̄C) + (ABC). [8]
4. (a) Draw and explain the truth table and Logic diagram of a 1 line to 8 line
Demultiplexer.
(b) Draw and explain the truth table and Logic diagram of a 3 line to 8 line
Decoder. [8+8]

6. (a) Find a modulo-6 gray code using k-Map & design the corresponding counter.
(b) Compare synchronous & Asynchronous. [10+6]
7. (a) From the given Mealy machine state diagram 7a obtain Moore - Machine state
table.
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www.andhracolleges.com Figure 7a
(b) A clocked sequential circuit with single input and single output Z is defined
by the following D - flip-flop input equations and output equations of Z.
D1 = Q1 Q2 Q3 x
D2 = Q1 Q2 Q3
D3 = Q1 Q3 x + Q1 Q3 x
Z = Q1 Q2 Q3 x
i. Obtain state table
ii. Draw the state diagram. [8+4+4]
wise go to T3 .
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1. Convert the following to Decimal and then to Hexadecimal.
(a) 32148
(b) 45678
(c) 101011012
(d) 11001012
(e) 75610
(f) 53310 [3+3+3+3+2+2]
2. (a) Simplify the following expressions and implement them with NAND gate cir-
cuits. [8]
i. AB’ + ABD + ABD’ + A’C’D’ + A’BC’
ii. BD + BCD’ + AB’C’D’
(b) Obtain the Dual of the following Boolean expressions.
i. AB + A(B + C) + B’(B + D)
ii. A + B + A’B’C [4]
(c) Obtain the complement of the following Boolean expressions.
3. Reduce
P the following function using six variable K- map
F = m(0, 2, 5, 7, 9, 11, 14, 16, 18, 21, 23, 27, 30, 32, 34, 36, 41, 43, 44, 48, 50, 52, 53, 59, 60, 61).
[16]
4. (a) Design a 32:1 Multiplexer using two 16:1 and 2:1Multiplexers.

(b) Design a circuit to convert Excess-3 code to BCD code Using a 4-bit Full
adder. [8+8]

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6. (a) Compare synchronous & Asynchronous circuits
(b) Design a Mod-6 synchronous counter using J-K flip flops. [6+10]
7. (a) Determine a minimal state ? table equivalent to the state table given below
using partition method.
(b) Obtain final transition table. [8+8]
Present state q v Next State q v+1 OutputZ
x=0 x=1 x=2 x=3 x=0 x=1 x=2 x=3
A E C B E 1 0 1 1
B C F E B 0 1 1 0
C B A D F 1 0 1 1
D G F E B 0 1 1 0
E C F D E 0 1 1 0
F C F D H 1 1 0 0
G D A B F 1 0 1 1
H B C E F 1 0 1 1
wise go to T3 .
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www.andhracolleges.

com The Complete Information About Colleges in Andhra Pradesh

Code No: R059210203 Set No. 1

1. Convert the following to Binary and then to gray code.

3. Minimize the following function using tabular

5. Write a brief note on:

(a) Architecture of PLDs

6. (a) Compare synchronous & Asynchronous circuits

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Code No: R059210203 Set No. 1

(a) Obtain State - Diagram.

8. For the ASM chart given 8:

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Code No: R059210203 Set No. 2

1. (a) Perform the following using BCD arithmetic. [2 × 4 = 8]

3. Minimize the following

4. (a) Design a 32:1 Multiplexer using two 16:1 and 2:1Multiplexers.

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Code No: R059210203 Set No. 2

(a) Obtain State - Diagram.

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Code No: R059210203 Set No. 3

5. Write a brief note on:

(a) Architecture of PLDs

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Code No: R059210203 Set No. 3

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Code No: R059210203 Set No. 4

1. Convert the following to Decimal and then to Hexadecimal.

4. (a) Design a 32:1 Multiplexer using two 16:1 and 2:1Multiplexers.

5. Write a brief note on:

(a) Architecture of PLDs

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Code No: R059210203 Set No. 4

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