IEEE ELECTRON DEVICE LETTERS, VOL. 33, NO.

4, APRIL 2012

519

Quaternary Enhancement-Mode HFET

With In Situ SiN Passivation
N. Ketteniss, H. Behmenburg, H. Hahn, A. Noculak, B. Hollnder, H. Kalisch,
M. Heuken, and A. Vescan, Senior Member, IEEE

AbstractA lattice-matched InAlGaN/GaN heterostructure

with a barrier-layer thickness of 4 nm has been grown and passivated in situ with a 63-nm SiN by metalorganic chemical vapor
deposition. Enhancement-mode heterostructure field-effect transistors have been realized by a fluorine-based surface treatment
after the local removal of the SiN. The threshold voltage and
transconductance were 0.65 V and 250 mS/mm, respectively, for a
1-m gate-length device. The benefits of an in situ SiN passivation
are demonstrated: first, the stabilization of the barrier material
and prevention from oxidation and second, the improvement of the
device characteristics by reduced source resistance and reduced
trapping effects.
Index TermsIn situ silicon nitride passivation, normally off
operation, quaternary nitride HFET.

in situ SiN layers of up to 6 nm were applied. Here, we present

an in situ SiN layer of 63 nm, which is thick enough to function
as a passivation layer. Hence, our approach needs no additional
ex situ passivation, and the source and drain resistance can be
kept low without any further increase in device complexity.
Still, a rather thin barrier layer can be applied to support the
depletion of carriers in the intrinsic device. Additionally, the
in situ passivation prevents the degradation of the barrier layer
after growth. It preserves the InAlGaN surface from oxidation
and protects against environmental contaminants.
II. M ATERIAL G ROWTH AND D EVICE FABRICATION
A. Material Growth and Characterization

I. I NTRODUCTION

NE MAJOR topic in GaN device research is the fabrication of enhancement-mode (E-mode) heterostructure
field-effect transistors (HFET). It is known that the charge
density in the 2-D electron gas (2DEG) is mainly dependent on
the polarization-induced charge at the heterostructure interface
[1]. Nevertheless, if the barrier layer of the heterostructure is
thin enough, the 2DEG will be depleted by the surface potential.
This effect is, for example, applied in gate-recessed E-mode
devices [2], [3]. Alternative concepts, e.g., fluorine implantation, have also been published [4], [5]. Here, we demonstrate
a normally off operation of devices, in which both depletion
effects are presentthe surface-related depletion due to the
thin barrier layer and the depletion due to a fluorine-based
surface treatment. Compared to the results already published
[2][5], the major improvement is the application of an in situ
SiN layer for device passivation. In situ SiN has already been
demonstrated to prevent barrier-layer relaxation [6], [7] and as a
gate dielectric [8], [9]. Nevertheless, in both cases, only the thin
Manuscript received January 3, 2012; revised January 9, 2012; accepted
January 12, 2012. Date of publication February 27, 2012; date of current
version March 23, 2012. The review of this letter was arranged by Editor
A. Ortiz-Conde.
N. Ketteniss, H. Behmenburg, H. Hahn, H. Kalisch, and A. Vescan are
with the GaN Device Technology, RWTH Aachen University, 52074 Aachen,
Germany, and also with the Jlich Aachen Research Alliance, JARA-FIT,
52425 Jlich, Germany (e-mail: ketteniss@gan.rwth-aachen.de).
A. Noculak is with the Jlich Aachen Research Alliance, JARA-FIT, 52425
Jlich, Germany.
B. Hollnder is with the Jlich Aachen Research Alliance, JARA-FIT, 52425
Jlich, Germany, and also with the Forschungszentrum Jlich GmbH, 52425
Jlich, Germany.
M. Heuken is with the GaN Device Technology, RWTH Aachen University,
52074 Aachen, Germany, AIXTRON SE, 52134 Herzogenrath, Germany, and
also with Jlich Aachen Research Alliance, JARA-FIT, 52425 Jlich, Germany.
Digital Object Identifier 10.1109/LED.2012.2184735

All layers of the investigated structure were deposited by

MOCVD in an Aixtron 3 2 inch CCS reactor on c-plane
sapphire without growth interruption using the standard precursors. The buffer consists of a 500-nm AlN layer followed by a
2.5-m GaN. The HFET is formed by a 1-nm AlN layer for mobility enhancement and a quaternary 4-nm In0.11 Al0.72 Ga0.17 N
barrier layer which is lattice-matched to the underlying GaN.
A 63-nm SiN was deposited as the top layer for the in situ
passivation of the HFET structure at a barrier-layer growth
temperature of 790 C using SiH4 and NH3 . The thickness of
the barrier layer was determined by comparing high-resolution
X-ray diffraction (HRXRD) 2 scans to simulations. Due
to the difficulty of accurately determining the composition
of a very thin quaternary barrier, Rutherford backscattering
measurements were performed on a reference sample with a
100-nm-thick InAlGaN layer grown under identical conditions.
The composition determined on the reference sample is assumed for the sample discussed here. HRXRD full-width at
half-maximum measurements of the GaN buffer layer yielded
260 and 330 arcsec for the (002) and (102) reflex, respectively. Inductive sheet-resistance mapping of the 2-inch wafer
resulted in an average value of 230 /sq. The value remained
unchanged upon the repetition of the sheet-resistance mapping
after one week of air exposure. This confirms the successful
passivation of the oxygen-sensitive barrier-layer surface by
in situ SiN passivation [10].
B. Device Processing
Although the in situ SiN passivation layer yields a very
good protection for the barrier layer, additional etch steps are
required to remove the SiN locally for mesa formation and

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IEEE ELECTRON DEVICE LETTERS, VOL. 33, NO. 4, APRIL 2012

Fig. 1. Transfer characteristics of the device with draincurrent IDS and

transconductance gm over the gate voltage VG . The drain voltage VDS is kept
constant at 10 V.

contact deposition. An optimized low-damage fluorine-based

etch process [11] has been applied prior to the mesa etching and
ohmic contact processing. The process minimizes the surface
damage to the barrier layer, which usually occurs due to the
fluorine ion bombardment. Mesa isolation has been realized
by a chlorine-based plasma etch process. The ohmic contact
metal stack Ti/Al/Ni/Au has been deposited directly on the
barrier layer after the local SiN removal. The subsequent rapid
thermal anneal was performed under nitrogen atmosphere at
800 C for 30 s. For the gate processing, an equivalent fluorinebased etch process has been applied to remove the SiN locally.
Additionally, the same plasma process has been applied in the
gate trench as a surface treatment of the barrier layer directly
after SiN removal and before metal evaporation. During the
gate metal evaporation, the sample was mounted on a rotating
carrier under a slightly inclined angle to prevent the formation
of gaps between the metal and the SiN passivation layer. The
gate stack consisted of Ni/Au. A subsequent gate anneal has
been performed at 400 C for 10 min to stabilize the Schottky
contact with respect to the Schottky-barrier height.
III. R ESULTS AND D ISCUSSION
A. DC Characteristics
Sheet-resistance RSH and contact-resistance RC measurements on passivated transfer length method patterns yielded
250 /sq and 0.47 mm, respectively. From the in situpassivated van der PauwHall structures, the carrier concentration ns was found to be 1.25 1013 cm2 . This confirms the
SiN to enhance the carrier concentration. As for an unpassivated
structure, one would expect from the theory an ns in the range
of 0.81 1013 cm2 [1, eq. (51)]. The electron mobility was
1970 cm2 /V s. The transfer characteristics of a 1-m gatelength device are presented in Fig. 1. With the drain voltage VDS
being 10 V, the transconductance gm reaches a maximum of
250 mS/mm at VGS = 1.8 V. The threshold voltage Vth is
as high as 0.65 V, and the maximum draincurrent exceeds
500 mA/mm. As the barrier layer is extremely thin and also due
to the lack of a gate dielectric, a gate-diode turnon occurs quite
early and IG is already 10 mA/mm at VGS = 2 V. It exceeds

Fig. 2. DC output characteristics of a 1-m gate-length device for different

gate voltages VGS .

100 mA/mm at a gate voltage of VGS = 2.8 V. Nevertheless,

for such a thin barrier layer and the device being Schottkygated, a high on/off ratio of more than three orders of magnitude
is achieved. Also, the OFF-state gate and draincurrents are
significantly below 1 mA/mm each.
The dc output characteristics ID (VDS ) of the device are
presented in Fig. 2. For high drain voltages, the saturation
current exhibits a negative slope which can be attributed to the
thermal effects. As already discussed with the transfer curve,
a significant gatecurrent flows for VGS > 2 V. This effect
influences the linear region of the output characteristics. For
higher gate voltages, the ID (VDS ) plots do not start at the origin
any more. Even a negative draincurrent occurs for the very
first onset of the device, which originates from the applied gate
potential being higher than the drain potential, thus a forward
biased gate diode which draws current from both, the source
and the drain contact. This limitation of the bias operating
region of our device could be circumvented by a MISHFET
approach. For example, a thin aluminum oxide layer deposited
directly before gate metal deposition would effectively suppress
the gatecurrent [12]. One could even apply the same in situ
SiN as in this letter and simply stop the local fluorine etch process several nanometers before the SiN is completely removed.
The gate metal deposition on these remaining few nanometers
of SiN would result in a MISHFET device with significantly
reduced gatecurrent. Although the threshold voltage would
shift to a negative value in this case, it might be a suitable
approach to be combined with more sophisticated normally
off concepts, like nonpolar, semipolar, or polarization-reduced
barrier layers, where a fluorine implantation is not mandatory
to achieve an E-mode operation.
B. Pulsed IV Characteristics
Pulsed output characteristics for different quiescent points
are shown in Fig. 3. The applied pulsewidth was 200 ns with
a duty cycle of 0.02%. Three different quiescent points were
chosen. With the gate and drain voltage both at zero volts, the
self-heating of the device can be suppressed (stress-free measurement). With VGS = 3 V and VDS = 0 V, the influence
of the traps below the gate contact is investigated (gate-lag

KETTENISS et al.: QUATERNARY ENHANCEMENT-MODE HFET WITH IN SITU SiN PASSIVATION

521

the unity current gain cutoff frequency fT and the maximum

frequency of oscillation fmax are 4.6 and 18 GHz, respectively.
For the E-mode devices, higher fT LG values have already
been reported [4], [5]. Our comparably low values are related to
the following reasons: First, we have an early gate-diode turnon
and second, we have a reduced carrier mobility in the intrinsic
device due to the incorporated fluorine ions being very close to
the channel.
IV. C ONCLUSION

Fig. 3. Pulsed output characteristics for the different VGS /VDS quiescent
points. Stress-free (0/0 V); Gate-lag (3/0 V); Drain-lag (3/25 V) with a
dc measurement as reference.

E-mode devices have been realized by the combination of

a thin barrier layer and a fluorine-based plasma treatment. An
excellent device passivation has been achieved by an in situ SiN
deposition. It was demonstrated that the in situ SiN possesses
several advantages. It acts as a protective layer after growth,
enhances the 2DEG carrier concentration, and ensures a lowtrap density passivation layer.
R EFERENCES

Fig. 4. Short-circuit current gain |h21 | and MUG for VDS = 6 V and
VGS = 2.25 V.

measurement). The third quiescent point was a deep class-B

operation point with VGS = 3 V and VDS = 25 V (drain-lag
measurement). With this measurement, the trap states in the
drain region of the device can be visualized.
The comparison of the pulsed measurements with the dc
characteristics shows an improved maximum draincurrent due
to the reduced self-heating effect. The difference within the
three types of pulsed measurements is negligible. In particular,
the drain-lag measurement shows the same draincurrent as
the stress-free measurement and only a minor knee walkout.
This implies that the passivation effect in the access region
is significantly enhanced in comparison to the other results
already published [5]. Hence, the semiconductor material, the
in situ SiN, and all interfaces are of high quality and have
only small trap densities. This observation demonstrates the
excellent properties of the in situ SiN passivation technique.
C. RF Characterization
Small-signal S-parameter measurements were carried out
using an HP 8510C network analyzer at different bias conditions. Fig. 4 shows the short-circuit current gain (|h21 |) and
the maximum unilateral power gain (MUG) for a drain bias
of 6 V and a gate bias of 2.25 V. The extracted values for

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