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hFE 70 40
FIGURE 1. PINOUTS OF HFA3046/3096/3127/3128 SOIC
CCB 500 600 fF PACKAGED TRANSISTOR ARRAYS
fT 9 5.5 GHz
Circuit Design
P1DB (IC = 10mA, VCE = 5V, 7.6 6.2 dBm
fO = 1GHz) High-Gain Low-Noise Amplifier
IP3 (IC = 10mA, VCE = 5V, 17.6 16.2 dBm One important design requirement for an RF amplifier is the
fO = 1GHz) accurate control of input and output impedance levels. This
is especially important if the amplifier is to interface with
NF (RS = 50Ω, IC = 5mA, 3.5 3.0 dB
VCE = 3V, fO = 1GHz) matched source and load impedances.
Based on S-parameter measurements, for a common-emitter
The SOI process has the advantage of lower DC and AC configuration, transistors of HFA3127 exhibit a prematched
parasitic leakage currents as opposed to junction isolation, condition on the input side over a wide range of frequencies.
which leads to good isolation between transistors. The package lead and bond wire inductances for these
Furthermore, an SOI process provides substantially lower transistors make the input impedance close to 50Ω. For
collector to substrate capacitance, immunity to any possible IC = 5mA - 10mA, VCE = 2V - 5V, the input VSWR of Q2 and
latch-up between the devices, and superior radiation Q5 was less than -10dB for frequencies of 800MHz to
hardness. 3000MHz. Furthermore, for these transistors, a good output
match, output VSWR < -10dB for frequencies 300MHz to
The HFA3127 is used for the two stage matched (800MHz to 3000MHz, could be accomplished through bypassing the
2500MHz) high-gain amplifier design, while the HFA3096 is collector with a 100Ω resistor. As the single stage amplifiers
used for the 10MHz to 600MHz wideband feedback amplifier. built with Q2 and Q5 both show good input and output
matching, they can be cascaded for higher gain without
requiring an impedance transforming network. Figure 2 shows
the final two stage amplifier. The advantage of this circuit is its
simplicity. This design does not use any tuning inductors or
capacitors which would tend to increase the cost of the circuit.
Furthermore, this circuit accomplishes higher gain by
cascading two amplifier stages built with integrated transistors.
3-1 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000
Application Note 9315
VCC + R1 R2 R3 R4
- 39kΩ 100Ω 39kΩ 100Ω –5
C2 1nF C3 1nF
under two different bias conditions: VCC = 3V, IC2 = IC5 = FREQUENCY (GHz)
5mA; and VCC = 5V, IC2 = IC5 = 10mA. As can be seen from
FIGURE 3B. INPUT VSWR
Figure 3, the input and output VSWR is less than -10dB for
frequencies greater than 800MHz. The amplifier shows better
performance at the expense of higher power dissipation (IC =
0
10mA and VCC = 5V) except the noise figure. For IC2 = IC5 =
10mA, the amplifier gains are 18.7, 8.8, and 6.6dB at
frequencies of 900MHz, 1800MHz, and 2200MHz, -5
40
6
30
NOISE FIGURE (dB)
5
GAIN (dB)
IC = 10mA, VCC = 5V
IC = 10mA, VCC = 5V
20
4
10
IC = 5mA, VCC = 3V
IC = 5mA, VCC = 3V
0
3
0 1 2 3 0 0.5 1 1.5 2
FREQUENCY (GHz) FREQUENCY (GHz)
3-2
Application Note 9315
Wideband Amplifier
OUTPUT
A well known simple amplifier configuration which achieves
flat gain and broadband matching without losing excessive
C3 signal power is shown in Figure 6. The simultaneous use of
both shunt and series feedback gives rise to broadband
THROUGH
HOLE resistive input and output impedances [2, 3].
R4 Figure 7 shows a similar version of the double feedback
HFA3127 wideband amplifier circuit realized with the HFA3096. This
CBP R3
C1
design takes advantage of the PNP transistors (Q4 and Q5)
R1
C2 INPUT available on the HFA3096, to bias amplifying transistor Q2
R2 CBP
for good temperature stability.
RF
CBP VO
LCHOKE RS
RL
+ VS
VCC - RE
3-3
Application Note 9315
15 0
-10
10
VSWR (dB)
OUTPUT VSWR
GAIN (dB)
-20
5
-30
INPUT VSWR
0 -40
107 108 109 107 108 109
FREQUENCY (Hz) FREQUENCY (Hz)
Summary
A detailed process of designing a high-gain low-noise and a
VCC
wideband amplifier using the Intersil UHF transistor arrays is
summarized.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
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