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William Stallings

Computer Organization
and Architecture
6th Edition
Chapter 7
Input/Output
7.1
7.2
7.3
7.4
7.5
7.6
7.7

External Devices
I/O Modules
Programmed I/O
Interrupt-Driven I/O
Direct Memory Access
I/O Channels and Processors
The External Interface

Input/Output Module

Input/Output Problems
Wide variety of peripherals
Delivering different amounts of data
At different speeds
In different formats

All slower than CPU and RAM


Need I/O modules
Third key element next to CPU and Memory

Generic Model of I/O Module

Interface to CPU and Memory


Interface to one or more peripherals
Why not connect peripherals directly to bus?
Wide variety of peripherals w/ various of methods
Difference in data transfer rate
Different data formats and word length

2 kinds of interface
Interface to the processor and memory via the
system bus
Interface to one or more peripheral devices by
tailored data links

7.1 External Devices

7.1.1 Keyboard/Monitor/Disk Drive

Human readable

Most common means of Computer Interface

Screen, printer, keyboard

Machine readable
Magnetic disks
Monitoring and control (sensor)

Communication
Modem
Network Interface Card (NIC)

Keyboard

Basic unit of exchange is the character


Associated with each character is a code (7-8 bits)
IRA (International Reference Alphabet )
Depressing a key generates an electronic signal, interpreted
by the transducer and translated into bit pattern

Monitor
IRA code characters are transmitted to an external device
from I/O module, and the transducer at the device interprets
this and sends the required electronics to the output device

Disk Drive
Contains electronics for exchanging data, control and status
signal w/ I/O module and electronics for disk read/write
mechanism

External Device Block Diagram

7.2 I/O Modules


Module function
Control & Timing
CPU Communication
Device Communication
Data Buffering
Error Detection

Module structure

7.2.1 Module Function


Control and timing
E.g. the control of transfer of data from an external
device to the processor

I/O steps
1. Processor checks the status of attached device
thru I/O module
2. I/O returns the status of device
3. The processor request data transfer to the I/O
module
4. I/O module obtains data from the device
5. The data is transferred from I/O module to the
processor

Processor communication
E.g. I/O module should communicate with the
processor and external device
Command decoding
READ SECTOR for disk drive

Data
between I/O module and processor over bus

Status reporting
Busy / Ready for requested job

Address recognition
Recognize one unique address for each peripheral it controls

Typical I/O Data Rates


Device communication
Commands, status, and data

Data buffering
Difference rate in the transfer rate between
memory/processor and device

Error detection
Mechanical and electrical error
Parity bit

7.2.2 I/O Module Structure

I/O Module Diagram

Vary considerably in complexity and the number


of external devices that I/O modules control
To allow the processor to view a wide range of
devices in a simple way
May hide the detailed timing, formats and electronics
I/O channel (I/O processor) : takes on the most of
the detailed processing burden mainframe
I/O controller (device controller) : primitive and
requires detailed control microcomputer

I/O Module Decisions

Input Output Techniques

Programmed I/O

Hide or reveal device properties to CPU


Support multiple or single device
Control device functions or leave for CPU
Also O/S decisions
e.g. Unix treats everything it can as a file

I/O occurs under the direct and continuous control of


the program requesting I/O

Interrupt driven I/O


Program issues an I/O command and then continues
to execute, until it is interrupted by the I/O hardware
to signal the end of I/O operation

Direct memory access (DMA)


A specialized I/O processor takes over control of an
I/O operation to move a large block of data

7.3 Programmed I/O

Programmed I/O - detail

CPU has direct control over I/O

Sensing status
Read/write commands
Transferring data

CPU waits for I/O module to complete operation


Wastes CPU time

I/O Commands

CPU requests I/O operation


I/O module performs operation
I/O module sets status bits
CPU checks status bits periodically
I/O module does not inform CPU directly
I/O module does not interrupt CPU
CPU may wait or come back later

Addressing I/O Devices

CPU issues address


Identifies module (& device if >1 per module)

CPU issues command


Control - telling module what to do
e.g. spin up disk

Under programmed I/O data transfer is very like


memory access (CPU viewpoint)
Each device given unique identifier
CPU commands contain identifier (address)

Test - check status


e.g. power? Error?

Read/Write
Module transfers data via buffer from/to device

I/O Mapping

7.4 Interrupt Driven I/O

Memory mapped I/O

Overcomes CPU waiting


No repeated CPU checking of device
I/O module interrupts when ready

Devices and memory share an address space


I/O looks just like memory read/write
No special commands for I/O
Large selection of memory access commands available

Isolated I/O
Separate address spaces
Need I/O or memory select lines
Special commands for I/O
Limited set

Interrupt Driven I/O


Basic Operation
CPU issues read command
I/O module gets data from peripheral whilst
CPU does other work
I/O module interrupts CPU
CPU requests data
I/O module transfers data

CPU Viewpoint
Issue read command
Do other work
Check for interrupt at end of each instruction
cycle
If interrupted:Save context (registers)
Process interrupt
Fetch data & store

See Operating Systems notes

Design Issues

Identifying Interrupting Module (1)

How do you identify the module issuing the


interrupt?
How do you deal with multiple interrupts?

Different line for each module

i.e. an interrupt handler being interrupted


Multiple interrupt lines
Software poll
Daisy chain (hardware poll, vectored)
Bus arbitration (vectored)

Not only Limits number of devices


Since dedicating more than few lines of bus or
processor pins to interrupt line, each line will have
multiple I/O modules attached to it
One of the followings used for each line

Software poll
CPU asks each module in turn
TESTI/O command
The processor reads the status register of each I/O module

Slow

Identifying Interrupting Module (2)

7.5 Direct Memory Access

Daisy Chain or Hardware poll

Drwabacks of Programmed and Interrupt-Driven


I/O
Interrupt driven and programmed I/O require
active CPU intervention

Interrupt Acknowledge sent down a chain


Module responsible places vector on bus
The address of I/O module
Unique identifier

CPU uses vector to identify handler routine

Bus Master
Module must claim the bus before it can raise
interrupt
When CPU detects interrupt, it responds on the
interrupt Acknowledge line. Then the requesting
module places its vector on the data line
e.g. PCI & SCSI

Transfer rate is limited


CPU is tied up

DMA is the answer

DMA Function

DMA Operation

Additional Module (hardware) on bus


DMA controller takes over from CPU for I/O
Transfer data from/to memory over system bus

CPU tells DMA controller:-

DMA use bus when CPU does not need it


Force CPU to suspend operation temporarily
Cycle stealing

DMA Module Diagram

Read/Write
Device address
Starting address of memory block for data
Amount of data to be transferred

CPU carries on with other work


DMA controller deals with transfer
DMA controller sends interrupt when finished

DMA Transfer
Cycle Stealing
DMA controller takes over bus for a cycle
Transfer of one word of data
Not an interrupt
CPU does not switch context

CPU suspended just before it accesses bus


i.e. before an operand or data fetch or a data write

Slows down CPU but not as much as CPU doing


transfer

Then,
What effect does caching memory have on
DMA?
Hint: how much are the system buses
available?
DMA mechanism can be configured in a variety
of ways

DMA Configurations (1)

Single Bus, Detached DMA controller


Each transfer uses bus twice
I/O to DMA then DMA to memory

CPU is suspended twice

DMA Configurations (2)

Single Bus, Integrated DMA controller


Controller may support >1 device
Each transfer uses bus once
DMA to memory

CPU is suspended once

DMA Configurations (3)

Separate I/O Bus


Bus supports all DMA enabled devices
Each transfer uses bus once
DMA to memory

CPU is suspended once

7.6 I/O Channels

I/O Channel Architecture

I/O devices getting more sophisticated


e.g. 3D graphics cards
CPU instructs I/O controller to do transfer
I/O controller does entire transfer
Improves speed
Takes load off CPU
Dedicated processor is faster

7.7 The External Interface

7.7.1 Types of interface

Parallel interface
Serial interface
I/O module to/from peripheral (write op.)

Connecting devices together


Bit of wire?
Dedicated processor/memory/buses?
E.g. FireWire, InfiniBand

I/O module send a control signal requesting


permission for sending data
The peripheral acknowledges the request
I/O module transfer data
The peripheral acknowledges

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7.7.2 Point-to-point & Multipoint

7.7.3 IEEE 1394 FireWire

Point-to-point

Keyboard
Printer
External modem

Multipoint external interface


Mass storage device (Disk, tape drive)
Multimedia (CD-ROM, Video, Audio)

High performance serial bus


Fast
Low cost
Easy to implement
Also being used in digital cameras, VCRs and TV

FireWire Serial Bus


InfiniBand

FireWire Configuration

Simple FireWire Configuration

Daisy chain
Up to 63 devices on single port
Really 64 of which one is the interface itself

Up to 1022 buses can be connected with


bridges
Automatic configuration
No bus terminators
May be tree structure

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FireWire 3 Layer Stack

FireWire Protocol Stack

Physical
Transmission medium, electrical and signaling
characteristics

Link
Transmission of data in packets

Transaction
Request-response protocol

FireWire - Physical Layer

FireWire - Link Layer

Data rates from 25 to 400Mbps


Two forms of arbitration

Two transmission types

Based on tree structure


Root acts as arbiter
First come first served
Natural priority controls simultaneous requests
i.e. who is nearest to root

Fair arbitration
Urgent arbitration

Asynchronous
Variable amount of data and several bytes of transaction
data transferred as a packet
To explicit address
Acknowledgement returned

Isochronous
Variable amount of data in sequence of fixed size packets at
regular intervals
Simplified addressing
No acknowledgement

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FireWire Subactions

7.7.4 InfiniBand
I/O specification aimed at high end servers
Merger of Future I/O (Cisco, HP, Compaq, IBM) and
Next Generation I/O (Intel)

Version 1 released early 2001


Architecture and spec. for data flow between
processor and intelligent I/O devices
Intended to replace PCI in servers
Increased capacity, expandability, flexibility

InfiniBand Architecture

InfiniBand Switch Fabric

Remote storage, networking and connection


between servers
Attach servers, remote storage, network devices
to central fabric of switches and links
Greater server density
Scalable data centre
Independent nodes added as required
I/O distance from server up to
17m using copper
300m multimode fibre optic
10km single mode fibre

Up to 30Gbps

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InfiniBand Operation

InfiniBand Protocol Stack

16 logical channels (virtual lanes) per physical


link
One lane for management, rest for data
Data in stream of packets
Virtual lane dedicated temporarily to end to end
transfer
Switch maps traffic from incoming to outgoing
lane

Foreground Reading
Check out Universal Serial Bus (USB)
Compare with other communication standards
e.g. Ethernet

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