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*
Centro Nacional de lnvestigacion y Desarrollo Tecnologico, Mexico
lnstituto de lnvestigaciones Electricas, Mexico
**
ABSTRACT
The fast and constant (evolution of the
electronic *s circuits in the last decade, require a
similar behavior from the power supply systems,
searching for more competitive electronic *s
equipment (with greater storage capacity, better
relationship of weight, volumc?, cost, etc.).
This paper present,, the results of the
implementation of a Two stages AC/DC preregulator".
using a BOOSTco,vverter /as a power
factor corrector), and a Full- Bridge ZVS-PWM
converter, in order to improve the dynamic
features of the DC bus, working as well as a
battery charger within the scheme of Distributed
Power Supply in which it will be used.
1. INTRODUCTION
Nowadays, it is not enough to increase the power
density (which implies the usi: of hgh frequency
conversion strategies, very elaborated mounting
techniques, etc,) to meet the requirements of
modularity, redundancy, battery backing which appear
to be necessary for the next generation of power
supplies.
Distributed architectures in a power supply system (fig.
1) solve part of the problem, introducing new challenges
and opening very attractive research areas. The most
interesting challenge in the primary stage of power
supply is probably the power factor correction.
ON-BOARD Cmveiles ,-\
scheme.
This work was done under a collaboration program between
IIE and CENIDET.
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3.1 Operation
Asuming that, the transistor is just tumed on, the
inductor current rises from its last value, to the current
reference level, in this moment the transistor is tumed
off and the inductor current decreases. When a complete
oscillation cycle finishes, the driver tums on the
transistor and a new cycle begins.
The current reference is a sine waveform which is a
sample of the rectified line voltage, multiplied by the
output of the error amplifier. The magnitude of' the
voltage error amplifier (VEA) is proportional to the
output power stage and reference voltages. If the output
voltage falls, the VEA rises and the current reference
too, so this cause an increment in the input line current.
On the other way, if the output voltage rises, the VEA
as well as the current reference decrease, causing a
decrement in the input line current.
Asc +Sm+RT*CT
RFC =
Where:
R, and C, are the oscillator components (131.
A, is the amount of slope compensation.
S,, The downslope as reflected to the input of the
PWM comparator.
3. Bandwidth must be in accordance with the line
frequency.
The voltage loop bandwidth should he set such that it
rejects the 100 Hz or 120 Hz ripple which is presented
at the output voltage typical bandwidth range in FPC
application is normaly bellow 15 Hz. Finally, the main
compromise is between transient response and
distortion.
4. Outout voltage Vout = 360 Vcd .
5. The voltage where the inductor dries out V,
(inductor design).
The first step and probably the most important premise
540bH
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where:
RT and C, are the oscillator components (131.
etc.
Input line current and voltage, are shown in the figure
5, in which the PF compensation can be seen in the
input current waveform. Figure 6 shows load variations
effect on the prototype efficiency, for differents input
voltage conditions. Another important result is that the
line regulation is as well as 0.55 5%.
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