Table of Contents

1.

Acknowledgement
EC-316:
2. Synopsis
MICROPROCESSORS
3. Project Description
4. Schematic Diagram
5. Board
file PE PATTA
PATTE
6. Main
Program
LFSR
BHAVNA
RACHURI and
47/EC/13
JATIN MAHAJAN 68/EC/13
7. Testing
and Debugging
8. Gantt chart: A comparison
9. Conclusion
10. Bibliography

PATTE PE PATTA

Acknowledgement
We would like to express our deepest gratitude and
heartfelt thanks to Professor Dhananjay V. Gadre for
giving us this wonderful opportunity to learn and grow.
Your constant vigilance, guidance and, mentorship has
enabled us to remain motivated and focussed
throughout. Had it not been for your continuous
attempts to push our limits, we would have never
achieved the best in the stipulated time.
We also acknowledge the support and help provided
to us by the entire CEDT, NSIT team, without which it
would have been extremely difficult to complete in the
given time frame.
We would also thank our parents, family, friends and
all the batch-mates, who have constantly supported
and helped us throughout the project.

Bhavna Rachuri 47/EC/13

Jatin Mahajan 68/EC/13

PATTE PE PATTA

Synopsis
Patte pe patta is a very popular 52-card deck game.
Players throw cards alternatively playing to make a
match. A deck of 52 cards (mapped on 52 integers,
here) is distributed randomly and equally amongst two
players so that each player has a set of 26 cards. One
of the two players, starts the game by turning a card
from the top of his/her pile followed by the other player
turning a card from his/her pile. A match is made when
the same card (number) is thrown twice (once by each
player) and the whole lot of piled cards, thrown up till
that point is taken by the player who makes the match.
The game ends with one of the players exhausting
his/her cards; effectively winning the game.

Implementation using 8085:

The backbone of the game lies in the effective
generation of random numbers. To achieve this
objective, double-layered randomization is
implemented. The first layer entails the latching of a
continuous counters value at users discretion that
serves as the seed for the Linear Feedback Shift
Register (LFSR). The LFSR in turn generates numbers
from 0 - 51 pseudo-randomly.

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PATTE PE PATTA
These numbers serve as the cards for the players
mapped to respective card numbers (0 -12) and deck
(clubs, diamonds, hearts and spades).

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PATTE PE PATTA

Project Description

The block diagram represents the interconnection

between various components of our project. The Intel
8085 microprocessing unit is interfaced with a 32K
EEPROM and 32K CMOS Static RAM for memory and
storage. 5 input switches serve the purpose of Reset,
Counter latch, SID and the two player buttons. A 16X2
LCD module is used to display the proceedings of the
game in the form of the card number, card deck,
match and win situations. The Programmable
Peripheral Interface Intel 8255 is used to interface the
input switches and the LCD. A USB connector
supplied with 5-volts powers the entire system.

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PATTE PE PATTA

Schema
tic

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PATTE PE PATTA

Board Layout

Partially
soldered
board

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PATTE PE PATTA

Main Program

Match

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End

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PATTE PE PATTA

Linear Feedback Shift

Register - LFSR
LFSR:

LOOP6:

MOV A,C
RRC
JNC LOOP6
MOV A,B
ANI 068H
CMA
ANI 068H
MOV D,A
MOV A,B
ANI 097H
ADD D
MOV B,A
MOV A,C
RRC
MOV C,A
MOV A,B
RAR
MOV B,A
MOV A,C
RAL
RRC
MOV C,A

The game essentially involved cards being turned one

by one and stacking up. Therefore, the obvious choice
to implement this was using the memory stack to store
the cards being thrown by the players. The Last In First
Out characteristics of the stack enables sequential
appending of the card stack in the unlucky players
stack. The complexity of the code rendered us with no
registers for temporary variable storage. Hence,
specific memory locations have been used many times
in the code to store temporary data. The complete
code when incorporated with the LCD output
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PATTE PE PATTA
statements resulted in 712 lines of code with a size of
1.4kB.

Testing & Debugging

The terminal stage of the project before it is presented
consists of testing the circuit and debugging it to ensure
complete functionality. This procedure mainly includes
two processes:

Hardware testing/debugging
Software testing/debugging

Hardware testing is done prior to software. Since, the

code has to finally run on the designed hardware board,
it is essential to make sure that all the components are
fully functional before uploading the code. The
components that frequently malfunctioned in our project
and many others were ROMs, shift registers, switches
and in some cases, the microprocessor 8085 itself.
Hardware debugging can be a tedious job, especially
after the board has been soldered. It is therefore, highly
recommended that all switches should be checked prior
soldering. The ICs are not soldered on the board directly.
Instead, an IC base is soldered on which the IC is
mounted. Hence, these can only be tested once the
circuit is completely soldered.
SID/SOD test: The preliminary test for checking all the
basic components and the decoding logic and circuit is
the SID/SOD test. A predefined code is uploaded on the
ROM that enables the LED connected at the SOD pin to
remain ON unless the SID button is pressed. If the SOD
LED is switched OFF every time a button connected at
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PATTE PE PATTA

SID is pressed, then it can be concluded that the board

has been properly soldered, the decoding logic is correct
and, the major components are working fine.
LCD testing: The display device that has been used is a
16x2 LCD. When the system is reset and LCD hasnt
been initialised, then it should either light up (when the
backlight pin has been connected to the power supply)
or should display a series of dark rectangles. This project
has the backlight disabled mainly to conserve power.
The LCD used here has been initialised to display a
cursor blinking at the first position of the first row when
the system is reset. A resistive potentiometer has also
been connected to the display to adjust contrast.
Software debugging involves a thorough study of the
written code. There is no predefined procedure and the
code has been debugged using trial and error. The
procedure becomes more difficult and complex in the
cases where many subroutines are called, extensive
jump statements are used to form loops and, contents of
certain registers are stored in other registers
temporarily. While working with loops, it should be made
sure that the loop termination condition is not
repeatedly reinitialised in the loop. Debugging should be
done by checking fragments of code to track down the
faulty part. Syntax errors are shown while assembling
the code in a simulator to create .obj files. Logical errors
are the most tedious and difficult, and it requires careful
inspection of the entire code line by line.

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Fully
soldered
board and
EEPROM
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programm

PATTE PE PATTA

Gantt chart: A
comparison
Actu
al

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Propose
d

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PATTE PE PATTA

Conclusion
A quick glance at the Gantt chart shall reveal shortcomings of
our project. We must concede that we were unable to meet
most of our deadlines on the hardware simulation and testing
front. Although in our defence, we will also like to concede
that:
We overestimated our and PCBPower (PCB printing
company)s efficiency.
We were sceptical of our efforts throughout the journey.
Here Id like to quote former Intel CEO and personal
computing pioneer, Andy Groves book title: Only the
Paranoid survive. It was our scepticism, our paranoia and our
cynicism about our efforts that helped us rise out to the top
despite falling short on deadlines. Delayed by 15 days, our
final schematic and board file didnt have a single error and
we received no warnings or defaults from the printing
company.
Over and above, while the Gantt chart enabled us to
strategize our activities and gave us direction throughout, it
also outlined our inherent shortcoming in thinking ahead of
time, as most of my fellow batch mates would agree.

Bhavna Rachuri 47/EC/13

Jatin Mahajan 68/EC/13

PATTE PE PATTA

Clubs Diamonds Hearts Spades

Bibliography
1.For Microprocessor 8085 theory and concepts:
Microprocessor Architecture, Programming and
Applications with the 8085, Sixth Edition by
Ramesh Gaonkar.
Online lecture series by Ajit Pal:
https://www.youtube.com/watch?
v=liRPtvj7bFU&list=PL0E131A78ABFBFDD0
2.For LFSR:
http://www.eng.auburn.edu/~strouce/class/elec625
0/LFSRs.pdf
https://www.maximintegrated.com/en/appnotes/index.mvp/id/4400
3.For other peripherals, the following datasheets:
ATMEL 256 (32K x 8) High-speed Parallel EEPROM:
AT28HC256N
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HITACHI 32,768-word 8-bit High Speed CMOS
Static RAM: HM62256B
3-Line to 8-line decoders/demultiplexers:
SN74LS138
Octal D-type transparent latch; 3-state: 74HCT573
LCD MODULE: ADM1602K-NSW-FBS-3.3v
4.For Programmable Peripheral Interface, INTEL 8255:
Microprocessor Architecture, Programming and
Applications with the 8085, Sixth Edition by
Ramesh Gaonkar.
5.For EEPROM Programmer:
Quick Start Guide by CEDT, NSIT

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Jatin Mahajan 68/EC/13