Analysis, Design, and Evaluation of Three-Phase Three-Wire Isolated AC-DC Converter

Implemented with Three Single-Phase Converter Modules

Laszlo Huber, Misha Kumar, and Milan M. Jovanovi

Dinggang Ping and Gang Liu

Delta Products Corporation

P.O. Box 12173
5101 Davis Drive
Research Triangle Park, NC 27709, USA

Shanghai Design Center,

Delta Electronics (Shanghai) Company Ltd,
Shanghai 201209,
Peoples Republic of China

Abstract In this paper, a control method for three single-phase

isolated ac-dc converter modules employed to implement an
isolated three-phase, three-wire ac-dc converter is presented and
its detailed design procedure provided. In the described control
the input voltages of the Yconnected single-phase modules with
floating common Y point are kept within a safe range by
equalizing their input admittances. It is shown that for
obtaining equal input admittances of the three PFC front stages,
the outputs of the PFC voltage controllers should be equal. This
is achieved by adjusting the reference currents of the current
controllers in the output dc-dc stages. The performance of the
presented control with both balanced and unbalanced source
voltages, as well as with a phase fault (open or short circuit) is
evaluated by Matlab/Simulink simulations and verified
experimentally on a 6-kW prototype.

operation has also to be guaranteed at startup, as well as in

case of phase failure (open and short circuit) and load
transients.
The balancing control between the three single-phase
modules can be achieved with additional passive components
used to create a virtual (artificial) neutral point and by using
balancing control methods [1]-[8], or without additional
passive components by using only balancing control methods
[9]. In [1]-[3], three auxiliary transformers with Y-connected
primaries and -connected secondaries are used to create an
artificial neutral point (ANP). The Y point of the modules is
connected to the ANP. With the ANP, the three single-phase
modules operate similarly as in the case when the source
neutral point is available. When the system is unbalanced, a
zero-sequence current flows in the auxiliary transformers that
can result in significant losses. To suppress the zerosequence current, a balancing control method can be
employed, where the output reference currents of the singlephase modules, which for a balanced system are equal, are
adjusted based on the phase angle of the zero-sequence
current [1]. The drawback of using auxiliary transformers is
the increased size and cost. Typically, the VA rating of the
additional magnetic components is 5% of the VA rating of
the rectifier [1].
In [4]-[8], a virtual neutral (VN) point is created by a star
connection of three equal resistors. When the three-phase
voltage source is balanced, the potential of the virtual neutral
point vVN is equal to the potential of the source neutral point
v0 and, therefore, the voltage across a star resistor is equal to
the corresponding phase voltage of the three-phase source.
Generally, the potential difference between the virtual neutral
point and the source neutral point is
v +v +v
vVN ,0 = vVN v0 = a0 b0 c0 ,
(1)
3

I. INTRODUCTION
Three-phase isolated ac-dc converters can be implemented
either with a direct three-phase PFC rectifier front end such
as the Vienna rectifier or the six-switch PFC boost rectifier
followed by an isolated dc-dc converter, or with three singlephase isolated ac-dc converters. Generally, the major
advantage of the modular implementation with three singlephase converters is its ease of power expandability. To be
able to employ single-phase modules designed for 220/277Vrms phase-to-neutral voltage in three-phase power systems
with nominal phase-to-phase voltage of 380/480 Vrms, the
three single-phase modules must be connected in star (Y)
configuration. The delta () configuration cannot be used
since it would require that single-phase modules be connected
across two phases, i.e., to a voltage exceeding their rating.
In applications where the neutral point of the three-phase
voltage source is available, the common point (Y point) of
the single-phase converter modules is connected to the source
neutral point and the three single-phase converters operate
independently from each other with their input voltages equal
to the respective phase-to-neutral voltages of the source.
However, in applications where the source neutral point is not
provided, such as, for example, in standard telecom power
supplies, any unbalance in the three-phase source phase
voltages and/or in the three single-phase modules will create
a potential difference between the Y point of the single-phase
modules and the source neutral point, resulting in oscillations
and significant variations of the input voltages of the singlephase converters [1]. For a stable and reliable steady-state
operation, i.e., operation where the input voltage always stays
within a specified range, a balancing control of the three
single-phase modules is necessary. The stable and reliable

978-1-4673-9550-2/16/$31.00 2016 IEEE

where, va0, vb0, and vc0 are the three-phase source phase-toneutral voltages. Therefore, if the phase voltages of the
three-phase source are unbalanced and contain a zerosequence component vZS, the zero-sequence component vZS
appears as voltage vVN,0, i.e., vZS=vVN,0, and, consequently, the
voltage across the star resistors will not contain the zerosequence component. The three-phase source phase voltages
can be reconstructed from the voltages across the star
resistors following the method presented in [11]. It should be
noted that in these implementations the Y point of the singlephase modules is not connected to the virtual neutral point.

38

In [4]-[8], the balancing control between the three singlephase modules is achieved by adjusting the output reference
current of the single-phase modules. In [4] and [5], the
output reference current of the single-phase modules is
adjusted based on the potential difference between the Y
point of the modules and the virtual neutral point, vY,VN,
whereas in [6]-[8], the output reference current of the singlephase modules is adjusted based on the voltages across the
star resistors. In addition, in [6]-[8], the amplitude of an
input phase reference current (regulated by average current
control) is obtained from the sum of three components: 1)
output of a PI-type average-voltage controller that regulates
the average value of the output voltages of the three singlephase PFC front ends, 2) an output-power feedforward term
(used to improve the control dynamics for load transients),
and 3) output of a P-type individual-voltage controller that
balances the unequal output voltages of the single-phase PFC
front ends. In [4]-[8], the phase currents are controlled to
follow the waveform of the voltages across the star resistors,
i.e., the source phase potentials referenced to the virtual
neutral point.
In [9], the balancing control between the three single-phase
modules is achieved by adjusting the output reference current
of the single-phase modules based on the output voltages of
the voltage controllers of the single-phase PFC stages
(employing average current control). Unlike in [4]-[8], in [9]
the phase currents are controlled to follow the input voltages
of the single-phase modules, i.e. the source potentials
referenced to the star point of the modules. Therefore, by
using the balancing control method in [9] compared to those
in [4]-[8], standard single-phase converter modules can be
easier modified for the three-wire three-phase systems.
Unfortunately, no control-oriented analysis is provided in [9].
Finally, in [12] a balancing control method that does not
require any load side balancing is described. In this method,
only two output voltages of the three single-phase PFC front
ends are balanced at the same time, which avoids the
coupling between the three single-phase modules. However,
it should be noted that in [12] the availability of the source
neutral point is required, but the Y point of the single-phase
modules is not connected to the source neutral point.
In this paper, principles of the balancing control method
introduced in [9] are explained and a detailed design
v a0

ia
vaY

v b0

Y
v c0

vbY

|vxY |

Iob
PFC

VoPFCb DC/DC

1-

dx

|vxY |

PI

voPFCref
VOLTAGE
FEEDFORWARD

|i xref |

|i x |

K m AB

vcY

C
See (11)

VOLTAGE
CONTROLLER

PI
A
|vxY |

Fig. 2 Block diagram of PFC control circuit.

procedure of the balancing controllers is provided. In

addition, the operation with unbalanced source voltages is
analyzed with respect to the power distribution between the
three single-phase modules, amplitude of the input phase
currents, and power factor of the modules. Finally, operation
and performance of the balancing control when one phase
voltage is reduced and when one phase is disconnected are
illustrated with Simulink simulations. Experimental results
obtained on a 6-kW prototype are also provided.
II. PRINCIPLES OF BALANCING CONTROL
The block diagram of the three single-phase converter
modules with Y connection at the input and parallel
connection at the output is shown in Fig. 1. The PFC stage of
the modules is implemented with average current control, as
shown in Fig. 2. The dc-dc stages are also implemented with
average current control, where the output-voltage controller is
common for all three dc-dc stages as shown in Fig. 3.
The three single-phase converter modules in Fig. 1 can be
equivalently represented with their input admittances Yk,
k{a,b,c}, as shown in Fig. 4 [10]. Using Kirchhoffs voltage
and current laws in phasor notation, the potential difference
between the Y point of the single-phase modules and the
source neutral point (neutral displacement voltage) can be
obtained as

VY0 =

V a 0 Y a + V b0 Y b + V c 0 Y c

Ya +Yb +Yc

(2)

If by the balancing control, the input admittances are kept

equal, i.e., Ya = Yb = Yc, the neutral displacement voltage in
ioa

Load

CURRENT
d DC/DCa
CONTROLLER a

Vo

Ioc
PFC

B v EAx

Vo

ic

PWM

v oPFCref

CURRENT
CONTROLLER

VoPFCa DC/DC

ib

DUTY-CYCLE
FEEDFORWARD

Ioa
PFC

voPFCx

Sx

Voref

VoPFCc DC/DC

iob
VOLTAGE
CONTROLLER

PI

PI

CURRENT
d DC/DCb
CONTROLLER b

io,ref
ioc

PI

CURRENT
dDC/DCc
CONTROLLER c

PI

Fig. 1 Block diagram of three single-phase rectifier modules with Y

connection at input and parallel connection at output.

Fig. 3 Block diagram of dc-dc control circuit.

39

va0

vb0

vc0

Yk =

Yb

ib

input admittance Yk can be obtained as

Ya

ia

ik
| vkY |

v Y0

ik ,ref
| vkY |

v EAk

= Km

Ck 2

, k {a ,b ,c} .

(6)

It follows from (6) that for equal input admittances

Ya = Yb = Yc = Yin ,

Yc

ic

(7)

the outputs of the voltage controllers as well as the voltagefeedforward terms in the PFC control circuits should be
equal, i.e.,

Fig. 4 Simplified equivalent circuit of three single-phase converter

modules.

(2) is

vEAa = vEAb = vEAc = vEA ,

(8)

Ca = Cb = Cc = C .

(9)

and

VY0 =

V a 0 + V b0 + V c 0
3

(3)

The voltage feedforward term C is obtained by considering

the total input power

Since for balanced source voltages VY0 = 0, the input voltage

of each single-phase PFC module is equal to the
corresponding source voltage.
For unbalanced source voltages where the amplitude of one
phase voltage is smaller than the amplitude of the other two
phase voltages, i.e., Va0 = mVm, m < 1, and Vb0 = Vc0 = Vm,
V Y0 =

1 m
V a0 ,
3

Pin,tot =

Ak Bk
Ck

= Km

| vkY | v EAk
Ck 2

C2 =

(4)

V b0 + V c0

_V

V b0

VkY ,RMS 2 ,

(11)

i.e., vEA does not depend on the input voltages, which is the
goal of the voltage feedforward control method. In the case,
no voltage feedforward is implemented, C = 1.
With equal input admittances, for balanced source
voltages, the total input power is equally distributed between
the three single-phase modules. However, for unbalanced
source voltages, to achieve equal input admittances, the total
input power cannot be equally distributed between the three
single-phase modules. In fact, a module connected to a
reduced source voltage will draw less input current and,
therefore, it will operate at reduced input power. The desired
distribution of the total power between the single-phase
modules that results in equal input admittances can be
achieved by implementing the balancing-control circuit as
shown in Fig. 6. In this balancing circuit, reference currents
iok,ref, k {a,b,c} of the current controllers in the dc-dc stages
are adjusted by currents iAdj,k, k {a,b,c} which are obtained at
the outputs of the balancing controllers that regulate the
difference between the average output-voltage of PFC
controllers
v EAk

, k {a, b, c} , (5)

Y0

V a0

k = a ,b,c

the output voltage of the voltage controllers in the PFC

control circuit is obtained as
Pin,tot
vEA =
,
(12)
Km

VcY = V c0 _ V Y0

V Y0

VkY , RMS 2 . (10)

k = a ,b,c

where, Km is the multiplier constant and Ck is the voltage

feedforward term. By the average current control, the current
controllers in the PFC stages enforce the input phase currents
to follow the reference currents, i.e., ik = ik,ref. Therefore, the

V c0

k = a ,b,c

= Yin

Then, it follows from (6)-(10), that if

i.e., VY0 is collinear with Va0, but it has opposite direction, as

shown in the phasor diagram in Fig. 5. It follows from Fig. 5
that the amplitude of the input voltage of all three single
phase PFC modules is smaller than Vm, i.e., VkY < Vm,
k {a,b,c}.
The condition for equal input admittances is derived by
recognizing that according to Fig. 2, the reference current of
the modules is given as
ik ,ref = K m

I k , RMS VkY , RMS

Re

_
V bY = V b0 V Y0

v EAavg =

Fig. 5 Phasor diagram of input voltages of single-phase PFC modules when

amplitude of phase a source voltage is smaller than amplitude of phase
b and c source voltages, i.e., for Va0 = mVm, m < 1, and Vb0 = Vc0 = Vm.

40

, k {a, b, c} ,

(13)

INJECTION i Inj
SIGNAL
SOURCE

io,ref

vEAa

i Adj,a

BALANCING
CONTROLLER a

i oa,ref

vResp,a

vEAa

PI

vEAb

i Adj,b

BALANCING
CONTROLLER b

i ob,ref

vEAb

PI

v EAc

i Adj,c

BALANCING
CONTROLLER c

i Adj,c = (i Adj,a + i Adj,b ) .

i Adj,c

where, TBC(s) is the transfer function of the balancing

controller.
The Bode plots of the plant transfer function, balancing
controller transfer function and balancing loop gain are
presented in Fig. 9, which were obtained at the zero crossing
of source voltage va0. The balancing controller is designed as
a PI controller. The crossover frequency of the balancing
loop gain is selected at 3.3 Hz to avoid interaction with the
PFC voltage loop whose bandwidth is 10 Hz. At the
crossover frequency, the magnitude of the balancing
controller transfer function is

(15)
80
80

va0

60
60
40
40

iAdj,a

|T| 20
[dB] 0
20

|TPL|

v b0

-40
-40

63.2dB

|TLG|

-20
-20

|TBC|

TBC ( s) = K p +

Ki
s

-63.2dB

-60
-60

vbY
vc0

PFCb

VoPFCb

ILoad,b

iAdj,c+Inj

where, VResp,a(s) is the response signal at the input of the

balancing controller a. Finally, the balancing loop gain is
defined as
TLG ( s) = TPL ( s) TBC ( s) ,
(17)

(14)

i Adj,a + Inj = i Adj,a + iInj .

ILoad,a

i Adj,b+Inj

1
2

To keep the total load current constant, injection signal iInj

is also injected in phases b and c with opposite sign and
with half of its value. The plant transfer function is defined
as
VResp ,a ( s )
,
(16)
TPL ( s ) =
I Adj ,a + Inj ( s )

To measure the balancing loop transfer function in phase

a, a perturbation signal is injected at the output of the a
balancing controller as shown in Fig. 8. This injection
current, iInj, is added to adjustment current iAdj,a,

VoPFCa

i Adj,b

Fig. 8 Block diagram of balancing control circuit with injection signal

source used for measuring balancing loop transfer functions.

and corresponding module PFC control voltage vEAk.

The design of the balancing controllers is performed
through simulations in Simulink and SIMetrix. In order to
reduce the simulation time, in the simulation circuit the dc-dc
output stages are replaced with current sources ILoad,k,
k {a,b,c}, which represent the load currents of the PFC
stages, i.e., the input currents of the dc-dc stages for balanced
source voltages, and with controlled current sources iAdj,k,
k {a,b,c}, which are controlled by the output signals of the
balancing controllers, as shown in Fig. 7. Instead of
adjusting the reference currents of the current controllers in
the dc-dc stages, the load currents of the PFC stages are
adjusted. However, to keep the total load current constant,
the total adjustment current must be zero. Therefore, the
balancing control circuit in Fig. 7 is modified so that the
adjustment current in phase c is generated as the negative
sum of the adjustment currents in phases b and c, i.e.,

PFCa

BALANCING
CONTROLLERb
PI

i Adj,a+Inj

1
2

vEAc

vEAavg

Fig. 6 Block diagram of balancing control circuit.

vaY

i Adj,a

i oc,ref

PI

BALANCING
CONTROLLERa
PI

iAdj,b

150
150

TPL

100
100

T
[o]
vcY

PFCc

VoPFCc

I Load,c

i Adj,c

50
50

00
-50
-50
100m
100m

TLG

PM = 43 o

TBC
200m
200m

400m
400m

11

22

44

10
10

fz=2Hz fC=3.3Hz

Fig. 7 Block diagram of three single-phase PFC modules used in

simulations.

20
20

40
40

100
100

Fig. 9 Bode plots of plant transfer function, balancing controller transfer

function, and balancing loop gain.

41

0.5

Pb 0 ,c 0 (m)
Ptot
0.4
1/3
0.3

PaY (m)
Ptot

Pa 0 (m)
Ptot

0.2

V c0

PbY ,cY (m)

Ptot

V b0 +V c0

Im

VcY = V c0 _ V Y0
_V

V Y0

Y0
Re

0.1
0

0.8

0.6 0.5 0.4

0.2

V b0

Fig. 10 Calculated power distribution between three single-phase modules.

Fig. 12 Phasor diagram of input voltages of PFC modules when phase a

is disconnected.

1.6

However, source a delivers only 15.4%, while sources b

and c each deliver 42.3% of the total power.
The calculated amplitude of the phase currents is shown in
Fig. 11. It should be noted in Fig. 11 that the amplitude of
phase current a decreases by only 1% when the amplitude
of phase voltage a decreases by 20%. It should also be
noted in Fig. 11 that at m = 0, the amplitude of phase currents
b and c increases by almost 60%. However, if phase a
is disconnected, the amplitude of phase currents b and c
increases by 73.2%. In fact, when phase a is disconnected
and the input admittances of phases b and c are equal, the
neutral displacement voltage VY0 is

Ib ,c (m )
Ib ,c (m = 1)

1.4
1.2
1

Ia (m )
Ia (m = 1)

0.8
0.6
1

0.8

0.6

0.4

0.2

Fig. 11 Calculated amplitude of phase currents.

TBC (c ) [dB ] = 20 log K p 1 + z

c

Selecting

K p = 5.91 10

fz = 2 Hz,
4

2

= TPL (c ) [ dB ] = 63.2 dB . (18)

it

follows

from

(18)

that

. Finally, from
z =

Ki
,
Kp

_
V bY = V b0 V Y0

(19)

VY0 =

V b0 + V c0
2

(20)

As shown by the phasor diagram in Fig. 12, when phase

a is disconnected, input voltages VbY and VcY, and,
consequently, input phase currents Ib = YVbY and Ic = YVcY
are equal with opposite signs and they are phase shifted by
30o versus the respective input source voltages Vb0 and Vc0. If
the total power is maintained before and after phase a is
disconnected, i.e.,
V I 3
V I 2
3
Ptot = 3 m m = 2 m m cos(30 o ) =
Vm I m2 , (21)
2
2
2

it is obtained that K i = 7 .42 10 3 .

III. ANALYSIS OF OPERATION FOR UNBALANCED SOURCE
VOLTAGES
The operation for unbalanced source voltages is analyzed
for the case when the amplitude of one phase voltage is
smaller than the amplitude of the other two phase voltages
i.e., for Va0 = mVm, m < 1, and Vb0 = Vc0 = Vm. The analysis
includes the power distribution between the three singlephase modules, the amplitude of the phase currents, and the
power factor of the modules.
The calculated power distribution between the three singlephase modules is shown in Fig. 10. The dashed lines present
the input power of the modules, PkY, k {a,b,c}, whereas, the
solid lines present the power delivered by the phase sources,
Pk0, k {a,b,c}. As can be seen in Fig. 10, the input power of
module a, whose source voltage is reduced, is provided by
its own source a, but also by sources b and c. For
example, for m = 0.5, module a consumes 20.5%, while
modules b and c each consume 39.7% of the total power.

it is finally obtained that

3
3
I m2 = 3 I m
= 1.732 I m
.

(22)

The calculated power factor of modules b and c when

the amplitude of phase voltage a decreases is shown in Fig.
13. It can be seen in Fig. 13 that the power factor of modules
b and c is greater than 0.99 for m > 0.55. The power
factor of module a does not decrease when the amplitude of
phase voltage a decreases as it can be concluded from Fig.
5.
IV. SIMULATION AND EXPERIMENTAL RESULTS
Simulink simulation results obtained for 230-Vrms source
phase voltages, 400-V output voltage of the PFC stages, and
6-kW output power are presented in Fig. 14. Figure 14
illustrates the operation with balancing control before and
after the amplitude of phase voltage a drops by 50%. It

42

v
aY
v
bY
v

0.99

cY

PFb,c 0.97
0.96
0.95
1

0.8

0.6

0.4

0.2

(a)

20
I
a
0
I
b
-20
I
c
|I | 20
aref
|I | 10
bref
|I | 0
cref
V
oa 450
400
V
V ob 350
oc 300
V
oref
VEA 10000
a
VEA 5000
VEAb
c
0
VEA

0.98

0.94

400
200
0
-200
-400

Fig. 13 Calculated power factor of single-phase modules.

should be noted in Fig. 14 that after the amplitude of phase

voltage a drops by 50%, it takes approximately 0.2 sec for
the new steady state to be established. It should also be
noted in Fig. 14 that in the new steady state, the adjustment
currents are IAdj,a -2A, and IAdj,b IAdj,c 1A. Before the drop
of the amplitude of phase voltage a, the load current of
each PFC stage was 2kW/400V=5A. Therefore, in the new
steady state, the adjusted load currents of the PFC stages are
ILoad,a,adj 5-2 = 3A and ILoad,b,adj ILoad,c,adj 5+1 = 6A, i.e.,
the output power of the PFC stages is adjusted as
PLoad,a,adj 1.2 kW and PLoad,b,adj PLoad,c,adj 2.4 kW, which
means that the output power of PFC stage a is reduced to
20% of the total output power, whereas, the output power of
each of the PFC stages b and c is increased to 40% of the
total output power. These results are in good agreement with
the analytical results for m = 0.5 presented in Fig. 10.
Simulation waveforms that illustrate the operation when
one phase is disconnected and then reconnected are
presented in Fig. 15. The waveforms in Fig. 15 are obtained
for 230-Vrms source phase voltages, 400-V output voltage
of the PFC stages, and 6-kW output power when all three
phases are connected, and at reduced output power of 76%
(determined by a maximum overcurrent of 32%, i.e.,
1.7320.76 = 1.32, for the single-phase modules) when one
phase is disconnected. It should be noted that when one
phase is disconnected, the reference voltage of the balancing
controllers is obtained as the averaged value of the output
voltages of the PFC voltage controllers of the two active
modules. In addition, when one phase is disconnected, the
balancing loop bandwidth is increased by increasing
balancing coefficient Kp five times. As can be seen in Fig.
15, in both cases (after disconnecting and after reconnecting
phase a), the new steady-state is established in
approximately 0.1 sec. The waveforms of the simulated
input voltages vkY and input currents ik, k{a,b,c}, are in good
agreement with the analytical results in Fig. 12.
Experimental results obtained on a 6-kW prototype at full
load are presented in Figs. 16(a)-(c). Figure 16(a) shows the
source phase voltages and input currents for balanced source
voltages Va0 =Vb0 =Vc0 = 230 Vrms. Figure 16(b) shows the
same waveforms when the RMS value of source voltage a
is decreased to Va0 = 180 Vrms, i.e., to 78%, whereas, Fig.
16(c) shows the waveforms when the RMS value of source
voltage a is further decreased to Va0 = 150 Vrms, i.e., to
65%. It should be noted in Figs. 16(a)-(c) that as the RMS

(b)

(c)

(d)

(e)

avg100

Y0

I
Adj,a
I
Adj,b
I
Adj,c

50
0
-50
-100

(f)

2
0
-2
0.1

0.15

0.2

(g)
t[sec]

0.25

0.3

0.35

0.4

0.45

Amplitude of phase a voltage drops by 50%

Fig. 14 Key simulated waveforms for 230Vrms source phase voltages and 6kW load before and after amplitude of phase a source voltage drops by
50%: (a) low-pass filtered input phase voltages with respect to Y point [V],
(b) input phase currents [A], (c) rectified input phase current references [A],
(d) PFC output voltages [V], (e) PFC voltage controller outputs [digital value
in Q12 format], (f) low-pass filtered neutral displacement voltage VY0 [V],
and (g) adjustment currents [A].

v
aY
v
bY
v
cY

I
a
I
b
I
c
|I |
aref
|I |
bref
|I |
cref
V
oa
V
V ob
Voc
oref
VEA
VEAa
VEAb
c
VEA

400
200
0
-200
-400
20
10
0
-10
-20

(a)

(b)

20
10
0

(c)

450
400
350
300

(d)

5,000
2,500
0

(e)

avg 200

100
0
-100
-200

I
Adj,a
I
Adj,b
I

1
0.5
0
-0.5
-1

Y0

Adj,c

(f)
(g)

20

Load,tot 15
10
0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

(h)
t[sec] Phase a reconnected
Phase a disconnected
Fig. 15 Key simulated waveforms for 230Vrms source phase voltages and 6kW load when phase a is disconnected and reconnected: (a) low-pass
filtered input phase voltages with respect to Y point [V], (b) input phase
currents [A], (c) rectified input phase current references [A], (d) PFC output
voltages [V], (e) PFC voltage controller outputs [digital value in Q12 format],
(f) low-pass filtered neutral displacement voltage VY0 [V], (g) adjustment
currents [A], and (h) total load current [A].

43

connected to a reduced source voltage draws less input

current and, therefore, it operates at reduced input power.
The desired distribution of the total power between the
single-phase modules is achieved by adjusting the reference
current of the current controllers in the dc-dc stages. The
adjustment currents are obtained at the outputs of the
balancing controllers, which balance the output voltages of
the PFC voltage controllers.
A detailed design procedure of the balancing controllers
performed through simulations in Simulink and SIMetrix is
provided.
The operation with unbalanced source voltages is analyzed
with respect to the power distribution between the three
single-phase modules, amplitude of the input phase currents,
and power factor of the modules. Operation and performance
of the balancing control when one phase voltage is reduced
and when one phase is disconnected and reconnected are
illustrated with Simulink simulations.
Experimental results obtained on a 6-kW prototype are also
provided.
REFERENCES

100V/div
5A/div
I [A]
a

I [A]
b

V [V]
a0

V [V]
b0

4ms/div
(a)
100V/div
5A/div
I [A]
a

I [A]
b

V [V]
a0
V [V]
b0

4ms/div
(b)
100V/div
5A/div

[1] M. Karlsson, C. Thoren, and T. Wolpert, A novel approach to

the design of three-phase AC/DC power converters with unity
power factor, Proc. International Telecommunications Energy
Conf. (INTELEC), paper 5-1, Jun. 1999.
[2] M. Karlsson, C. Thoren, and T. Wolpert, Practical
considerations concerning a novel 6kW three-phase AC/DC
power converter with unity power factor, Proc. International
Telecommunications Energy Conf. (INTELEC), pp. 28-33, Sep.
2000.
[3] M. Karlsson and T. Wolpert, Stable artificial neutral point in a
three phase network of single phase rectifiers, U.S. Patent
6,466,466, Oct. 15, 2002.
[4] D. Chapman, D. James, and C.J. Tuck, A high density 48V
200A rectifier with power factor correction An engineering
overview, Proc. International Telecommunications Energy
Conf. (INTELEC), pp. 118-125, Sep. 1993.
[5] C.J. Tuck, D.A. James, and D.A. Chapman, Power converter
with star configured modules, U.S. Patent 5,757,637, May 26,
1998.
[6] R. Greul, S.D. Round, and J.W. Kolar, Analysis and control of
a three-phase unity power factor Y-rectifier, IEEE Trans.
Power Electronics, vol. 22, no 5, pp. 1900-1911, Sep. 2007.
[7] R. Greul, U. Drofenik, and J.W. Kolar, Analysis and
comparative evaluation of a three-phase three-level unity power
factor Y-rectifier, Proc. International Telecommunications
Energy Conf. (INTELEC), pp. 421-428, Oct. 2003.
[8] R. Greul, U. Drofenik, and J.W. Kolar, A novel concept for
balancing of the phase modules of a three-phase unity power
factor Y-rectifier, Proc. Power Electronics Specialists Conf.
(PESC), pp. 3787-3793, Jun. 2004.
[9] R. Girod and D. Weida, High efficiency true 3-phase compact
switch-mode rectifier module for telecom power solutions,
Proc. International Telecommunications Energy Conf.
(INTELEC), pp. 658-663, Oct. 2013.
[10] M.L. Heldwein A.F. Souza, and I. Barbi, A simple control
strategy applied to three-phase rectifier units for
telecommunication applications using single-phase rectifier
modules, Proc. Power Electronics Specialists Conf. (PESC),
pp. 795-800, Jun. 1999.

I [A]
a

I [A]
b

V [V]
a0

V [V]
b0

4ms/div
(c)
Fig. 16 Experimental waveforms of source phase voltages and input
currents obtained on a 6-kW prototype at full load with: (a) balanced source
voltages Va0 = Vb0 = Vc0 = 230 Vrms, (b) unbalanced source voltages
Va0 = 180 Vrms, Vb0 = Vc0 = 230 Vrms, and (c) unbalanced source voltages
Va0 = 150 Vrms, Vb0 = Vc0 = 230 Vrms.

value of source voltage Va0 decreases to 78% and to 65%, the

amplitude of the input current of phase a is almost constant,
whereas, the amplitude of input current of phase b
increases by approximately 10% and 18%, respectively,
which is in good agreement with the analytical results
presented in Fig. 11.
V. SUMMARY
In this paper, analysis of the balancing control method for
three single-phase isolated ac-dc converter modules
employed to implement an isolated three-phase, three-wire
ac-dc converter, introduced in [9], is presented. The
balancing control between the three single-phase modules is
achieved by equalizing the input admittances of the PFC front
stages, which operate with average current control. It is
shown that for equal input admittances, the outputs of the
voltage controllers as well as the voltage feedforward terms
in the PFC control circuit should be equal.
With equal input admittances, for balanced source
voltages, the total input power is equally distributed between
the three single-phase modules. However, for unbalanced
source voltages, to achieve equal input admittances, a module

44

[11] T. Atsushi, Y. Itsuo, and O. Tsuyoshi, The control method of

3-phase PWM converter for 3-phase 3-wired imbalanced ac
voltages, Proc. International Telecommunications Energy
Conf. (INTELEC), pp. 1-8, Oct. 2011.

[12] J. Biela, U. Drofenik, F. Krenn, J. Miniboeck, and J.W. Kolar,

Three-phase Y-rectifier cyclic 2 out of 3 dc output voltage
balancing control method, IEEE Trans. Power Electronics,
vol. 24, no 1, pp. 34-44, Jan. 2009.

45