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Timing Constraints
Timing analysis in the Quartus II software with the
TimeQuest Timing Analyzer relies on constraining
your design to make it meet your timing
requirements
When discussing these constraints, they can be referred
to as timing constraints, SDC constraints, or SDC
commands interchangeably
set_clock_groups
create_clock
The first statements in a SDC file should be
constraints for clocks, for example, constrain the
external clocks coming into the FPGA with
create_clock
An example of the basic syntax is:
create_clock -name sys_clk -period 8.0 [get_ports fpga_clk]
derive_pll_clocks
After the create_clock commands add the following
command into your SDC file:
derive_pll_clocks
This command automatically creates a generated
clock constraint on each output of the PLLs (Phase
Locked Loop) in your design.
When PLLs are created, you define how each PLL
output is configured
Because of this, the TimeQuest analyzer can
automatically constrain them, with the derive_pll_clocks
command
Electrical & Computer Engineering
derive_clock_uncertainty
Add the following command to your SDC file:
derive_clock_uncertainty
This command calculates clock-to-clock
uncertainties within the FPGA, due to
characteristics like PLL jitter, clock tree jitter, etc.
This should be in all SDC files
The TimeQuest analyzer generates a warning if this
command is not found in your SDC files
Output Constraints
Output constraints allow you to specify all external delays
from the device for all output ports in your design
Input Constraints
Output Constraints
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Constraints->Create Clock
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