1

APPENDICES

moduleradix_2_5_top(clk,rst,enable,fft_in1,fft_in2,fft_in3,fft_in4,fft_in5,fft_in6,fft_in7,f
ft_in8,fft_in9,fft_in10,fft_in11,fft_in12,fft_in13,fft_in14,fft_in15,fft_in16,fft_in1,fft_out
1,fft_out2,fft_out3,fft_out4,fft_out5,fft_out6,fft_out7,fft_out8,fft_out9,fft_out10,fft_out1
1,fft_out12,fft_out13,fft_out14,fft_out15,fft_out16);
inputclk;
inputrst;
input enable;
input signed [31:0] fft_in1;
input signed [31:0] fft_in2;
input signed [31:0] fft_in3;
input signed [31:0] fft_in4;
input signed [31:0] fft_in5;
input signed [31:0] fft_in6;
input signed [31:0] fft_in7;
input signed [31:0] fft_in8;
input signed [31:0] fft_in9;
input signed [31:0] fft_in10;
input signed [31:0] fft_in11;
input signed [31:0] fft_in12;

input signed [31:0] fft_in13;

input signed [31:0] fft_in14;
input signed [31:0] fft_in15;
input signed [31:0] fft_in16;
outputreg signed [31:0] fft_out1
output reg signed [31:0] fft_out2;
outputreg signed [31:0] fft_out3;
outputreg signed [31:0] fft_out4;
outputreg signed [31:0] fft_out5;
outputreg signed [31:0] fft_out6;
outputreg signed [31:0] fft_out7;
outputreg signed [31:0] fft_out8;
outputreg signed [31:0] fft_out9;
outputreg signed [31:0] fft_out10;
outputreg signed [31:0] fft_out11;
outputreg signed [31:0] fft_out12;
outputreg signed [31:0] fft_out13;
outputreg signed [31:0] fft_out14;
outputreg signed [31:0] fft_out15;
outputreg signed [31:0] fft_out16;

wire signed [31:0]but_1_out1;

wire signed [31:0]but_1_out2;
wire signed [31:0]but_1_out3;
wire signed [31:0]but_1_out4;
wire signed [31:0]but_1_out5;
wire signed [31:0]but_1_out6;
wire signed [31:0]but_1_out7;
wire signed [31:0]but_1_out8;
wire signed [31:0]but_1_out9;
wire signed [31:0]but_1_out10;
wire signed [31:0]but_1_out11;
wire signed [31:0]but_1_out12;
wire signed [31:0]but_1_out13;
wire signed [31:0]but_1_out14;
wire signed [31:0]but_1_out15;
wire signed [31:0]but_1_out16;

wire signed [31:0]but_2_out1;

wire signed [31:0]but_2_out2;
wire signed [31:0]but_2_out3;

wire signed [31:0]but_2_out4;

wire signed [31:0]but_2_out5;
wire signed [31:0]but_2_out6;
wire signed [31:0]but_2_out7;
wire signed [31:0]but_2_out8;
wire signed [31:0]but_2_out9;
wire signed [31:0]but_2_out10;
wire signed [31:0]but_2_out11;
wire signed [31:0]but_2_out12;
wire signed [31:0]but_2_out13;
wire signed [31:0]but_2_out14;
wire signed [31:0]but_2_out15;
wire signed [31:0]but_2_out16;
integeri;
wire signed [31:0]but_3_out1;
wire signed [31:0]but_3_out2;
wire signed [31:0]but_3_out3;
wire signed [31:0]but_3_out4;
wire signed [31:0]but_3_out5;
wire signed [31:0]but_3_out6;

wire signed [31:0]but_3_out7;

wire signed [31:0]but_3_out8;
wire signed [31:0]but_3_out9;
wire signed [31:0]but_3_out10;
wire signed [31:0]but_3_out11;
wire signed [31:0]but_3_out12;
wire signed [31:0]but_3_out13;
wire signed [31:0]but_3_out14;
wire signed [31:0]but_3_out15;
wire signed [31:0]but_3_out16;
wire signed [31:0]but_4_out1;
wire signed [31:0]but_4_out2;
wire signed [31:0]but_4_out3;
wire signed [31:0]but_4_out4;
wire signed [31:0]but_4_out5;
wire signed [31:0]but_4_out6;
wire signed [31:0]but_4_out7;
wire signed [31:0]but_4_out8;
wire signed [31:0]but_4_out9;
wire signed [31:0]but_4_out10;

wire signed [31:0]but_4_out11;

wire signed [31:0]but_4_out12;
wire signed [31:0]but_4_out13;
wire signed [31:0]but_4_out14;

wire signed [31:0]but_4_out15;

wire signed [31:0]but_4_out16;

radix_2_5_BUTTERFLY_1 STAGE1(
.clk(clk),
.rst(rst),
.in1_reg(fft_in1),
.in2_reg(fft_in2),
.in3_reg(fft_in3),
.in4_reg(fft_in4),
.in5_reg(fft_in5),
.in6_reg(fft_in6),
.in7_reg(fft_in7),
.in8_reg(fft_in8),
.in9_reg(fft_in9),

.in10_reg(fft_in10),
.in11_reg(fft_in11),
.in12_reg(fft_in12),
.in13_reg(fft_in13),
.in14_reg(fft_in14),
.in15_reg(fft_in15),
.in16_reg(fft_in16),
.stage_1_out1(but_1_out1),
.stage_1_out2(but_1_out2),

.stage_1_out3(but_1_out3),
.stage_1_out4(but_1_out4),
.stage_1_out5(but_1_out5),

.stage_1_out6(but_1_out6),
.stage_1_out7(but_1_out7),
.stage_1_out8(but_1_out8),

.stage_1_out9(but_1_out9),

.stage_1_out10(but_1_out10),

.stage_1_out11(but_1_out11),

.stage_1_out12(but_1_out12),

.stage_1_out13(but_1_out13),

.stage_1_out14(but_1_out14),

.stage_1_out15(but_1_out15),

.stage_1_out16(but_1_out16)
);
radix_2_5_BUTTERFLY_2 STAGE2(
.clk(clk),
.rst(rst),
.in1_reg(but_1_out1),

.in2_reg(but_1_out2),
.in3_reg(but_1_out3),
.in4_reg(but_1_out4),
.in5_reg(but_1_out5),
.in6_reg(but_1_out6),
.in7_reg(but_1_out7),
.in8_reg(but_1_out8),
.in9_reg(but_1_out9),
.in10_reg(but_1_out10),
.in11_reg(but_1_out11),

.in12_reg(but_1_out12),
.in13_reg(but_1_out13),
.in14_reg(but_1_out14),
.in15_reg(but_1_out15),
.in16_reg(but_1_out16),

.stage_2_out1(but_2_out1),
.stage_2_out2(but_2_out2),

10

.stage_2_out3(but_2_out3),
.stage_2_out4(but_2_out4),
.stage_2_out5(but_2_out5),
.stage_2_out6(but_2_out6),
.stage_2_out7(but_2_out7),
.stage_2_out8(but_2_out8),
.stage_2_out9(but_2_out9),

.stage_2_out10(but_2_out10),

.stage_2_out11(but_2_out11),

.stage_2_out12(but_2_out12),

.stage_2_out13(but_2_out13),

.stage_2_out14(but_2_out14),

.stage_2_out15(but_2_out15),

.stage_2_out16(but_2_out16)

11

);
radix_2_5_BUTTERFLY_3 STAGE3(
.clk(clk),
.rst(rst),
.in1_reg(but_2_out1),

.in2_reg(but_2_out2),
.in3_reg(but_2_out3),
.in4_reg(but_2_out4),
.in5_reg(but_2_out5),
.in6_reg(but_2_out6),
.in7_reg(but_2_out7),
.in8_reg(but_2_out8),
.in9_reg(but_2_out9),
.in10_reg(but_2_out10),
.in11_reg(but_2_out11),
.in12_reg(but_2_out12),
.in13_reg(but_2_out13),
.in14_reg(but_2_out14),

12

.in15_reg(but_2_out15),

.in16_reg(but_2_out16),
.stage_3_out1(but_3_out1),
.stage_3_out2(but_3_out2),
.stage_3_out3(but_3_out3),
.stage_3_out4(but_3_out4),
.stage_3_out5(but_3_out5),
.stage_3_out6(but_3_out6),
.stage_3_out7(but_3_out7),
.stage_3_out8(but_3_out8),
.stage_3_out9(but_3_out9),

.stage_3_out10(but_3_out10),

.stage_3_out11(but_3_out11),

stage_3_out12(but_3_out12),

.stage_3_out13(but_3_out13),

13

.stage_3_out14(but_3_out14),

.stage_3_out15(but_3_out15),

.stage_3_out16(but_3_out16)
);

radix_2_5_BUTTERFLY_4 STAGE4(
.clk(clk),
.rst(rst),
.in1_reg(but_3_out1),
.in2_reg(but_3_out2),
.in3_reg(but_3_out3),
.in4_reg(but_3_out4),
.in5_reg(but_3_out5),
.in6_reg(but_3_out6),
.in7_reg(but_3_out7),
.in8_reg(but_3_out8),
.in9_reg(but_3_out9),
.in10_reg(but_3_out10),

14

.in11_reg(but_3_out11),
.in12_reg(but_3_out12),
.in13_reg(but_3_out13),
.in14_reg(but_3_out14),
.in15_reg(but_3_out15),
.in16_reg(but_3_out16),
.stage_4_out1(but_4_out1),
.stage_4_out2(but_4_out2),
.stage_4_out3(but_4_out3),
.stage_4_out4(but_4_out4),
.stage_4_out5(but_4_out5),
.stage_4_out6(but_4_out6),
.stage_4_out7(but_4_out7),
.stage_4_out8(but_4_out8),
.stage_4_out9(but_4_out9),

.stage_4_out10(but_4_out10),
.stage_4_out11(but_4_out11),
.stage_4_out12(but_4_out12),
.stage_4_out13(but_4_out13),
.stage_4_out14(but_4_out14),

15

.stage_4_out15(but_4_out15),
.stage_4_out16(but_4_out16)
);
always @(posedgeclk)
begin
if (rst)
begin
fft_out1<=0;
fft_out2<=0;
fft_out3<=0;
fft_out4<=0;
fft_out5<=0;
fft_out6<=0;

fft_out7<=0;
fft_out8<=0;
fft_out9<=0;
fft_out10<=0;
fft_out11<=0;
fft_out12<=0;

16

fft_out13<=0;
fft_out14<=0;
fft_out15<=0;
fft_out16<=0;
end
else
begin fft_out1<=but_4_out1;

fft_out2<=but_4_out2;
fft_out3<=but_4_out3;
fft_out4<=but_4_out4;
fft_out5<=but_4_out5;
fft_out6<=but_4_out6;
fft_out7<=but_4_out7;
fft_out8<=but_4_out8;
fft_out9 <=but_4_out9;
fft_out10<=but_4_out10;
fft_out11<=but_4_out11;
fft_out12<=but_4_out12;

17

fft_out13<=but_4_out13;
fft_out14<=but_4_out14;
fft_out15<=but_4_out15;
fft_out16<=but_4_out16;
end
end
endmodule