Documenti di Didattica
Documenti di Professioni
Documenti di Cultura
Journal of Semiconductors
February 2013
A fast novel soft-start circuit for peak current-mode DCDC buck converters
Li Jie(), Yang Miao() , Sun Weifeng(), Lu Xiaoxia(),
Xu Shen(), and Lu Shengli()
National ASIC System Engineering Research Center, Southeast University, Nanjing 210096, China
Abstract: A fully integrated soft-start circuit for DCDC buck converters is presented. The proposed high speed
soft-start circuit is made of two sections: an overshoot suppression circuit and an inrush current suppression circuit.
The overshoot suppression circuit is presented to control the input of the error amplifier to make output voltage
limit increase in steps without using an external capacitor. A variable clock signal is adopted in the inrush current
suppression circuit to increase the duty cycle of the system and suppress the inrush current. The DCDC converter
with the proposed soft-start circuit has been fabricated with a standard 0.13 m CMOS process. Experimental
results show that the proposed high speed soft-start circuit has achieved less than 50 s start-up time. The inductor
current and the output voltage increase smoothly over the whole load range.
Key words: current-mode; DCDC converter; soft-start; inrush current; overshoot voltage
DOI: 10.1088/1674-4926/34/2/025006
EEACC: 2570
1. Introduction
In recent years, switching power supplies have been
widely applied in portable electronic systems market due to
their high efficiency, stability, and dynamic characteristics1 .
A typical block diagram of a current-mode DCDC buck converter is depicted in Fig. 1. It works in a control loop converting
the error signal into a variable duty cycle of the driving signal
for the switching element. The problem is that at the beginning
of the start-up transient the error amplifier (EA) is unbalanced,
thus causing the converter to work at 100% duty cycle. This
situation makes the inductor current rise above its equilibrium
value, and produces an inrush current. And it will remain above
its equilibrium value for a little time because the inductor current cannot change instantaneously. This can induce the output
voltage to rise abruptly to exceed its regulated value2 . The
electronic system may be damaged at the start-up period by
the inrush current and overshoot voltage. Therefore a soft-start
circuit is normally adopted to eliminate the inrush current and
reduce the overshoot voltage.
The most conventional method is using an external capacitor named Csoft to make the output voltage rise slowly3 5 .
The output of the EA or the reference voltage Vset rises gradually when Csoft is charged linearly. The soft-start time of the
converter depends on the charge current and the value of Csoft .
The method has an explicit principle and can be used effortlessly, but the capacitor is usually too large to be integrated
on chip. Another method to limit the output voltage is the
clock-based soft-start circuit, which can precisely control the
start-up time6 . These two methods are both devised to control the output voltage. In addition, the method of suppressing
the inrush current is to detect the current of the inductor and
compare the current with a constant current value. Considering that the limited current is usually higher than the maximal
* Project supported by the Natural Science Foundation of Jiangsu, China (No. BK2011059), the Program for New Century Excellent Talents
in University (NCET-10-0331), and the Qing Lan Project.
Corresponding author. Email: myron@seu.edu.cn
Received 21 June 2012, revised manuscript received 11 September 2012
2013 Chinese Institute of Electronics
025006-1
Li Jie et al.
output voltage of the D/A. So the output of the D/A will remain
in the voltage of Va . This structure ensures that the D/A output
slowly increases to a stable voltage.
The soft-start time is determined by the clock which controls the D/A. The fastest start-time of the system is when the
system works using maximum duty cycle up to a limited current. And the start-up includes two phases. If the inrush current
is not considered, the system will work using a maximum duty
cycle up to limited current Ilimited and then work using Ilimited
until the output voltage reaches stable value. The work state is
shown in Fig. 3. Therefore the fastest time can be calculated by
the two sections as follows.
(1) The system works using a maximum duty cycle up to
limited current
The time is t1 when the system works using a maximum
duty cycle up to a limited current, as shown in Fig. 3. As the
increment of output voltage is very small, zero is assumed to
represent the output voltage. Then the time t1 can be expressed
025006-2
Li Jie et al.
Ilimited L
:
Vin
(2)
(2) The system works using limited current until the output
voltage reaches stability
As shown in Fig. 3 the time is t2 when the system works
using limited current until output voltage reaches a limited current. The inductor current keeps a stable value. The load and
the capacity are both charged. Therefore the charge process can
be expressed as follows:
ILoad D
IC D IL
IC D C
Vo
;
RL
(3)
ILoad ;
(4)
dVo
:
dt
(5)
(7)
It is obvious that it takes a longer time at a heavy load condition compared with a light condition. In the proposed circuit,
the rise time of Vset is designed slightly longer than trise to get
the balance of suppression of the overshoot of Vo and the softstart time.
As mentioned above, the 6-bits D/A will supply rising voltage slowly to the gate of transistor M1 in Fig. 2. However, the
gate voltage of transistor M2, which is larger than the gate voltage of M1, has been fixed on Vref , so at the initial phase of softstart, transistor M2 is cut off. And the drain current of M1, M2,
M3 will always meet
IM1 C IM2 D IM3 :
(8)
Because of the virtual short characteristics of the operational amplifier, the gate voltage of transistor M3 will increase
with the rising of transistor M1. Moreover, IM1 will decrease
while IM2 increases at this phase to keep the balance of current.
When the gate voltage of transistor M1 rises to a certain value,
transistor M1 will be cut off. At this moment, IM2 D IM3 . The
soft start-up of the setting voltage is completed successfully.
Therefore the Vo will rise following the setting voltage Vset and
avoid the overshoot voltage. And the voltage Vset is set by the
resistance network.
2.2. Inrush current suppression circuit
In order to prevent the power MOSFET from thoroughly
closing and suppress the noise influencing the stability of the
converter between opening and closing the MOSFET, a clock
025006-3
Li Jie et al.
cle is adopted in the initial phase, and then the discharge current
will be larger than that in CLK1. When Vo is larger than Vref1 ,
the system switches to CLK1. As shown in Fig. 4(b), several
clock cycles in CLK1 will be shielded to compose CLK2 and
the cycle of CLK2 is three times as much as the cycle of CLK1.
At the initial phase, the time the system spends rising to the limited value is the same. Then the discharge time of inductor is
longer and the charge time is shorter when the converter works
in CLK2. It is obvious that the inductor current will rise slower
and decrease larger when the converter works in CLK2. The
charge current is smaller than the discharge current, so the inrush current can easily be suppressed. When the voltage Vo is
larger than Vref1 , the system automatically switches to CLK1.
The key of this circuit is to set the voltage Vref1 . The voltage
Vref1 is set complying with the following principles.
(1) When the circuit switches to CLK1, the charge current
must be equal to or smaller than the discharge current. Otherwise, the circuit will generate inrush current after it switches
to CLK1, and the inrush current suppression circuit will lose
its function. (2) The inductor current must be smaller than the
limited current when the circuit switches to the CLK1, so it can
guarantee that the circuit has not generated inrush current.
The above principles can be expressed by the following
formulas:
Vin
Ik D Ik
Vref1
Vref1
Dmin1 T1 6
.1 Dmin1 / T1 ;
L
L
Z mT
Vin Vo .t/
I1 D
t.k D 1/;
L
0
mT C.k 2/T2
mT C.k 1/T2
Vin
(9)
(10)
Fig. 6. Simulated results of start-up Vset , Vout , IL and CLK (a) with
constant minimum duty cycle and (b) with variable minimum duty
cycle.
Vo .t/
t
L
Vo .t/
t 6 Ilimited .k D 2n/:
L
(11)
025006-4
Li Jie et al.
rent suppression circuit. The overshoot suppression circuit generates a linear ramp voltage which can effectively suppress the
overshoot of the output voltage. The inrush current suppression circuit with a variable minimum duty cycle can suppress
the inrush circuit effectively. The simulation results show that
the proposed high speed soft-start circuit implemented to the
current-mode DCDC converter is well consistent with the theory. Using a standard 0.13 m CMOS process, the test chip has
been fabricated and experimental results are presented to the
theoretical analysis. The test result shows that this technology
can achieve a very fast start-up time of about 43.5 s. Furthermore, because the proposed soft-start circuit is designed with
a CMOS process, it is convenient to be transplanted to other
converters.
References
4. Conclusion
This paper presented a fast integrated soft-start circuit consisting of an overshoot suppression circuit and an inrush cur-
[1] Lai Xinquan, Jia Ligang, Hu Juncai, et al. The design of a low
voltage and high speed driver circuit for boost DCDC converter.
5th International Conference on ASIC Proceeding, 2003, 1(10):
635
[2] Lai Xinquan, Guo Jianping, Yu Weixue. A novel digital soft-start
circuit for DCDC switching regulator. 6th International Conference on ASIC Proceeding, 2005, 2(10): 564
[3] Yuan Bing, Lai Xinquan, Ye Qiang, et al. A novel compact softstart circuit with internal circuitry for DCDC converter. 7th International Conference on ASIC Proceeding, 2007: 450
[4] Chen K H, Chang C T, Liu T H. Bidirectional current-mode capacitor multipliers for on-chip compensation. IEEE Trans Power
Electron, 2008, 23(1): 180
[5] Wang Y, Xu D, Guo D, et al. The new soft starting methods for
electronics ballasts of UV lamps based on microcontroller. IEEE
Conference on Industrial Electronics and Applications, 2006: 1
[6] Ryu Y C, Hwang Y W. A new soft-start method with abnormal
over current protection function for switching power supplies.
IEEE International Conference on Electric Machines and Drives,
2005: 431
[7] Li Sizhen, Zou Xuecheng, Chen Xiaofei. Designing a compact
soft-start scheme for voltage-mode DCDC switching converter.
Microelectron J, 2010, 41(7): 430
[8] Lee K C, Chae C S, Cho G H, et al. A PLL-based high-stability
single-inductor 6-channel output DCDC buck converter. IEEE
International ISSCC, 2010: 200
[9] Barrado A, Quintero J, Lazaro A, et al. Linear-non-linear control
applied in multiphase VRM. IEEE Power Electronics Specialists
Conference, 2005: 904
[10] Shibata K, Pham C K. A DCDC converter using a high speed
soft-start control circuit. IEEE International Symposium on Circuits and Systems, 2010: 833
025006-5