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An Efficient VLSI Architecture of a Reconfigurable PulseShaping FIR Interpolation Filter for Multi standard DUC
Abstract
This brief proposes a two-step optimization technique for designing a reconfigurable
VLSI architecture of an interpolation filter for multi standard digital up converter (DUC) to
reduce the power and area consumption. The proposed technique initially reduces the number of
multiplications per input sample and additions per input sample by 83% in comparison with
individual implementation of each standards filter while designing a root-raised-cosine finiteimpulse response filter for multi standard DUC for three different standards. In the next step, a 2bit binary common sub expression (BCS)-based BCS elimination algorithm has been proposed to
design an efficient constant multiplier, which is the basic element of any filter. This technique
has succeeded in reducing the area and power usage by 41% and 38%, respectively, along with
36% improvement in operating frequency over a 3-bit BCS-based technique reported earlier, and
can be considered more appropriate for designing the multi standard DUC.

Index TermsDigital up converter (DUC), finite-impulse response (FIR) interpolation filter,

reconfigurable hardware architecture, software defined radio (SDR) system.

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Existing Method:
Requirement of various high data transfer rates and high channel capacities by different
operating modes of the present day cell phones motivated the telecommunication industry to
spawn the concept of software defined radio (SDR). SDR refers to a single device that is capable
of supporting all the present as well as emerging standards available under the wireless
communication category. In an SDR system, multiple standards can be realized in a single chip
by providing a programmable channel select filter at the baseband level. Different standards have
different channel bandwidths, sampling rates, carrier-to-noise ratios, blocking, and interference
profiles. This makes the development of a reconfigurable sample rate converter chip to be a
major challenge faced by the telecommunication industry of today. a combination of
symmetrical retimed direct form architecture, balanced modular architecture, separated signed
processing architecture, and modified canonical signed digit (CSD) technique-based finiteimpulse response (FIR) filter to improve the power consumption. However, the reduction in
power has been achieved by compromising with the speed of operation that makes this design
unsuitable for the SDR system. A multiplier-less FIR interpolator with smaller area usage has
been proposed in [5]. Efficient use of lookup tables (LUTs) in this design helps to reduce the
power and area while compared with the conventional FIR filter implementation. In case of
higher order filter implementation , this architecture fails to achieve low power because of an
increase in the ROM size.

Softroniics
Calicut||Coimbatore||Palakkad

www.softroniics.in
9037291113, 9037061113

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Proposed Method:
To overcome the disadvantages of the existing reconfigurable architectures for FIR filter
mentioned above, a new reconfigurable architecture has been proposed in this brief for initial
reduction of multiplications per input sample (MPIS) and additions per input sample (APIS) and
subsequent reduction of hardware and power by designing an efficient constant multiplier using
2-bit binary The organization of this brief is as follows. The problem regarding the realization of
a reconfigurable FIR interpolation filter in hardware and the proposed method for its solution
have been explained and describe the architectural details of the proposed reconfigurable FIR
filter architecture for multi standard DUC. Implementation results and discussion common sub
expression (BCS).

Front End

: Modelsim 6.3 for Debugging and Xilinx 14.3 for

Synthesis and Hard Ware Implementation

This softwares where Verilog source code can be used for design
implementation.

Softroniics
Calicut||Coimbatore||Palakkad

www.softroniics.in
9037291113, 9037061113