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Sampling theory
Fig. shown below illustrates the sampled signal in time and frequency
domain.
Types of Sampling
Nyquist rate Sampling: Sampling at twice the signal frequency
Down sampling
Up sampling
Over Sampling
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- negative DNL implies that the code is Shorter than the ideal
code width
- DNL is measured in the increasing code direction of the transfer
curve.
- The transition of code N is compared to that of code N+1.
- For DAC, DNL error of -1LSB implies that the output did not
increase for increasing input code.
-
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- For DAC, DNL error of greater than -1LSB implies that the
device is non-monotonic.
- For an ADC,DNL error of greater than -1LSB implies that at
least one code is missing, meaning that there is no analog
voltage which will generate a particular code.
- Manufactures includeNo missing Codesspec.
Gain and Offset error
- Gain error has a non ideal slope.
- Ideally, in the graphs above, as the analog input increases at a
certain rate, the output codes would also increase at the same
rate.
- If the output codes increase at a different rate than the analog
input does, then it results in gain error.
Gain error can be defined as the difference between the level that
produces the greatest code and the smallest code, versus the ideal
levels that produce these codes
In an ideal situation, data converter would begin to notice deviations
from true zero voltage.
However, because of offset error, a small constant analog voltage is
always present before the conversion begins to function linearly.
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Dynamic Characteristics
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Thermometer code
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I LSB = Vref/2N
For 3-bit DAC 1 LSB= 5/8 V = 0.625V
MSB causes the output to change by Vref.
Ex- Find the resolution of DAC if the output voltage is desired to
change in 1mV, Vref is 5V.
Solution : DAC must resolve
1mV/5V = 0.0002 =.02%
Accuracy required = 1/2N =0.0002
N=Log (5V/1mV)= 12.29 = 13 bits
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DAC-Nonlinearity
Differential Nonlinearity:
Ideal increments as per the ideal curve= 0.625V=1LSB
Nonideal components cause the analog increments to differ
from ideal values.The difference between actual and idealdifferential nonlinearity is
DNLn
= Actual increment height of transition n Ideal
increment height
N-number corresponding to digital input transition.
Differential Nonlinearity:Example
n=3, Vref=5V
1LSB=1/8 of Vout/Vref
DNL 1=DNL 2=DNL 7=0
DNL 3=1.5 LSB-1 LSB =0.5 LSB=0.3125V
DNL 4=0.5 LSB-1 LSB =-0.5 LSB
DNL 5=0.25 LSB-1 LSB =-0.75 LSB
DNL 6=1.75 LSB-1 LSB =0.75 LSB
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Differential Nonlinearity:Example
Plot DNL in LSB versus input digital code.
DNL for the converter is 0.75LSB since the overall error of DAC is
defined by its worst-case DNL.
Generally, DAC will have 1/2 LSB of DNL ,if it is to be n-bit
accurate.
Differential Nonlinearity:Example
5-bit DAC with .75LSBs of DNL has resolution of 4-bit DAC.
If the DNL for DAC is less than -1LSBs, then DAC is said to be
nonmonotonic.
DAC-should exhibit monotonicity if it is to function witout error.
The DNL specification measures how well a DAC can generate
uniform analog LSB multiples at its output.
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Integral Nonlinearity:
Another important Static characteristic of DAC.
Difference between the data converter output values and a
reference straight line drawn through the first and last output
values.
INL defines the linearity of overall transfer curve as
INL n = Output value for input code n output value of the
reference line at that point.
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Integral Nonlinearity:
Converter with N-bit resolution will have less than 1/2 LSB of DNL or
INL.
For ex- 13 bit DAC having greater than 1/2 LSB of DNL or INL
actually has the resolution of 12bit DAC.
0.5LSB = Vref/2 N+1
Integral Nonlinearity:Ex
3-bit DAC, Vref=5V
Integral Nonlinearity:
INL2 = INL4 = INL6= INL7=0
INL1 = INL3 = 0.5LSB
INL5 = -0.75LSB
INL for the DAC is considered to be its wirst case INL of +0.5 LSB
and -0.75 LSB.
Another method: Best-fit-minimize INL
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Offset ERROR:
Analog output should be 0V for D=0
However, an offset exists.-seen as shift in the transfer curve.
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Gain ERROR:
Gain error exists if the slope of the best-fit line through the transfer
curve is different from the slope of the best-fit line for the ideal case.
Gain error=Ideal slope-Actual slope.
Latency:
Total time from the moment that the input digital word changes to the
analog output value has settled to within a specified tolerance.
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in
both
static(hold
mode)
and
Sample Mode
.Acquisition time: Time required for the S/H to track the analog
signal to within a specified tolerance, once the sampling
command has been issued.
Worst case acquisition time would correspond to the time
required for the output to transition from 0 to Vin(max).
S/H circuits use amplifiers as buffers.
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Sample Mode
.Acquisition time:
Output of T/H is limited by the amplifiers slew rate.
If the amplifier is not compensated correctly, and the phase
margin is too small, then a large overshoot occur which
requires a longer settling time.
Error tolerance at the output of S/H dependent on amplifierss
offset, gain error and linearity.
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Hold Mode
1.Pedestal error: occurs as result of charge injection and clock
feedthrough.
Part of the charge built up in the channel of the switch is
distributed onto the capacitor,slightly changing its voltage.
Clock couples onto the capacitor via overlap capacitance
between the gate and the source or drain.
Droop error:
related to leakage of current from the capacitor due to parasitic
impedances and to the leakage through reverse biased diode formed
by drain of the switch.
Leakage current: compensated by making drain area small.
Minimize droop: increase the value of the capacitor.
Tradeoff,however increase time required to charge the capacitor to
the value of the input signal.
Aperture Error
Transient effect that introduces error occurs between the sample and
hold modes.
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Aperture Error
Related to the frequency of the signal and the worst case aperture
error occurs at the zero crossing, where dV/dt is the greatest.
This assumes that the S/H circuit is capable of sampling both positive
and negative voltages.
The amount of error that can be tolerated is directly related to the
resolution of the conversion.
Example:
Given Vin= A sin 2*pi*f*t A=2V f=100KHz
Aperture uncertainity is 0.5ns.
Find the sampling error
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Quantization Error:
Qe =Vin V staircase
V staicase =D. Vref/2N
= D. VLSB
VLSB is value of 1 LSB in volts.
Qe-expressed in terms of LSBs.
Qe-generated by subtracting the value of the staircase from the
dashed line.
Quantization Error:
Sawtooth waveform is centered about LSB.
Ideally magnitude of Qe will be between 0 and 1 LSB.
If Qe is centered about zero so that error would be 1/2 LSB.
Here entire curve is shifted to left by LSB.
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Quantization Error:
First code transition occurs when Vin/Vref 1/16. .(between 0 and
1/8)
Therefore the range of Vin/Vref for the digital output corresponding to
000 is half as wide as the ideal step.
Last transition occurs when Vin/Vref 13/16.(between 6/8 and 7/8)
DNL:
Similar to that of DAC.
DNL is the difference the actual code width of a nonideal converter
and the ideal case.
DNL=Actual step width-Ideal step width.
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Since the step widths can be converted to either volts for LSBs, DNL
can be defined in either units.
DNL:
Ideal step width=1/8
Videalstepwidth=1/8 Vref= 0.625V=1LSB
Example: 3-bit ADC, Vref=5V, find Qe in units of LSBs.
DNL0=DNL4 =DNL5=0
DNL2 = 1.5 LSB-1LSB = 0.5LSB
DNL3= 0.5 LSB-1LSB = -0.5LSB
DNL5 = -0.5LSB
DNL6 = -0.5LSB
Overall DNL for the curve is 0.5LSB
As DNL increases in either direction, Qe worsens.
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DNL:
ADC with -1LSB DNL is guarnteed to have a missing code.
DNL5 = -1LSB- missing code.
ADC with -1LSB DNL is not guarnteed to have a missing code
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Aliasing.
Dynamic aspects of converter.
Falias = Factual - Fsample
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Guard rings
Fully differential/Matching design
Power supply and Grounding Issues
Floorplanning
Types of DAC
Resistor String
R-2R ladder Network
Current Steering
Charge scaling DAC
Cyclic DAC
Pipeline DAC
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Problem
3bit resistor string DAC using binary switches, VrefV, PD=
5mW, Compute the analog output for each input digital data.
Imax= 5mW/5V =1mA
R= 1/8 * 5V/1mA = 625 ohms.
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Ri
= 0
i=1
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Vi =
k =1
Rk
Vref
R + Rk
k =1
Rk
Vref
k =1
Vref i
Vi =
Vi = Vi, ideal +
Vref
Vref
Rk
k =1
Rk
k =1 R
INL
Vref
Rk
/ R
k =1
INL =
Vref
Rk
k =1
/R
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INL =
Vref 2
N 1
Rk
/R
k =1
Vi Vi 1 =
(i )Vref
Vactual =
Vref
Vref
1 +
Rk
R
k =1
Ri
DNL=Vactual Videal
= Vref/2N* Ri/R
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Ex: let R = 2%
DNL max= .02R/R * Vref/2N = .02LSB
DNL max 1/2 LSB
R-2R Ladder Network
Fewer resistors
Starting at the right end of network, resistance looking to right
of any node to groun is 2R.
Vout= -itot*Rf
N 1
itot =
Dk
k =0
Vref
1
2R
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Problem
3-bit DAC R=1k, Rf = 2k, Vref=5V
Switch resistances negligible.
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Integral Nonlinearity
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Current Steering
Uses current throughout conversion.
Requires precision current source.
Set of current sources
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