1 EE287: CMOS ASIC

Morris Jones
Office Hours:
TW 5 pm-6pm
EE Department SJSU
EM: morris.sjsu@comcast.net
HP: http://www.engr.sjsu.edu/mjones
Email is the best way to contact me.
Course Description:
EE287 is an overview of CMOS ASIC concepts and design. Industry tools will be
used to illustrate principles taught. Overall concepts will be tied together by a
design project. Team work will be stressed.

2 Course Aims:
1. Prepare students to be productive members of an industrial ASIC design
team.
2. Prepare students for graduate projects involving digital circuits using ASIC
techniques and synthesis.
3. Provide an understanding of the ASIC life cycle.
4. Provide an opportunity developing teamwork skills.
5. Provide an environment where students learn to think critically.
6. Provide an environment where students learn to enjoy the design and
learning processes.
7. Have students internalize the culture of the design engineer.
Course Objectives (Outcomes):
To be productive members of an industrial ASIC design team students should be
able to:
Understand requirements and translate them to a high level design
language (Verilog not taught in EE287).
Understand capabilities and limitations of CMOS logic and adjust designs
to best use CMOS ASIC technologies.
Demonstrate common ASIC team rules, and articulate the purposes for
such rules.
Demonstrate an ability to use industry synthesis tools to achieve desired
project objectives.
Demonstrate an understanding of module interfaces, pipelining, Design for
test, test pattern generation, and BIST.
Modify designs to achieve performance objectives.

Perform an ASIC design from requirements to timing verification

Students who can think critically can:

design test benches that can prove that a design meet a specification
identify design errors, and adjust a design to meet all program criteria
A course goal is students learn to enjoy the CMOS ASIC design team experience
through a hands on approach.

3 Outcome Assessment (Grading):

Homework (20%): (-10% per class period late) Homework will consist of a
mix of analysis and design problems. Analytical and CAD based
techniques will be required to solve problems. The homework is designed
to reinforce lecture concepts and prepare the student for the exams and
class project. Homework assignments will be due roughly each week.
Students are encouraged to work in groups after homework 2, but each
student needs to try to solve the homework problems, before group
meetings. Place the last 4 digits of your SJSU ID on the homework to
ensure credit is given to the correct student.
o 50% of the homework grade is a class project. This project is a
design problem. The specifications are found on the web. Teams
of 2-4 people are expected to work on the design problem. To
discourage borrowing of other designs, the successful designs will
be run through a recursive difference engine, and the score will be
reduced by the similarity to other submitted designs. Both designs
will be penalized.

Midterm (35%): Covers the first half of the semester. A study guide is
available on the web site with typical questions. Several past midterms
are also posted on the web. All EE287 exams are closed book, no notes.
Scratch paper will be provided during the exam. You will be seated
randomly in the class, and there will be multiple versions of the exam. (58 typically). You should bring a calculator and writing instruments to the
exam.

Final Exam (45%): The final exam will be the same format as the midterm
except it will cover the entire semester with emphasis on the last half of
the semester.

4 Course outline and schedule

Date
27-Aug
29-Aug
3-Sep
5-Sep
10-Sep
12-Sep
17-Sep
19-Sep
24-Sep
26-Sep
1-Oct
3-Oct
8-Oct
10-Oct
15-Oct
17-Oct
22-Oct
24-Oct
29-Oct
31-Oct
5-Nov
7-Nov
12-Nov
14-Nov
19-Nov
21-Nov
26-Nov
28-Nov
3-Dec
5-Dec
10-Dec

Topic
Introduction, overview
CMOS gate review
ASIC concepts
Delay in CMOS overview
Cell types in 260
Latches and FFs
Working with latches
The clock cycle and paths
Fixing Long Paths and Races
Working with timing
A real library
Delay models
Timing closure
Clock distribution networks
Midterm Review
Midterm
Synchronizers
Multiple Clock domains
I/O pads and packaging
Power and Ground pins
Power estimation
Product debug requirements
Floorplan and impacts
Manf. test. D algorithm
Scan based testing
Bist -- Concepts
Bist -- Logic
Bist -- Memory

pdf readings
intro296.pdf,
CMOSASIC2000.pdf
cmosgr.pdf
asicconcepts.pdf
cmosdelay.pdf
260c_pri_e.pdf p 37-59
latches.pdf
discussion
clkcycle.pdf
examples, discussion
In lab discussion
260c_highpri_e.pdf
260c_pri_e.pdf p 61-72

Note

HW 1 due
Last day to add
HW 2 due

HW 3 due
Study Guide
---------------------HW 4 due
260e_mac_e.pdf I/O
pages, P16,17
HW 5 due

faults.pdf

Design Logic due

HW 6 due

Memories in ASICs
Review for Final

Design synthesis
due

There is no text book. The class notes are available on the web site
www.engr.sjsu/mjones
The class typically gets ahead of the green sheet, and then stops for review and
reinforcement.