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LabVIEW FPGA Programming Best Practices

Presented by:
Zach Hawkins, Software Developer, Averna
CLA, CPI
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Agenda

About Averna

Things to Keep in Mind

Structure

Style

Naming Conventions and Designs

No Pink in a Case

Standardization

Project Organization, Reuse and Portability

Synchronization and Multi-FPGA Systems

Summary
Q&A

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Things to Keep in Mind

If the code fits onto the FPGA, it fits!

Know that ~70% means its full

You may need to optimize later if/when new features are added

We dont believe in complexity for the sake of complexity

We almost exclusively use the SCTL

Some targets have IO nodes that will prevent using them inside SCTLs

NI has a course for this: High Throughput LabVIEW FPGA

Remember that the determinism of hardware is your friend

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Well, most of the time

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Structure: Project Organization

Setup for test-benching

Two high-level testing categories

o
o

On-chip testing
Off-chip testing

Requirements

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FPGA code
Host code
Shared code
Testing code

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Structure: Project Organization

Reuse and portability

How can we write FPGA code that can just be dropped into a new
project?

What if the code has configuration items?

o

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Use the Register Bus!

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Style: Naming Conventions & Project Organization

<Module>_FPGA

<Module>_Host

API VIs

<Module>_Shared

<Module>.vi
CreateResources.vi (Register Bus optional)
Registers.vi (Register Bus optional)

Resources.ctl (Register Bus optional)

FPGA_<Test/Module/Main>
Model_<Module/Algorithm>
Test_<TestName>

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Style: Designs State Machine

Makes code easier to read and follow

Normally, we would put all the logic in the case structure

Have you ever tried to implement a state machine in pure logic? We have

On an FPGA, additional enable chain logic is added to know which state is active

Think of it more as a State Controller

Only state control logic is necessary

Use handshaking to control logic that gets placed outside the case structure

Remember that each new case can cause a new MUX to be added in
the HW implementation

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Style: Designs State Controller

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Ever Seen Something Like This Before?

Solved with the Register Bus!

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Style: Designs Register Bus

Controls and indicators get implemented as MMRAs

o

Configuration data will come down from the host on a single DMA
channel

Think of it as a Pipe for both controls and indicators

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Can become costly/cumbersome

Put whatever you want on it!

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Style: Before Using the Register Bus

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Style: After Using the Register Bus

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Style: Designs Register Bus

Pros

Saves space on large applications

Allows for better code modularity and portability

Cons

A little more code to write

May be slower to read back large data sets or data larger than 32 bits
wide
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Solved for special cases by adding additional DMA FIFOs

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Style: Designs Basic Elements

Dont try to reinvent the wheel

There are some basic

operations that NI provides

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If you install an instrument

design library

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Style: Designs Counters

NI Decrement

Useful for a terminal count

NI Increment

Zero isnt really a valid number, except on the first set

o

But as programmers, we often like base-zero!

A Different Increment

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Supports reset and increment on the same cycle

Commands tell what to do on the next cycle

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Style: Designs NI Increment & Decrement

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Style: Designs A Different Increment

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Style: Designs Accessing Memory Items

Size of memory items: What gets implemented regardless of what you

set, etc.

36 bit port width for BRAM

If youre using a 64-bit data type, youre using 2 BRAMs
Think about it as a box how much stuff can you put in the box before
its full?

Use Base-2 addressing

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Easier logic but it can be wasteful . . . or is it?

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Style: No Pink in a Case

Using the case structure causes additional underlying logic that we

might not want (and dont have control over)

Fanout

Exceptions: Items without handshaking interfaces

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Memory writes

Registers.vi of the Register Bus

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Style: Avoid Costly/Unnecessary Operations

Many operations on FPGA that are free

Example: Shift/scale by power of 2

Many other operations are dependent on the width of the data type

Use only the bits that you need (FXP)

Unnecessarily large data types propagate through the chain

How would the operation be performed with hardware logic?

No unnecessary math on the FPGA

Example of a width-dependent operation:

Greater/less than or equal to

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Determinism normally allows you to simply use equal to!

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Standardization: Synchronization

How will data flow in your system?

How does the system respond when data isnt flowing?

What tells modules to start?

How are modules reset?

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Standardization: Feedback Nodes & Reset

Three options:

Uninitialized

Initialize on Compile or Load

Initialize on First Call

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Additional code is added to return the register to the default value when a
Reset command is sent (RESET = FANOUT!)
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Standardization: Multi-FPGA Systems

Do the FPGAs need to be synchronized?

What kind of synchronization?

Data-driven synchronization
o

Hardware synchronization
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P2P FIFOs

Clocks
Triggers

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Summary

Set up the project with testing in mind

Agree on standard naming conventions

Think of state machines as state controllers

Use the Register Bus to modularize designs and preserve space

Dont reinvent the wheel!

Make accessing memory simple with Base-2 addressing

No pink in a case (with some exceptions)

Develop to a standardized strategy for synchronization (or lack of!)

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Thank You!

Questions?

Zach Hawkins

Software Developer, Averna

CLA, CPI
zaha@averna.com
ni.com

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