EECS 142

Lecture 14: MOSFET LNA Design

Prof. Ali M. Niknejad
University of California, Berkeley
c 2005 by Ali M. Niknejad
Copyright

A. M. Niknejad

University of California, Berkeley

EECS 142 Lecture 14 p. 1/29

p.

MOS Amplifier Noise Figure

Rs

Vs

2
vR
g

Rg

Cgs

+
vgs

gm vgs

ro

RL

id

Lets recalculate the MOS amp noise figure (quickly).

Note that the current gain of the MOS amp is given by


1
vs
io = gm v1 = gm
1
jCgs
Rs + Rg + jC
gs
gm
gm
= vs
vs
1 + jCgs (Rs + Rg )
jCgs (Rs + Rg )
A. M. Niknejad

University of California, Berkeley

EECS 142 Lecture 14 p. 2/29

p.

Noise Figure by Current Gain

This can be rewritten as io = Gm vs , where
Gm =

1
T
j
Rs + Rg

This facilitates the noise calculations since the total

noise is given by
i2o,T = G2m (vg2 + vs2 ) + i2d

And the noise figure is easily computed

F =1+

A. M. Niknejad

vg2
vs2

i2d
G2m vs2

University of California, Berkeley

EECS 142 Lecture 14 p. 3/29

p.

Expression for F (again)

Substitution of the the various noise sources leads to
 2


Rg

gm
+
(Rs + Rg )2
F =1+
Rs
Rs
T
Assume that Rs Rg to get
 2


Rg

F =1+
+
gm Rs
Rs

Its important to note that this expression contains both

the channel noise and the gate induced noise. If we
assume that Rg = Rpoly + 5g1m , and the noise is
independent from the drain thermal noise, we get a
very good approximation to the actual noise without
using correlated noise sources.
A. M. Niknejad

University of California, Berkeley

EECS 142 Lecture 14 p. 4/29

p.

Minimum Noise for MOS Amp

Lets find the optimal value of Rs
F
=
Rs

 2


Rg

+
gm = 0
2
Rs

or

Rs,opt

 2


Rg

gm
=
2
Rs

T
s


2
 2
p  
Rg
T
= Rs = Rg
gm =

gm

We now have (after simplification)

 r
 

gm Rg
Fmin = 1 + 2
T

A. M. Niknejad

University of California, Berkeley

EECS 142 Lecture 14 p. 5/29

p.

MOS Amp Example

Lets find Rs,opt for a typical amplifier. Say fT = 75 GHz,


f = 5 GHz, and = 2. Also suppose that by proper
layout Rpoly is very small. The intrinsic gate resistance
is given by
1
1
=
Rg = Rpoly +
5gm
5gm

To make the noise contribution from this term 0.1

requires that
Rg
= 0.1
Rs
5gm Rs = 10
A. M. Niknejad

1
5gm Rs

= 0.1

10
1
gm =
=
S = 40 mS
5 50
25
University of California, Berkeley

EECS 142 Lecture 14 p. 6/29

p.

MOS Amp Continued

Note that for Vgs
fairly hefty

VT = 200 mV, the required current is

2Ids
gm =
= 40 mS
Vgs VT

1
Ids = 40 mS 200 mV = 4 mA
2
The optimum source resistance is given by
s
r
Rg
fT
5 25
Rs,opt =
= 15
119


f
2
gm
Fmin

A. M. Niknejad

f
=1+2
fT

gm Rg

 

2p
5 2/25 = 1.08
=1+

15

University of California, Berkeley

EECS 142 Lecture 14 p. 7/29

p.

MOS Amp Continued

This is a very low noise figure of .35 dB !!
In practice, though, itll be difficult to get this low of a
noise figure and get useful gain with the simple
common source. Lets see why.
Note that Cgs gm /T = 85 fF. The input impedance of
the FET is given by
1
= Rg
Zi = R g +
jCgs

A. M. Niknejad

T
j
5
gm

University of California, Berkeley

j375

EECS 142 Lecture 14 p. 8/29

p.

Matching Option 1
j157

Rs = 50

119

Matching
Network

Rg = 5
j375

Dont match the input impedance. Simply use a

matching network to multiply the 50 source up to 119.
This means that the source (antenna) will see a
termination that is m = 119/50 = 2.38 times smaller, or
about 157.
This is a good for noise but a bad power match.
A. M. Niknejad

University of California, Berkeley

EECS 142 Lecture 14 p. 9/29

p.

Matching Option 2
2

Rs = 50

+j375
Rg = 5

Matching
Network

j375

119

Use an inductor to tune out the capacitive part of the

input. This will add noise due to finite inductor Q. Note
that the matching network will match this low 5
resistance down to 5/2.38 2.
Now the power match is even worse.

A. M. Niknejad

University of California, Berkeley

EECS 142 Lecture 14 p. 10/29

Matching Option 3
Q2 Rg

Rs = 50

Rg = 5

Matching
Network

j375

119

Use a shunt inductor to resonate the input impedance.

The inductor should be connected to the DC value of
Vgs and can double as a bias element.

A. M. Niknejad

University of California, Berkeley

EECS 142 Lecture 14 p. 11/29

Option 3 (cont)
But since the gate capacitance is high Q
Q=

1
Cgs Rg

1
Cgs 5g1m

fT
= 5 15 = 75
=5
f

The input resistance is going to be Q2 Rg 28 k, or too

big.
The matching circuit will bring this down to about
12 k, a very poor match.

A. M. Niknejad

University of California, Berkeley

EECS 142 Lecture 14 p. 12/29

Source/Emitter Degeneration
The voltage at the input of the
amplifier is given by
vx = ix Zgs + (ix + gm Zgs ix )Zs
Zin = Zs + Zgs + gm Zgs Zs
| {z }

ZL

due to feedback

Lets assume that Zs is reactive

(zero noise)
gm X
1
jX =
gm Zgs Zs = gm
jCgs
Cgs

Zin
ZS

which produces a purely passive input resistance if X > 0

A. M. Niknejad

University of California, Berkeley

EECS 142 Lecture 14 p. 13/29

Inductive Degeneration
The reactive feedback from an
inductor produces a broadband
programmable real input impedance
that can simplify matching (or even
eliminate it altogether).
gm L
T L
(Zin ) =
Cgs

We thus select L by L =

Rs
T

If this value of L is impractical, we

can artificially reduce T by inserting
a capacitor in shunt with Cgs .

A. M. Niknejad

University of California, Berkeley

EECS 142 Lecture 14 p. 14/29

Series Resonant Input

The input impedance of the FET
with inductive degeneration is
given by
Zin

1
+ T Ls
= jLs +
jCgs

Zin
Rs
+
vs

Lg

Ls

1
+ Rs
= jLs +
jCgs

The input impedance behaves like a series RLC circuit.

We need to tune the resonant frequency of the series
circuit to align with the operating frequency. This can be
done by adding gate inductance Lg

A. M. Niknejad

University of California, Berkeley

EECS 142 Lecture 14 p. 15/29

Q Boosting
Recall that in a resonant circuit, the voltage across the
reactive elements is Q times larger than the voltage
across the resistor.
At resonance, the voltage across the resistors is simply
vs , so we have
vgs = Q vs

Q=

A. M. Niknejad

+
vs

1
0 Cgs 2Rs

gm
Gm = Qgm =
=
0 Cgs 2Rs

Rs

T
0

University of California, Berkeley

Lg

Q +
v
s

id = gm vgs = Q gm vs = Gm vs

Ls

1
2Rs
EECS 142 Lecture 14 p. 16/29

Equivalent Circuit at Resonance

From the source, the amplifier input (ignoring Cgd ) is
equivalent to the following circuit
Rs

Lg

Cgs

+
vs

Ls
T Ls

At resonance, the complete circuit is as follows

Rs
+
vs

A. M. Niknejad

Rs

University of California, Berkeley

Q gm vs

EECS 142 Lecture 14 p. 17/29

Noise Figure for Inductive Degen

Rs

Vs

Lg

2
vR
g

Rg

Cgs

io
+
vgs

gm vgs

ro

id

Ls

Its fairly easy to calculate the noise for the case with
inductive degeneration. Simply observe that the input
generators (vs2 and vg2 ) see a gain of G2m to the output.
The drain noise i2d , though, requires a careful analysis.
Since i2d flows partly into the source of the device, it
activates the gm of the transistor which produces a
correlated noise in shunt with i2d .
A. M. Niknejad

University of California, Berkeley

EECS 142 Lecture 14 p. 18/29

Drain Noise (degen)

Lg

Rs

io

Cgs

+
vgs

gm vgs

id

Ls

The above equivalent circuit shows that the noise

component flowing into the source is given by the
current divider
v =

A. M. Niknejad

jLs
1
(gm v + id )

1
jLs + jCgs + jLg + Rs jCgs
University of California, Berkeley

EECS 142 Lecture 14 p. 19/29

Drain Noise (degen)

The denominator simplifies to Rs at resonance, so we
have
jLs 1
v = (gm v + id )
Rs jCgs
Ls
= (gm v + id )
Cgs Rs


Ls
gm Ls
v 1 +
= id
Cgs Rs
Cgs Rs

But T Ls = Rs , so we have

2v =
A. M. Niknejad

Ls
id
Cgs Rs

or

gm v =

University of California, Berkeley

id gm Ls
=
2 Cgs Rs

id
2
EECS 142 Lecture 14 p. 20/29

Total Output Noise (degen)

So we see that only 1/4 of the drain noise flows into the
output! The total output noise is therefore
i2o,T

G2m (vs2

F =1+

vg2
vs2

+ vg2 ) +
+

1 2
id
4

i2d
4vs2 G2m

Substitute as before and we have

 2


2
Rg

gm (2Rs )
F =1+
+
Rs
4Rs
t

A. M. Niknejad

University of California, Berkeley

EECS 142 Lecture 14 p. 21/29

Noise Figure with Degen

Note that the noise figure is the same as the common
source amplifier
 

Rg
+
gm Rs
F =1+
Rs

2

The inductive degeneration did not raise the noise ! So

the minimum noise figure Fmin is the same.
The advantage is that the input impedance is now real
and programmable (T Ls ). By proper sizing, its
possible to obtain a noise and power match.

A. M. Niknejad

University of California, Berkeley

EECS 142 Lecture 14 p. 22/29

LNA Chip/Package/Board Interface

package
leads

on-chip
spiral
PCB trace
bond wire

Since the LNA needs to interface to the external world,

its input network must transition from the Si chip to the
package and board environment, which involves
macroscopic structures such as bondwires and
package leads.
A. M. Niknejad

University of California, Berkeley

EECS 142 Lecture 14 p. 23/29

Bond Wire Inductance

One reason inductive degeneration is popular is
because we can use package parasitics to our benefit.
Some or all of Ls can be absorbed into the loop
inductance (or the partial inductance of the bondwire)
These parasitics must be absorbed into the LNA design.
This requires a good model for the package and
bondwires. It should be noted that the inductance of the
input loop depends on the arrangement of the
bondwires, and hence die size and pad locations.
Many designs also require ESD protection, which
manifests as increased capacitance on the pads.

A. M. Niknejad

University of California, Berkeley

EECS 142 Lecture 14 p. 24/29

Package Parasitics
Recall that a changing flux generates an emf around a
circuit loop. Let

L=
I
dI
d
=L
vemf =
dt
dt
Note that in reality is composed of flux from all the
loops in the package, causing undesired mutual
coupling to other parts of the circuit
vemf

A. M. Niknejad

d(1 + 2 + 2 + )
dI1
dI2
=
=L
+ M12
+
dt
dt
dt

University of California, Berkeley

EECS 142 Lecture 14 p. 25/29

Cascode LNA
Vdd

LL
Vout
Vcas
M2
Vin

C1

Zin

Lg
M1

Rs
Ls

A. M. Niknejad

Its very common to use a

cascode device instead of a
common source device.
This simplifies matching since
the cascode device is nearly
unilateral.
Lets show that the cascode
device adds virtually no noise
at low/medium frequencies.

University of California, Berkeley

EECS 142 Lecture 14 p. 26/29

Cascode Noise Contribution

io

Cgs

+
vgs

gm vgs

id

ro

The noise contribution

from the cascode is
small due to the degeneration. For simplicity
assume the transistor
degeneration is ro . Then
most of the drain noise
current will flow into Cgs
at high frequency

1
v = (gm v + id )
jCgs
v (jCgs
gm v =
A. M. Niknejad

gm

gm ) = id

gm
id =
jCgs
1
University of California, Berkeley

1
id
j T

id
EECS 142 Lecture 14 p. 27/29

Cascode (cont)
A similar calculation shows that at low frequency, the
noise into ro produces an output current noise of
(id + gm v )ro =
id ro =

gm ro v =

v
(1 + gm ro )v

ro
id
v =
1 + gm r o
gm ro
gm v =
id
1 + gm r o

id

The total current noise is therefore





gm ro
1
1
id =
id 0
1 + gm r o
1 + gm r o
A. M. Niknejad

University of California, Berkeley

EECS 142 Lecture 14 p. 28/29

Differential LNA Design

One
undesired
consequence
of
the package is
that the parasitic
inductors vary from
on-chip
part to part and
inductors
bond-wire,
require
careful
on-chip
modeling and extra
or off-chip
bond-wire
care to correctly
inductance
implement
the
LNA.
The advantage of a differential LNA is that the parasitics
are only on the gate side, and not on the source of the
transistors. The source inductors are realized with
on-chip inductors with tight process tolerances.
A. M. Niknejad

University of California, Berkeley

EECS 142 Lecture 14 p. 29/29