THE UNIVERSITY OF THE WEST INDIES

ST. AUGUSTINE, TRINIDAD & TOBAGO, WEST INDIES

FACULTY OF ENGINEERING
Department of Electrical & Computer Engineering

ECNG 3016
ADVANCED DIGITAL ELECTRONICS
http://myelearning.sta.uwi.edu/course/view.php?id=686
Semester II 2009
1.

GENERAL INFORMATION
Lab #:
Name of the Lab:

1 Part B
Frequency Division and Time Multiplexing of Displays

Lab Weighting:

0%

Delivery mode:

Lecture

Online
 Lab

Other

Venue for the Lab:

Microprocessor Laboratory

Lab Dependencies2

The theoretical background to this lab is provided in ECNG 3016

Theoretical content link: given at top of page
Pre-Requisites ECNG 2004
To undertake this lab, students should be able to:
1. Use of Xilinx ISE and Modelsim in the implementation of digital
system
2. VHDL programming

Recommended
prior knowledge
and skills3:

Course Staff
Lucien Ngalamou
Marcus George

Position/Role
Lecturer
Instructor

Estimated total
study hours1:

E-mail

lucien.ngalamou@sta.uwi.tt
marcus.george@sta.uwi.tt

Phone


Office

Office
Hours

room 202
room 203

THE UNIVERSITY OF THE WEST INDIES

ST. AUGUSTINE, TRINIDAD & TOBAGO, WEST INDIES
FACULTY OF ENGINEERING
Department of Electrical & Computer Engineering

2.

LAB LEARNING OUTCOMES

Upon successful completion of the lab assignment, students will be able to:
1. Understand the concept of frequency division
2. Design and implement a frequency divider in VHDL to meet a required
specification
3. Understand the concept of Time Multiplexing of displays
4. Design and implement a Time Multiplexing display unit to meet a required
specification

Cognitive
Level
C
Ap
C
Ap

3. PRE-LAB
Due Date:
Submission
Procedure:
Estimated time to
completion:
3.1. Required Reading Resources
3.2. Recommended Reading Resources
3.3. Other Resources
3.4. Pre-Lab Exercise

THE UNIVERSITY OF THE WEST INDIES

ST. AUGUSTINE, TRINIDAD & TOBAGO, WEST INDIES
FACULTY OF ENGINEERING
Department of Electrical & Computer Engineering

4.

IN-LAB

Allotted Completion 3 hours

Time:
1 Computer
Required lab
1 Spartan 3 Toolkit
Equipment:
4.1. In-Lab Procedure
Seven-segment displays are now widely used in almost all microprocessor-based instruments.
A single seven-segment display can display the digits from 0 to 9 and the hex digits A to F. Each
display is composed of seven LEDs that are arranged in a way to allow the display of different digits
using different combinations of LEDs figure 1.

Figure 1: Common anode detail

Since the display is composed of LEDs, which need high current to drive them, power consumption
is very critical. Consider a panel with 4 displays and the number to be displayed is 8888. Each LED
needs 20 mA. So we need a current of 20x7x4 = 560 mA. Thats a lot of current compared to the
current consumed by the microprocessor. Another problem is the number of components and output
bits that are needed to connect the displays to the processor. We need at least 4x7 = 28 resistors and
28 output bits for the 4 displays. Is there a solution for these problems? Yes, there is, its called
MULTIPLEXING!
The Pegasus board contains a four-digit common anode seven-segment LED display. The
display is multiplexed, so only seven cathode signals exist to drive all 28 segments in the display.

THE UNIVERSITY OF THE WEST INDIES

ST. AUGUSTINE, TRINIDAD & TOBAGO, WEST INDIES
FACULTY OF ENGINEERING
Department of Electrical & Computer Engineering

Four digit-enable signals drive the common anodes and these signals determine which digit the
cathode signals illuminate figure 2.

Figure 2: Common anode Sseg display

This connection scheme creates a multiplexed display, where driving the anode signals and
corresponding cathode patterns of each digit in a repeating, continuous succession can create the
appearance of a four-digit display. Each of the four digits will appear bright and continuously
illuminated if the digit enable signals are driven low once every 1 to 16ms (for a refresh frequency of
1KHz to 60Hz). For example, in a 60Hz refresh scheme, each digit would be illuminated for one
quarter of the refresh cycle, or 4ms. The controller must assure that the correct cathode pattern is
present when the corresponding anode signal is driven (figure 3).
To illustrate the process, if AN0 is driven low while CB and CC are driven low, then a "1" will
be displayed in digit position 0. Then, if AN1 is driven low while CA, CB and CC are driven low,
then a "7" will be displayed in digit position 1. If A1 and CB, CC are driven for 4ms, and then A2
and CA, CB, CC are driven for 4ms in an endless succession, the display will show "17" in the first
two digits. Figure 4 shows the pattern of decimal digit.

THE UNIVERSITY OF THE WEST INDIES

ST. AUGUSTINE, TRINIDAD & TOBAGO, WEST INDIES
FACULTY OF ENGINEERING
Department of Electrical & Computer Engineering

Figure 3: Sseg signal timing

Figure 4: Cathode pattern for decimal digits

THE UNIVERSITY OF THE WEST INDIES

ST. AUGUSTINE, TRINIDAD & TOBAGO, WEST INDIES
FACULTY OF ENGINEERING
Department of Electrical & Computer Engineering

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mux7seg is
Port(muxclk: in std_logic; multiplexing clock
areset: in std_logic; asynchronous reset
switchs : in std_logic_vector(7 downto 0); slide switches inputs
sseg : out std_logic_vector(6 downto 0); 7-segement leds
anode : buffer std_logic_vector(3 downto 0)); selection of the 7-segment
end mux7seg;
The function of the circuit is described in the architecture. There are certain considerations that
have to be taken into account. Only one of the seven segment displays can be active at a time. It is
selected by the output signal anode. The signal anode can have at a single given moment only one
value like 1110, 1101, 1011, or 0111. This function can be implemented by a shift register with a
parallel load. The shifting operation of this shift register must be clocked by an internal clock signal
with a period between 0.25 ms and 4 ms. Let it be 1 ms. The input clock is at 50 MHz, so it must be
divided by 50000 in order to get an internal clock of 1000 Hz (1 ms period). If the signal anode is
1110 (selecting display #1), then only bits 3 downto 0 of display_value are displayed. If
anode=1101, then bits 7 downto 4 of display value are displayed (display#2). This means that the
upper and lower 4 bits coming from the 8 switches SW7 to SW0 must be multiplexed to the decoder
for the seven segment display. In all other cases the control signals sseg must be set to 1 in order to
turn off the diodes.
There are three processes associated with displaying the result from input data (8 switches): (1)
select the seven segment display; (2) select the four bits to decode; (3) decode the bits. The shifting
process is synchronized with the muxclk signal, and is reset by the asynchronous signal areset. You
can think of it as a shift register. The shifting can be expressed with a construct like this: anode <=
(anode(0) & anode(3 downto 1)); Remember to load anode with an initial value of say 1110, when
areset is high.The multiplexing process is sensitive to the changes both in the displayed signal(data
from the input switches) and in the selection signal a. The multiplexing can be done with a case

THE UNIVERSITY OF THE WEST INDIES

ST. AUGUSTINE, TRINIDAD & TOBAGO, WEST INDIES
FACULTY OF ENGINEERING
Department of Electrical & Computer Engineering

construct: case anode is

when "1110" => disp_led <= ...
...
end case;
Notice that bits to decode must be an internal signal with which the multiplexing and
the decoding processes will communicate with each other. The decoding process is sensitive to
changes in the selected display (changes in anode) and to changes in the displayed value (bits to
decode). The project file to be used here is mux7seg_lab3.npl.

Write the VHDL code of the multiplexing display, simulate it, synthesize and test it
on the FPGA board. In your report, you will have to add the complete code and the
simulation result. FPGA switches must be used to test the time multiplexing displays. Results of this
test must be clearly shown in report. Figure 5 below is the datapath block diagram of the system.

clk

Frequency Divider
RESET

clock1

reset

clk

seg
7

RESET

reset

2-digit Time MUX

display_value

connected to switches

anode

Figure 5: Block diagram interface between frequency divider and time multiplexer

Lab 1b: Frequency Division and Time Multiplexing of Displays

Design Port

FPGA Pin to be mapped to

clk
reset
display_value(0)
display_value(1)
display_value(2)
display_value(3)
display_value(4)
display_value(5)
display_value(6)
display_value(7)
anode(0)
anode(1)
anode(2)
anode(3)
seg(0)
seg(1)
seg(2)
seg(3)
seg(4)
seg(5)
seg(6)

T9
any available pushbutton
F12 - switch
G12 - switch
H14 - switch
H13 - switch
J14 - switch
J13 - switch
K14 - switch
K13 - switch
D14
G14
F14
E13
E14
G13
N15
P15
R16
F13
N16

Table 1: Pin Configuration for the Time Multiplexing of displays design

1. Explain all steps required to upgrade the two digit time multiplexer to the four-digit time
multiplexer.
2. Upgrade the two-digit time multiplexer to a four-digit time multiplexer(capable of displaying
4 digits). A new VHDL module must be created for this purpose and labelled
four_digit_multiplexor.vhd.
3. Observe time multiplexing at high and low frequencies. This can be done by modifying the
frequency divider to produce required frequencies. Utilize the following frequencies below:
i. 1kHz
ii. 1Hz
iii. 50MHz

Proceed to post-lab exercise.

Lab 1b: Frequency Division and Time Multiplexing of Displays

5.

POST-LAB

A signed plagiarism declaration form must be submitted with your assignment.

Due Date:
Submission
Procedure:
Deliverables:

N/A
N/A
N/A

End of Lab 1b: Frequency Division and Time Multiplexing of Displays

Lab 1b: Frequency Division and Time Multiplexing of Displays

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