Documenti di Didattica
Documenti di Professioni
Documenti di Cultura
INTRODUCTION
If no bias to the gate is given MOSFET acts as two back to back diodes, namely n+
drain and p-type substrate one diode and p-type substrate and n+ source other
diode.
These back to back diodes prevent current conduction from drain to source when a
voltage vDS is applied i.e., the path between drain and source has very high
resistance (10 12 ohms).
If source and drain are grounded and positive voltage vGS is applied to gate, the
majority carriers (holes) in the p-type substrate below the gate (in the channel
region)are repelled and pushed downward into the substrate, leaving behind bound
negative charges associated with the acceptor atoms.
Also the positive gate voltage attracts electrons (majority carriers) from both n+
source and n+ drain regions in between the source and drain.
Now if a positive voltage is applied between drain and source, current flows through
the induced region carried by mobile electrons.
This induced region forms a channel for current flow from drain to source. Therefore
this MOSFET is called the n-channel MOSFET or NMOS Transistor.
The induced channel is also known as inversion layer because it is created by
inverting the substrate surface from p-type to n-type.
The value of vGS at which sufficient quantity of electrons accumulate in the channel
region to form a conducting channel is called the threshold voltage Vt whose typical
value is 0.5 to 1V.
The gate and channel form a parallel plate capacitor with oxide layer acting as the
dielectric.
A small vDS (=50mV) causes a current iD to flow through the induced n channel from D
to S.
Magnitude of iD depends on the density of electrons in the channel, which is
dependent upon vGS.
Specifically for vGS = Vt, the channel is just induced and current is negligibly small.
As vGS exceeds Vt more electrons are attracted into the channel, resulting in a
channel of increased conductance and decreased resistance.
This conductance is proportional to (vGS-Vt) also known as the Effective Voltage or
Overdrive Voltage.
Also the current iD is proportional to (vGS-Vt) as well as vDS.
Fig below shows the sketch of iD vs vDS for different values of vGS (for small values of
vGS).
MOSFET acts as a linear resistance here and its value is infinite for vGS<=Vt and
decreases as vGS exceeds Vt.
Since channel size increases as vGS exceeds Vt, MOSFET is called enhancement
type MOSFET or enhancement mode MOSFET.
As vDS is increased, when vDS= vGS-Vt, the channel depth at the drain becomes almost
zero and the channel is said to have pinched off.
If vDS is increased beyond this, it will have no effect and the drain current saturates
and MOSFET is said to have entered the saturation region of operation. Thus vDS
sat = vGS Vt.
For every vGS>=Vt there is a corresponding vDS sat and the device operates in the
saturation region when vDS>= vDS sat. And the region where vDS < vDS sat is called the
triode region
Derivation of iD vs vDS
Gate and channel region form a parallel plate capacitor with oxide acting as
dielectric.
The capacitance /unit area Cox is then given by
Cox = ox/tox ; where tox is the thickness of oxide layer and the permittivity
ox =3.9 o=3.9 x 8.854 x 10 -12 = 3,45 x 10 -11 F/m
Consider an infinitesimal strip dx of gate at distance x from source. The capacitance
of this strip is Cox W dx.
The charge stored on this strip is
......................................(1)
Voltage vDS produces electric field along the channel, this electric field at the point x
is written as
E(x) = -dv(x)/dx
The electric field causes electric charge to drift towards the drain with velocity dx/dt
given by
dx/dt = - n E(x) = -n dv(x)/dx
.....................................(2)
where n is the mobility of electrons.
The resulting drift current is given by
i= dq/dt = (dq/dx )(dx/dt)
Substituting from (1) and (2) we get
i = -n Cox W [ vGS v(x)-Vt] dv(x)/dx
This is the source to drain current. Therefore the drain current is
iD= -i = n Cox W [ vGS v(x)-Vt] dv(x)/dx
i.e., iD dx = n Cox W [ vGS v(x)-Vt] dv(x)
Integrating both sides we get
iD dx =
in saturation region
n-channel
p-type
Electrons
Positive
D to S
Smaller
Faster
Lower
p-channel
n-type
Holes
Negative
S to D
Bigger
Slower
Higher
CUURENT-VOLTAGE CHARACTERSTICS
Circuit Symbol
Spacing between two vertical lines representing gate and channel indicates the
insulation (dielectric SiO2 layer).
Arrowhead represents the polarity of NMOS.
It also represents p-type body and n-channel
MOSFET is a symmetrical device; however it is useful to designate one as Source
and other as drain.
The simplified symbols are shown in fig where body is connected to source.
Fig 1 shows the NMOS with voltages vDS and vGS applied and with normal direction of
current flow.
Fig 2 shows a typical set of iDvDS curves, which show three distinct regions; cut-off,
triode and saturation.
Vov = VGS>Vt
FIG 1
FIG 2
Characteristics of a pmos
In cut off
vGS > Vt
Triode region
vGS <= Vt and vDS >vGS-Vt
and current iD is given by
iD = kp (W/L) [ (vGS -Vt ) vDS ( vDS 2/2)] where kp= p Cox and p=0.25 to 0.5 n
Saturation Region vGS <= Vt and vDS <=vGS-Vt
and current iD is given by
iD = ()kp (W/L) (vGS -Vt ) 2(1+ vDS)
2f +VSB
2f
) ................................(6)
Where Vt0 is the threshold voltage when VSB = 0, f is the physical parameter with
2 f = 0.6 and is fabrication process parameter, given by
=
Where q is electronic charge 1.6 X 10-19 C, NA is acceptor doping concentration of
p-substrate and Si =permittivity of Si = 11.7 0 = 11.7 x 8.854 x 10-12 =1.04 x 10-10
has dimensions of
V
, VSB is +ve for reverse biasing
Temperature Effects
We assumed that when vGS < Vt then iD=0 and device is cut-off .
However a small drain current flows. In this sub-threshold region of operation iD
is exponentially related to vGS
There are special but growing number of applications that make use of subthreshold region of operation.
In the saturation region MOSFET acts as a voltage controlled current source i.e.,
changes in vGS give rise to changes in iD.
Thus MOSFET can be used as a Trans-conductance Amplifier.
The relationship between vGS and iD is highly nonlinear( Square Law).
To linearize it we provide dc biasing, so as operate the MOSFET at a dc voltage
VGS & corresponding ID & then superimpose the voltage signal vgs to be amplified
on the dc voltage VGS .
If vgs is kept small, the resulting change in drain current can be made nearly
proportional to vgs.
Fig (a) shows circuit of a Common Source (CS) MOSFET amplifier and fig (b)
shows the output characteristic of the MOSFET circuit.
Operation as a Switch
When vI < Vt the MOS is cot off (turned OFF) resulting in vO = VDD.
When vI VDD , the MOS operates around C & is turned ON (triode region) & vO is
very small i.e., vO = VOC
Thus Common Source (CS) MOS can be used as a logic inverter with low
voltage close to 0 and high voltage close to VDD
However CMOS device acts as a better inverter.
Fix the gate to source voltage VGS so as to provide the desired ID.
VGS can be derived either from
o VDD , by using appropriate voltage divider network.
OR
o Suitable reference voltage in the system
However biasing by fixing VGS is not a good approach.
In saturation region ID vs VGS is given by
ID = (1/2) n Cox (W/L) (VGS Vt )2
The value Vt -the threshold voltage, Cox -the oxide capacitance & W/L vary widely
among devices.
Also both Vt and n are temperature dependent i.e., even we fix VGS , the ID will be
temperature dependent.
This can be emphasized by the curve given below where the spread for ID will be
large for the two curves with same VGS.