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I. INTRODUCTION
ULTILEVEL inverters include an array of power semiconductors and dc voltage sources, the output of which
generate voltages with stepped waveforms [1]. In comparison
with a two-level voltage-source inverter (VSI), the multilevel
VSI enables to synthesize output voltages with reduced harmonic distortion and lower electromagnetic interference [2].
By increasing the number of levels in the multilevel inverters,
the output voltages have more steps in generating a staircase
waveform, which has a reduced harmonic distortion. However,
a larger number of levels increase the number of devices that
must be controlled and the control complexity [3].
There are three well-known types of multilevel inverters [4],
[5]: the neutral point clamped (NPC) multilevel inverter, the
flying capacitor (FC) multilevel inverter, and the cascaded
H-bridge (CHB) multilevel inverter. The NPC multilevel inverter, also called diode-clamped, can be considered the first
generation of multilevel inverter introduced by Nabae et al. [6]
which was a three-level inverter. The three-level case of the NPC
multilevel inverters has been widely applied in different industries. Unlike the NPC type, the FC multilevel inverter offers
Manuscript received July 30, 2011; revised November 16, 2011 and February
4, 2012; accepted May 24, 2012. Date of current version September 27, 2012.
Recommended for publication by Associate Editor J. R. Rodriguez.
The authors are with the Faculty of Electrical and Computer Engineering, University of Tabriz, 51664 Tabriz, Iran (e-mail: m.farhadi@tabrizu.ac.ir;
e-babaei@tabrizu.ac.ir).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TPEL.2012.2203339
626
TABLE I
OUTPUT VOLTAGES FOR STATES OF SWITCHES
Fig. 1.
Considering Fig. 1, for each value of the output voltage of submultilevel inverter, two switches must be turned ON, one from
the upper switches and the other from the lower switches. For
example, to get output voltage of Vdc , the switches S1 and S2 are
turned ON. In order to obtain the output voltage of (n 1)Vdc ,
the switches Sn /2 and S(n
+2)/2 should be turned ON.
Considering Fig. 1, the following equations can be written:
2,
for n = 1
Nswitch,sub =
(1)
(n + 2), for n 2
Ndriver,sub = Nswitch,sub
(2)
NIGBT,sub = 2n
(3)
Nsource,sub = n
(4)
2m + 4,
for n = 1
m (n + 2) + 4,
for n 2
627
(6)
Ndriver = Nswitch
(7)
NIGBT = 2mn + 4
(8)
Nsource = mn
(9)
Nlevel = 2mn + 1
(10)
(11)
( n 1 )
1
1
1 )/2
( n +2
2
4
3n
n
1
n+1
5
n1
2
k Vdc,i + 2
k Vdc,i +
Vdc,i =
+n+
Vdc,i
2
2
4
8
8
k
=0
k
=0
n1
is even
if n is odd and
+1
1 )/2
( n 21
(n
4 1 )
3n
n1
n+1
5
n+1
k
V
k
V
V
+
n
+
2
+
2
+
=
Vdc,i
dc,i
dc,i
dc,i
2
2
4
8
8
Vstand,i =
k =0
k =0
1 )/2
( n2
3n
k
V
+n+
=
dc,i
2
8
k
=0
2
4 1 )
3n
n
n
k Vdc,i + Vdc,i =
4
2
2
8
k =0
n1
is odd
if n is odd and
2
1
2
Vdc,i ,
+ n Vdc,i
if n is even and
n
is odd
2
if n is even and
n
is even
2
(5)
628
(12)
(13)
Nlevel 1
m=
(14)
2n
From (13) and (14), the following equation is obtained:
Nlevel 1
Vstand,1
+ 4Vdc,1 . (15)
Vstand,total =
2
n
2) Proposed Asymmetric Multilevel Inverter: For the asymmetric topology, the value of the dc voltage sources is different
from a submultilevel inverter to another. In other words, if the dc
sources of the first submultilevel inverter is Vdc,1 , the dc sources
of the second submultilevel inverter is Vdc,2 . To get maximum
number of level for the output voltage, there must be no redundancy. This is achieved when the value of the dc voltage sources
in submultilevel inverters have the following relation:
Vdc,2 = (n + 1) Vdc,1
Vdc,3 = (n + 1)Vdc,1 + nVdc,2 = (n + 1)Vdc,1 + n(n + 1)Vdc,1
= (n + 1)(n + 1)Vdc,1 = (n + 1)2 Vdc,1 .
(16)
i = 1, 2, 3, . . . , m
(17)
Using (17) and (18), the maximum value of the output voltage
can be written as
Vo,m ax = [(n + 1)m 1]Vdc,1 .
(19)
(20)
m
i=1
Vstand,i + 4Vo,m ax .
(21)
Using (5), (17), (19), and (21), the total standing voltage of
the switches can be written as follows:
(n + 1)m 1
Vstand,total =
n
Vstand,1 + 4[(n + 1)m 1] Vdc,1 . (22)
Using (20) and (22), the total standing voltage in terms of
number of output voltage level and n can be expressed as
follows:
Nlevel 1
Vstand,1
+ 4Vdc,1 . (23)
Vstand,total =
2
n
C. Optimal Structures
In this section, the aim is to determine the optimal structures
considering different aspects. For the proposed multilevel inverter, there are two design parameters. The first parameter is
the number of dc sources in each submultilevel inverter n and
the other is the number of series connected submultilevel inverters, m. Both m and n affect maximum value of the output
voltage. However, one of them can be used as a parameter for
topology optimization and the other should be left to meet the
desired maximum value of the output voltage (output voltage
rating of the multilevel inverter). Here, m is used to meet the
required nominal voltage. Therefore, n is used as a variable
to determine the optimal structures. In the following, the optimal structures are discussed for the proposed symmetric and
asymmetric multilevel inverters.
1) Optimal Structures of the Symmetric Topology: The aim
is to determine the parameter n in order to use minimum number
of IGBTs for a specific number of levels. Using (8) and (11),
NIGBT can be written as follows:
NIGBT = Nlevel + 3.
(24)
for n = 1
(Nlevel 1) + 4,
Ndriver = n + 2
(Nlevel 1) + 4, for n 2
2n
1,
for n = 1
Ndriver 4
= n+2
Normalized Ndriver =
Nlevel 1
, for n 2.
2n
(25)
Fig. 3 shows variation of the normalized value of the number
of drivers versus n for a given number of voltage levels. The
figure indicates that as n increases, the number of required
629
N s w i t c h 4
2
2(2)
1,
for n = 1
Nlevel =
N s w i t c h 4
2(n + 1) ( n + 2 ) 1, for n 2
1
2(2 2 )N s w i t c h 4 1,
for n = 1
=
1
(N s w i t c h 4)
2 (n + 1) ( n + 2 )
1, for n 2.
Normalized Vstand,total =
(27)
In (27), the number of switches is considered as a constant.
Therefore, the number of voltage levels is maximized for such
an n that maximizes the following term:
1
for n = 1
22 ,
(28)
D=
1
(n + 1) ( n + 2 ) , for n 2.
Fig. 4 shows the variation of D versus n. As the figure indicates, n = 1 gives the optimal structure from the viewpoint of
number of switches.
Fig. 4.
Similarly, another optimal structure can be obtained for minimizing the number of switches for a constant number of voltage
levels. In this case, using (27), the following equation can be
written:
2
for n = 1
ln 2 ,
Nswitch 4
=
(29)
ln N l e v2e l 4
(n + 2) , for n 2.
ln(n + 1)
The variation of (29) versus n is also depicted in Fig. 4. It is
clear that n = 1 gives again the optimal structure.
Considering (7), the number of gate drivers is equal to the
number of switches. Therefore, n = 1 also gives the optimal
structure from the viewpoint of minimum gate drivers.
In the previous analysis, the number of switches was considered as a criterion for determining the optimal structures. As
mentioned before, the number of switches is not equal to the
number of IGBTs. If the number of IGBTs is used as a criterion,
the results will be the same.
Considering (8) and (20), the number of voltage levels as a
function of n for a constant number of IGBTs is as follows:
N I G B T 4
1
Nlevel = 2(n + 1) 2 n
1 (N
4)
IG B T
1.
= 2 (n + 1) 2 n
(30)
Taking into account that the number of IGBTs has been considered to be constant, in (30), the number of voltage levels will
be maximum if the term 2(n + 1)1/2n is maximum.
Fig. 4 also shows the variation of 2(n + 1)1/2n versus n. As
this figure shows, the number of levels decreases as n increases.
Therefore, the maximum number of voltage level for a constant
number of IGBTs is obtained when n is equal to 1. The same
result can be obtained for the minimum number of IGBTs for a
constant number of voltage levels.
The number of the dc voltage sources Nsource is the other
variable which is used to obtain optimal topology. The aim is
to minimize the number of required dc voltage sources for a
specific number of voltage levels. Using (9) and (20), Nsource
can be written as follows in terms of the number of output
voltage levels and the number of dc voltage sources in each
submultilevel inverter:
Nlevel + 1
n
ln
Nsource =
.
(31)
ln(n + 1)
2
630
x(t)VT ,j + y(t)VD ,j
1
i(t)
Pc,sub,j =
0
+x(t)RT ,j i (t) + y(t)RD ,j i(t)
d(t).
The specifications of the switches used in different submultilevel inverters may be different. Therefore, the index j in the
aforementioned equation is used in order to refer to the jth submultilevel inverter. As the losses are calculated for the typical
jth submultilevel inverter, it can be extended to other cascaded
submultilevel inverters.
As the conduction power loss of the cascaded submultilevel
inverters are calculated one by one, they are added together to
obtain the total conduction power loss Pc, sub of the cascaded
submultilevel inverters:
Pc,sub =
Pc,sub,j .
(36)
j =1
2
2
RD ,H Im
=
(2 sin(2))
VD ,H Im (1 cos ) +
A. Conduction Losses
In order to calculate the conduction losses, first conduction
losses of a typical power transistor and diode are calculated; then
they are developed to the multilevel inverter. The instantaneous
conduction losses of a transistor (pc,T (t)) and diode (pc,D (t))
can be written as follows:
(35)
+ VT ,H Im (1 + cos )
+1
+ RT ,H Im
sin +1 (t)d(t) .
(37)
(33)
(34)
Pc = Pc,sub + Pc,H .
(38)
B. Switching Losses
The switching losses are calculated for a typical switch, and
then, the results are extended for the proposed multilevel inverter. For this calculation, the linear approximation of the voltage and current during switching period is used. Using this approximation, energy loss during the turn-off period of a switch
can be obtained as follows:
Eo ,k
to f f
=
v(t)i(t)dt =
0
1
Vsw ,k I to
6
to f f
Vsw ,k
I
t
(t to ) dt
to
to
(39)
Fig. 5. (a) Number of IGBTs and (b) number of driver circuits versus number
of levels for the symmetric topologies.
631
Fig. 6. Standing voltage on the switches versus number of levels for the
symmetric topologies.
where Eo ,k is the turn-off loss of the switch k, to is the turnoff time of the switch, I is the current through the switch before
turning OFF, and Vsw ,k is the off-state voltage on the switch.
The turn-on loss of the switch can be calculated as follows:
to n
Eon,k =
v(t)i(t)dt
0
to n
=
0
Vsw ,k
t
ton
I
(t ton ) dt
ton
Fig. 7. (a) Per-unit conduction power loss and (b) per-unit switching power
loss versus number of levels for the symmetric topologies (R T = 0.15 , V T =
2.5 V, R D = 0.1 , V D = 1.5 V, n = 3, to n = to = 2 s).
1
= Vsw ,k I ton
(40)
6
where Eon,k is the turn-on loss of the switch k, ton is the turn-on
time of the switch, and I is the current through the switch after
turning ON.
The switching losses depend on the number of switching
transitions. Therefore, it depends on the modulation method.
Generally, the average switching power loss can be written as
follows:
Non ,k
No ff , k
N
sw itch
Eon,k i +
Eo ,k i (41)
Psw = 2f
i=1
k =1
i=1
(42)
632
Fig. 11.
Fig. 8. Number of IGBTs versus the number of output voltage level in the
submultilevel inverters.
Fig. 9. Standing voltage on the switches versus the number of output voltage
level in the submultilevel inverters.
Fig. 10.
B. Asymmetric Topology
The proposed topology in this paper is compared with the
topologies presented in [12] and [13] and the asymmetric CHB
topology. Initially, the proposed submultilevel inverter (see
Fig. 1) is compared with the submultilevel inverters proposed
in [12] and [13]. It is noticeable that the submultilevel inverter
is called as basic unit in [12] and [13]. The number of IGBTs
versus the number of voltage levels is shown in Fig. 8 for the
proposed submultilevel inverter and the basic units presented
in [12] and [13]. As shown in Fig. 8, the proposed submultilevel inverter uses lower number of IGBTs in comparison with
the others. Fig. 9 shows the sum of the standing voltage on the
switches for the submultilevel inverters. As shown in the figure,
the proposed submultilevel inverter has a better condition from
the viewpoint of standing voltage on the switches.
In the previous comparison, the submultilevel inverters have
been compared together. Here, the aim is to compare the multilevel inverters resulted from series connection of the submultilevel inverters. For the comparison purpose, the required number
of IGBTs for each number of output voltage levels is depicted
in Fig. 10. It can be seen from this figure that the proposed
topology uses a considerable lower number of IGBTs for any
specific number of output voltage level in comparison with the
topologies presented in [12] and [13] and the asymmetric CHB
topology. For the topology presented in [13], the optimal topology derived in [19] is used for comparison.
Fig. 12. (a) Per-unit conduction losses and (b) per-unit switching losses for
the proposed asymmetric topology and the asymmetric CHB topology (R T =
0.15 , V T = 2.5 V, R D = 0.1 , V D = 1.5 V, n = 1, to n = to = 2 s).
633
TABLE II
TYPICAL IGBTS IN DIFFERENT VOLTAGE RATINGS
Fig. 13.
(43)
Vrated =
2
634
operates as a low-pass filter for the current. The load current has
also phase difference with the load voltage because of inductive
characteristic of the load.
Fig. 15.
B. Asymmetric Topology
commercially. This will make the mentioned topologies suitable
for medium-voltage applications.
VI. SIMULATION AND EXPERIMENTAL RESULTS
This section deals with the simulation and experimental validation of the proposed multilevel inverter topology. For the proposed symmetric multilevel inverter, only the simulation results
are presented, but, for the asymmetric topology both simulation
and experimental results are given.
For all of the studies, the load is an RL load with the value
of 45 and 55 mH. The output voltage frequency is assumed
50 Hz.
There are many control methods for multilevel inverter. It is
noticeable that the staircase control method is used in this paper [1]. The term staircase control method is used to state that in
this method, transition from one level of voltage to the next level
happens once as shown in Fig. 15 (for example). This control
method tends to generate a staircase voltage which minimizes
the error with respect to the reference voltage. It is worth noting
that the calculation of optimal switching angles for different
goals, such as elimination of the selected harmonics and minimizing total harmonic distortion (THD), is not the objective of
this paper.
A. Symmetric Topology
Fig. 14 shows the 13-level inverter based on the proposed
symmetric multilevel inverter with n = 3. Six dc voltage sources
each of them 100 V have been used so that the maximum output
voltage will be 600 V. The number of IGBTs for a 13-level
inverter in the proposed topology is 16. For the same number
of voltage levels, the topology of [15] and CHB use 19 and 24
IGBTs, respectively, which are higher than that of the proposed
topology.
Fig. 15 shows the load voltage and scaled load current of
the 13-level inverter. As the figure shows, all of the expected
voltage levels are generated at the output voltage. The load
voltage is sine-waved current as a result of the RL load which
635
Fig. 19. Experimental results. From top to bottom, the traces are output voltage
of cascaded submultilevel inverters, load voltage, and load current.
Fig. 17. Output voltage of each submultilevel inverter: from top to bottom
traces are first, second, third, and fourth submultilevel inverter output voltage,
respectively.
636
factors dictate that the number of dc voltage sources per submultilevel inverter should be 1. The comparison between the
proposed topology and the topologies presented in [12], [13],
and [15] and the CHB topologies has been presented considering
several factors. The simulation results of a 13-level symmetric
topology based on the proposed multilevel inverter have been
presented. In the case of asymmetric topology, the simulation
and experimental results have been presented for a 31-level inverter based on the proposed optimal structure to validate the
ability of the proposed topology in generating of desired output
voltage.
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