Modeling and Design of a Low-Voltage SOI Suspended-Gate MOSFET

(SG-MOSFET) with a Metal-Over-Gate Architecture

Adrian M. Ionescu1, Vincent Pott1,2, Raphael Fritschi1,2, Kaustav Banerjee3,
Michel J. Declercq1, Philippe Renaud2, Cyrille Hibert2, Philippe Fluckiger2, Georges A. Racine2
1

Electronics Laboratories (LEG), Swiss Federal Institute of Technology Lausanne, Switzerland

Center of Microtechnology (CMI), Swiss Federal Institute of Technology Lausanne, Switzerland
3
Center of Integrated Systems, Stanford University, Stanford, CA, USA
E-mail: Adrian.Ionescu@epfl.ch

Abstract
A novel MEMS device architecture: the SOI SGMOSFET, which combines a solid-state MOS
transistor and a suspended metal membrane in a
unique metal-over-gate architecture, is proposed. A
unified physical analytical model (weak, moderate
and strong inversions) is developed and used to
investigate main electrostatic characteristics in order
to provide first-order design criteria for low-voltage
operation and high-performance. It is demonstrated
that the use of a thin gate oxide (<20nm) is essential
for a high Con/Coff ratio (>100) and a low spring
constant (<100N/m) is needed for low voltage (<5V)
actuation. An adapted fabrication process is reported.

1. Introduction
The MEMS platform has attracted special
attention for RF ICs, especially wireless, because of
its gain in terms of: device and system
miniaturization, CMOS-compatibility, power savings,
higher
performances
and,
especially,
new
functionality, such as re-configurable circuit
architectures in which RF switches could program
signal coupling to interconnect lines and passive
components are programmable and/or tunable [1-10].
The basic building block of RF MEMS circuits is the
RF-MEMS switch, which plays a similar role to the
MOS switch in a standard RF system. RF MEMS
devices have several clear advantages over their solidstate counterparts (FETs and diodes): lower series
resistances, low power operation and negligible intermodulation distortion, [2-4].
This paper reports on the physical and analytical
modeling and the design of a novel MEMS-device
architecture, called the suspended-gate (SG)
MOSFET, which combines in a single cell a
MOSFET and a MEMS switch with a metal-over-gate
architecture. An adapted new technological process is
proposed, involving the use of polysilicon or
amorphous silicon as sacrificial layers. It is
demonstrated that the SG-MOSFET has some unique
electrical characteristics and is particularly adapted
for low-voltage MEMS contact-less switches (with
better performances for programmable interconnects
than FPGA) and, furthermore, for high-Q tunable
MEMS capacitors.

2. SG-MOS architecture and principle

The cross section and the principle of the SOI
SG-MOSFET are depicted in Fig. 1: it combines in a
top-down architecture a metal membrane MEMS
switch and a partially depleted (PD) SOI MOSFET. A
typical device design inspired by RF MEMS
membrane switches, including suspension arms, is
given in Fig. 2 that also shows its 3-D simulated
actuation under an uniformly distributed force, [11].
When the front gate voltage, Vg1 (simply denoted by
Vg), is increased, the intrinsic gate-voltage, Vgint
(=Vgint1), which drives the MOS channel formation, is
tuned according to a capacitor divider:
Vg
(1)
Vg int =
1 + C gc int / C gap
where Cgcint, Cgap are the intrinsic gate-to-channel
capacitance of the underneath MOSFET and the airgap capacitance, respectively. Note that in the
following analysis the back gate (Vg2) and the body
(Vb) of the PD SOI MOSFET are considered
grounded. The gate membrane moves continuously
downwards as long as the equilibrium is maintained
between electrostatic and elastic forces:
2
1 air A ( Vg Vg int )
Felastic = kx =
= Felectr (2)
2
( t gap 0 x ) 2
where x is the gate displacement, tgap0 the initial airgap dimension and Vgint the intrinsic gate voltage.
When Vg equals the pull-in voltage, Vpi, unstable
equilibrium is reached and the switch (suspended
membrane) moves from the off to the on state
(tgap=0). It is worth noting that in metal-metal plate
capacitors, Vpi is a well-known non-linear function of:
the initial air-gap, (tgap0-tox), the membrane area, A,
and the spring effective elastic constant, k. Unstable
equilibrium condition is reached at x=tgap0/3, which is
a limiting factor for the tuning range of MEMS
capacitors. It is can be demonstrated that the use of an
MOS capacitor connected in series (like in the case of
SG-MOSFET architecture), underneath the suspended
metal membrane, can slightly extend the equilibrium
region beyond tgap0/3 [3] and the well known Vpi
formulation of the metal-metal switch:

Proceedings of the International Symposium on Quality Electronic Design (ISQED02)

0-7695-1561-4/02 $17.00 2002 IEEE

8k
(3)
t 3gap 0
27 0 Ww
where W and w are the membrane and underneath
metal line widths, respectively, is no longer adapted,
depending also on the value of the series capacitor.
Note that the SG-MOSFET architecture has not any
underneath metal line and, for simple analogy, it can
be considered that the inversion layer of the MOSFET
plays the role of the underneath metal line of a metalmetal RF MEMS capacitive switch.
Vpi =

Suspended
(movable)
metal gate

Vg1=Vg

Equivalent
spring

C gc int (Vg int ) =

C ox C inv
=
C ox + C inv + C d

[
2 exp[(V

]
]+ 1

( 1) / 2 exp (Vg int (Vg ) Vfb 2 F ) / Vth C ox

( 1) /

g int

(Vg ) Vfb 2 F ) / Vth

(4)
where Cox, Cinv and Cd are the oxide, inversion and
depletion capacitances, respectively, =1+Cd/Cox,
Vth=kT/q is the thermal voltage, and the other
parameters are standard for MOSFET devices. This
simple continuous formulation allows the compact
integration of the inversion charge as a function of the
SG-MOSFET intrinsic voltage Vgint:
Vg int

Q inv (Vg int ) =

gc

(Vg int )dVg int =

source

tgap

n+

drain

tox

n+

Vgint
Vd

Vs

Buried oxide

Vg2 Vb

Si substrate
Back gate

Inversion
layer

(a)
(b)
Fig. 1 (a) Cross section of n-channel SOI SGMOSFET and (b) simplified electrical equivalent
schematic.
Gate (Al) membrane
Hinge
n+
W
L

n+

Fig. 2 3-D numerical simulation with SOLIDIS [11]

of the deflection of a SG-MOSFET metal membrane
(100x100 m2) under uniformly distributed force of
1000Pa. The suspension hinge design (number of
meanders) determines the equivalent elastic
coefficient, k.

3. SG-MOSFET unified DC model

In order investigation, a long channel, partially
depleted (PD) SOI MOSFET (for which Si-bulk
MOSFET models stand) is considered. The following
physical unified expression of the gate-to-channel
capacitance, Cgc, available for weak, moderate and
strong inversions (with source, drain and back gate
supposed grounded for simpler analytical equations)
is proposed:

2 1
Vg int (Vg ) Vfb 2 F
+ 1
= C ox Vth ln
exp

Vth
2

(5)
Eq. (5) is then used to derive the SG-MOSFET drain
current at low voltage (quasi-linear regime) in both
on and off states of the switch. The proposed
analytical model is able to capture some unique
characteristics of the SG-MOSFET in a single,
unified analytical expression:
(i) the dynamic threshold voltage: low in the on
state and high in the off state, which is a key
advantage for RF switch use because of a higher
isolation in the off state compared to the solid
state MOSFET,
(ii) the super-exponential dependence of Qinv on Vg
in the subthreshold region,
(iii) the super-linear dependence of Qinv on Vg in
both moderate and strong inversions.
It is worth noting that in strong inversion, eq. (5)
becomes similar to the well-known formulation of the
inversion charge:
(6)
Q inv ( Vg ) = C ox ( Vg int ( Vg ) VT )
where VT=Vfb+2F is the intrinsic threshold voltage
and because Vgint is a non-linear function of Vg
through eq. (1), it follows that the SG-MOSFET has a
specific super-linear dependence of Qinv with respect
to the gate voltage, Vg.

4. Design-Of-Experiment
model predictions

(DOE)

and

Based on the new proposed analytical

formulation, calibrated by static 3-D electromechanical numerical simulation, various SG-MOS
architectures with a metal-over-gate (Al) architecture
and thin oxide (5-50nm) have been investigated.
The aim of our DOE was to identify an
acceptable design window for a low voltage DC
actuation (CMOS compatible), with acceptably small
gate area. As a first approximation, we have observed
that using the SG-MOSFET for RF switch
applications needs a low-loss (high resistivity or SOI)

Proceedings of the International Symposium on Quality Electronic Design (ISQED02)

0-7695-1561-4/02 $17.00 2002 IEEE

10

substrate and air-gaps in excess of 0.2m (for better

isolation when the switch is not actuated).

gate pulled-in:
Vg = Vgint
1.2

Vgint (V)

k(N/m)=100, A=WxL(mxm)=100x100, tox (nm)=10

1.0

tgap0+tox(m) = 1

tox(nm)= 50
1

tgap ( m)

0.8
0.6

k(N/m)=100
A=WxL(
mx
m)=100x100
tgap0 +tox (
m)=0.2

0.5

0.4

0.1
0.10

0.2

0.2

Vpi

0.1
0.05

0
0.10

1.00

10.00

1.00

10.00

Vg (V)

100.00

Vg (V)

Fig. 7 Intrinsic (internal) gate voltage, Vgint, vs.

extrinsic gate voltage, Vg, with the oxide thickness,
tox, as a parameter.

Fig. 3 SG-MOSFET actuation for various tgap0.

0.2

tgap ( m)

0.15

k(N/m)=
500

10 20 50 100 200

0.10

tox(nm)
=10
A=WxL
(mxm)
=100x100
t gap0(m)
=0.19

0.05

0
0

Vg (V)

Fig. 4 SG-MOSFET actuation for various k.

0.2
k(N/m)=100
tox(nm)=10
tgap0( m)
=0.19

tgap ( m)

0.15

200x200
100x100

0.10

50x50

A=W xL
(mxm)
=10x10

20x20

0.05

0
0.0

5.0

10.0
Vg (V)

15.0

20.0

Fig. 5 SG-MOSFET actuation for various A.

0.2

10

tox(nm)=
5

20

0.15

tgap ( m)

50
0.1

0.05
k(N/m)=100
A=WxL(mxm)=100x100
tgap0(m)=0.2
0
0.0

1.0

2.0

3.0

Vg (V)

Fig. 6 SG-MOSFET actuation for various tox.

Figs. 3, 4, 5 and 6 depict typical calculated SGMOSFET gate electrostatic actuations for various: (i)
initial air-gap, tgap0 (Fig. 3), (ii) spring constant, k
(Fig. 4), (iii) gate area, A=WxL (Fig. 5) and (iv)
oxide thickness (Fig. 6).
Systematic calculations based on the proposed
model suggest that a combination of spring constant
less than 100N/m (possible by an adapted, meanderlike, design of the gate hinges, Fig. 2), air-gap less
than 0.5m and area larger than 20x20m2, define a
preliminary SG-MOSFET low-voltage (Vpi<5V)
window design. It is found that the gate oxide
thickness has no great impact on the pull-in voltage
value. This is also confirmed in Fig. 7, where the
internal gate voltage, Vgint, is plotted against the SGMOSFET external gate voltage, Vg. It should be
noted that the typical switching speed between off
and on states is estimated to be of the order of 10 to
100s (being dictated by the membrane pull-down
time, as for the metal-metal RF switches).
Another interesting result is suggested by Fig. 8 a
and b, where the evolution of the SG-MOSFET
surface potential, S, is plotted for various parameters
of the device architectures. It is found that the
membrane always snaps down in moderate inversion,
near the onset of strong inversion, which is a very
unique characteristic. This result is in good agreement
with [3] that reported on the non-equilibrium of a
similar device associated with strong inversion.
Moreover, this result highlights the usefulness of a
unified analytical model including all regimes of
MOS inversions (weak, moderate and strong).
A key parameter for a RF switch is the ratio
between its capacitance in off and on states that
should be larger than 100 [1, 2]. Typical SGMOSFET switching capacitance characteristics are
reported in Fig. 9 a and b. It is clearly demonstrated
that a Con/Coff ratio in excess of 100 can be obtained
by the use of a reasonably thin oxide (tox<10-20nm)
instead of a large initial gap. This is a very useful and
original finding for the device design since in the lowvoltage analysis it was shown that tox does not
significantly impact the pull-in voltage value.

Proceedings of the International Symposium on Quality Electronic Design (ISQED02)

0-7695-1561-4/02 $17.00 2002 IEEE

1.2

The SG-MOSFET inversion charge, Qinv(Vg),

derived from eq. (6) is plotted in Fig. 10. It can be
observed that there are more than five orders of
magnitude difference between inversion charge in
on and off states (switch pulled-down and up). It
follows that the device works as a combination of a
solid-state MOSFET and a micromechanical switch
and can also be useful for microrelay (or current
switch) applications. The device drain current and
transconductance at low VD (=50mV) are reported in
Figs. 11, 12 and 13. Typically, the switching occurs
prior to the onset of strong inversion (in moderate
inversion) and the drain current has a slight superlinear dependence on the extrinsic gate voltage Vg.
It is worth noting that in the subthreshold region
(weak inversion), because of the action of the
capacitor divider described by eq. (1), the SGMOSFET can theoretically exhibit a local
subthreshold slope better than the ideal limit for a
solid-state bulk or SOI MOSFET (60mV/decade).
However, as already mentioned, the device
commutation speed is essentially limited by the
electromechanical displacement of the suspended gate
membrane.

Suspended gate pulled down: t gap=0

1

S (V)

0.8

2F
t ox (nm) = 5

0.6

10

20
50

0.4

16

0.2

Suspended gate
in equilibrium (up)

0
0.00

1.00

-3

NA =10 cm
k(N/m)=100
A=WxL(mxm)=100x100
t gap0(m)=0.2

2.00

3.00

4.00

5.00

Vg (V)

(a)
1.00

k(N/m )=
10

0.80

20 50 100 200

500

S (V)

2 F
0.60

t ox(nm)=10, t gap0(mm)=0.19
A=WxL(mxm)=100x100

0.40

NA =10 16cm-3
0.20
0

Vg (V)

(b)
Fig. 8 SG-MOSFET surface potential, S, versus Vg.
tox (nm) = 5
20

-3

50
2

Cgc (F/m )

10

-2

10

-3

-2

10
10

-1

gate membrane pulled-down

Q inv ( C/m 2 )

10

10

Switch ON: Cgc =HIGH

10

-4

10

-5

10

-6

10

-7

Switch OFF:
Cgc = LOW
k(N/m)=100
A=WxL(mxm)=100x100
tgap0 +tox(m)=0.20

10

-4

10 20 50 100 200
10

-5

10

-6

10

-7

tox(nm)=10, tgap0(
m)=0.19
gate membrane
mx
m)=100x100
in equilibrium (up) A=WxL(
0

Vg (V)

k(N/m)=
500

Vg (V)

Fig. 10 SG-MOSFET inversion charge, Qinv, vs. gate

voltage, Vg, with k, as a parameter.

(a)
10-4

Switch down

10-2

~Cox

ON

-5

10

10-6
10-3

k(N/m)=
500

10 20 50 100 200

10-4

Id ( A )

C gc ( F/m )

10-7

k(N/m)=
500

10 20 50 100 200
10-8
-9

10
10

Switch up (equilibrium)

OFF

10-10

-5

t ox (nm)=10, tgap0 +tox (

m)=0.2
A=WxL(
mx
m)=100x100

Subthreshold

10-11
-12

tox(nm)=10, tgap0+tox(
m)=0.20
A=WxL(
mx
m)=100x100

10

10-6

Vg (V)

(b)
Fig. 9 SG-MOSFET extrinsic capacitance, Cgc, vs.
gate voltage, Vg: a) tox as a parameter; Con/Coff >100 is
obtained for tox<10-20nm and b) k as a parameter.

Vg (V )

Fig. 11 SG-MOSFET drain current, ID, vs. gate

voltage, Vg, (in log-lin scale) at low drain voltage,
VD=50mV, with k as a parameter.

Proceedings of the International Symposium on Quality Electronic Design (ISQED02)

0-7695-1561-4/02 $17.00 2002 IEEE

25

Vg
k(N/m)=
10 20 50 100 200

20

500

Cstab

Id ( nA )

Vgsg
15

Cgap

Vgint

10

Cinv

m)=0.2
tox(nm)=10, tgap0+tox(
A=WxL(
mx
m)=100x100

V D=50mV

Cox

supe r-line ar
de pe nde nce

Cd

Vg (V)

Fig. 12 SG-MOSFET drain current, ID, vs. gate

voltage, Vg, (in lin-lin scale), at low drain voltage,
VD=50mV, with k as parameter. Inset, the specific
super-linear dependence in moderate inversion, prior
to the gate snap-down, is highlighted.

Fig. 14 Electrical equivalent circuit of the stabilized

SG-MOSFET, including a series capacitance, Cstab.
0.2
10
0.15

C stab(pF)=
0.5

k(N/m)=
10 20 50 100 200

g m =dI d /dV g( nS )

15

tg ap ( m)

20

500

Equilibrium

0.1

0.05
10

0
0

10

V g (V)

V D=50mV

Vg (V)

Fig. 13 Transconductance, gm, vs. gate voltage, Vg,

derived from data in Fig. 12.

5. Equilibrium and capacitor tuning

range
One key concern for the use of the SG-MOSFET
architecture as a tunable RF capacitor is its limited
tuning range (around 50%) because of the snap-down
event near 1/3 of the gap. A significant increase of the
tuning range can be essentially provided by the
extension of the equilibrium via the series connection
of a constant value high-Q capacitor (Fig. 14). The
series capacitor can be smartly integrated in the
MEMS device by the use of one extra-metal layer; the
movable gate is made of a metal-insulator-metal
sandwiched architecture, instead of a single metal.
The intrinsic gate voltage, Vgint, is now:

Vg int =
1+

Vg
C gc (C stab + C gap )

Fig. 15 Effect of a series capacitance, Cstab, on the

gate displacement and extension of the SG-MOSFET
equilibrium region. The device parameters are:
A=200x200m2, tgap0=0.2m, tox=10nm, k=100N/m.

6. SPICE modeling
Table 1 shows the mechanical-to-electrical
analogy that allows building a SG-MOSFET DC
macro-model for fast simulation with SPICE. The
specific electrostatic displacement of the suspended
gate can be modeled by using an empirical
polynomial
voltage-controlled
source,
f(VG),
combined with a conventional MOSFET model, as
shown in Fig. 16. A second voltage source can be
added in order to model some hysteresis effects
linked with charge trapping in the gate oxide. The
passive elements, R and L, mirror the damping and
the inertia (mass) of the SG-MOSFET membrane and
are relevant especially for the membrane dynamics
(transients) and AC investigations.

(7)

(C stab C gap )

In Fig. 15 the impact of various values of the series

capacitance on the device stabilization is shown. It
appears that a trade-off should be considered among
the tuning range (extension of the stable region) and
the low voltage actuation.

Proceedings of the International Symposium on Quality Electronic Design (ISQED02)

0-7695-1561-4/02 $17.00 2002 IEEE

Table 1: Mechanical-to-Electrical Analogy

Mechanical
Electrical
Variable
Variable
Damping, c
Resistance, R
Stiffness-1, k-1
Capacitance, C
Mass, m
Inductance, L
Force, F
Voltage, V
Velocity, v
Current, I

Vg
R
k
c
F

m
f(Vg)
n+

n+

Vs

+
_
Vd

Vb
Fig. 16 Equivalent electrical SPICE model of the
SG-MOSFET according to the mechanical-toelectrical analogy reported in Table 1.

(a)

Polycrystalline silicon is here the sacrificial layer. An

alternative to this process consists of the use of
amorphous silicon (a-Si) instead polycrystalline
silicon. Amorphous silicon is also expected to
improve the underneath roughness of the released
metal membrane. The new releasing techniques are
combined with an adapted design of a metal-over-gate
architecture, the suspended gate being made of Al or
AlSi. In Fig. 17, SEM micrographs of fully suspended
AlSi membranes, released with the dry SF6 process
and using a-Si, which becomes the sacrificial layer,
are reported.

8. Conclusion
A novel MEMS device architecture: the SOI SGMOSFET, which combines a solid-state MOS
transistor and a suspended metal membrane, in a
metal-over-gate architecture, was proposed. A unified
physical analytical model was developed and used to
predict main electrostatic characteristics and provide
first-order design criteria for CMOS-compatible, lowvoltage actuated RF switches. Main DC
characteristics for both capacitive switch and
microrelay applications are addressed. It is shown that
controlling the thickness of the gate oxide (<20nm) is
essential for a high Con/Coff ratio (>100) and a low
spring constant (<100N/m), provided by special
meander-like hinge design, is needed for <5V
actuation. Other key results concern the specific
super-exponential and super-linear drain current
dependence on the gate voltage, at low drain voltage,
the possibility to obtain a subthreshold slope better
than the theoretical solid-state bulk/SOI MOSFET
limit and equilibrium extension solutions.

References
1.

(b)
Fig. 17 a) and b) AlSi membranes released using the dry
SF6 etching of sacrificial amorphous silicon (images with
different magnification factors).

7. Fabrication process
State-of-the-art fabrication processes for RF
MEMS switches and tunable capacitors [4-10] use
surface micromachining to release the movable metal
membranes. Some typical sacrificial layers are SiO2,
polymers and/or similar insulators.
This work reports on a new CMOS-compatible
MEMS-process, specially designed to provide SGMOSFET architectures on SOI or bulk silicon
substrates. The novelty of the process consists of the
SF6 dry etching of polycrystalline silicon for the
release of the suspended SG-MOSFET metal gate.

E.R. Brown, IEEE Trans. On Microwave Theory and

Techniques, vol. 46 (1998) p. 1868.
2. C.L. Goldsmith and S. Eshelman, IEEE Microwave
and Guid. Wave Letts., vol. 8 (1998) p. 269.
3. J. Seeger and S. Crary, Proc. of 1997 Int. Conf. on
Solid-State Sensors and. Actuators (1997) p. 1133.
4. J. Zhuo, C. Liu, J. Schutt-Aine, J. Chen and S.-M.
Kang, Proc. of IEDM 2000 (2000) p. 403.
5. Z. Yao, S. Chen, S. Eshelman, D. Dennison and C.
Goldsmith, IEEE Journal of MEMS, vol. 8 (1999)
p.129.
6. J.J. Yao and M.F. Chang, Proc. of 8th Int. Conf. on
Solid-State Sensors and Actuators, Eurosensors IX
(1995) p. 384.
7. S. Pacheco, C.T. Nguyen, L. Katehi, Proc. of IEEE
MTT-S International Microwave Symp., Baltimore,
Maryland (1998) p.1569.
8. C.T. Nguyen, Proc. of SPIE, Santa Clara, California
(1998) p. 24.
9. C.T. Nguyen, L. Katehi, G. Rebeiz, Proc. of IEEE, vol.
86 (1999) p. 1756.
10. S. Duffy, C. Bozler, S. Rabe, J. Knecht, L. Travis, P.
Wyatt, C. Keast, M. Gouker, IEEE Microwave and
Wireless Letts., vol. 11 (2001) p.106.
11. SOLIDIS ISE, Reference manual, 2000.

Proceedings of the International Symposium on Quality Electronic Design (ISQED02)

0-7695-1561-4/02 $17.00 2002 IEEE