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University of Technology
Electrical Eng. Department
Microprocessor Engineering &
Microcontroller
What is a Computer?
A computer is an electronic machine that accepts information, stores it until
the information is needed, processes the information according to the instructions
provided by the user, and finally returns the results to the user. The computer can
store and manipulate large quantities of data at very high speed, but a computer
cannot think. A computer makes decisions based on simple comparisons such as
one number being larger than another. Although the computer can help solve a
tremendous variety of problems, it is simply a machine. It cannot solve problems
on its own.
Computer Generations
From the 1950s, the computer age took off in full force. The years since
then have been divided into periods or generations based on the technology used.
1. First Generation Computers (1945-1954): Vacuum Tubes
The first computers used vacuum tubes for circuitry and magnetic drums for
memory, and were often enormous, taking up entire rooms. They were very expensive to
operate and in addition to using a great deal of electricity, generated a lot of heat, which
was often the cause of malfunctions.
First generation computers relied on machine language, the lowest-level
programming language understood by computers, to perform operations, and they could
only solve one problem at a time. Input was based on punched cards and paper tape,
and output was displayed on printouts.
Page 1 of 27
Lecture One
Introduction to Computer &
Microcomputers
Assist.Prof. Dr. Hadeel Nasrat
University of Technology
Electrical Eng. Department
Microprocessor Engineering &
Microcontroller
Page 2 of 27
Lecture One
Introduction to Computer &
Microcomputers
Assist.Prof. Dr. Hadeel Nasrat
University of Technology
Electrical Eng. Department
Microprocessor Engineering &
Microcontroller
Page 3 of 27
Lecture One
Introduction to Computer &
Microcomputers
Assist.Prof. Dr. Hadeel Nasrat
University of Technology
Electrical Eng. Department
Microprocessor Engineering &
Microcontroller
Software &
Applications
Generation
First
(1945-54)
Second
(1955-64)
Third
(1965-71)
Integrated circuits,
Microprogramming, Pipelining,
Caching, Lookahead Processing
Fourth
(1971Present)
Fifth
(present &
Beyond)
Multiprocessor OS,
languages, Compilers
parallel processing,
Systems
superconductors,
voice recognition
Applications
ENIAC TIFRAC
IBM 701 Princeton
IAS
IBM7099
CDC 1604
Types of Computers
Computer now comes in a variety of shapes and sizes, which could be roughly
classified according to their processing power into five sizes:
Lecture One
Introduction to Computer &
Microcomputers
Assist.Prof. Dr. Hadeel Nasrat
University of Technology
Electrical Eng. Department
Microprocessor Engineering &
Microcontroller
computers:
The
only
type
of
computer
available until the late 1960s, mainframes are water- or air-cooled computers that
vary in size from small, to medium, to large, depending on their use. Small
mainframes are often called midsize computers;
midsize mainframes, workstations are used for such tasks as designing airplane
fuselages, prescription drugs, and movie special effects. Workstations have
caught the eye of the public mainly for their graphics capabilities, which are used
to breathe three-dimensional life into movies such as Jurassic Park and Titanic.
The capabilities of low-end workstations overlap those of high-end desktop
microcomputers.
Microcomputer - small computers: Microcomputers, also called personal
computers (PC), can fit next to a desk or on a desktop, or can be carried around.
They are either stand-alone machines or are connected to a computer network,
such as a local area network. A local area network (LAN) connects, usually by
special cable, a group of desktop PCs and other devices, such as printers, in an
office or a building. Microcomputers are of several types:
Desktop PCs:
often on the floor beside a desk, thus freeing up desk surface space.
Laptop computers (also called notebook computers): are lightweight portable
computers with built-in monitor, keyboard, hard-disk drive, battery, and AC
Page 5 of 27
Lecture One
Introduction to Computer &
Microcomputers
Assist.Prof. Dr. Hadeel Nasrat
University of Technology
Electrical Eng. Department
Microprocessor Engineering &
Microcontroller
adapter that can be plugged into an electrical outlet; they weigh anywhere from
1.8 to 9 pounds.
Personal digital assistants (PDAs) (also called handheld computers or
palmtops) combine personal organization tools-schedule planners, address
books, to-do lists. Some are able to send e-mail and faxes. Some PDAs have
touch-sensitive screens. Some also connect to desktop computers for sending
or receiving information.
Microcontrollers-tiny computers: Microcontrollers, also called embedded
computers, are the tiny, specialized microprocessors installed in "smart"
appliances and automobiles. These microcontrollers enable PDAs microwave
ovens, for example, to store data about how long to cook your potatoes and at
what temperature.
Basic Blocks of a Microcomputer
All Microcomputers consist of (at least):
1. Microprocessor Unit (MPU) MPU is the brain of microcomputer
2. Program Memory (ROM)
3. Data Memory (RAM)
4. Input / Output ports
5. Bus System
Lecture One
Introduction to Computer &
Microcomputers
Assist.Prof. Dr. Hadeel Nasrat
University of Technology
Electrical Eng. Department
Microprocessor Engineering &
Microcontroller
ADDRESS BUS
DATA BUS
CONTROL BUS
Data Bus
The data bus consists of 8, 16, or 32 parallel signal lines. As indicated by the
double-ended arrows on the data bus line in Figure 1, the data bus lines are
bidirectional. This means that the CPU can read data in from memory or from a
port on these lines, or it can send data out to memory or to a port on these lines.
Many devices in a system will have their outputs connected to the data bus, but
only one device at a time will have its outputs enabled. Any device connected on
the data bus must have three-state outputs so that its outputs can be disabled
Page 7 of 27
Lecture One
Introduction to Computer &
Microcomputers
Assist.Prof. Dr. Hadeel Nasrat
University of Technology
Electrical Eng. Department
Microprocessor Engineering &
Microcontroller
Control Bus
The control bus consists of 4 to 10 parallel signal lines. The CPU sends out
signals on the control bus to enable the outputs of addressed memory devices or
port devices. Typical control bus signals are Memory Read, Memory Write, I/O
Read, and l/O Write. To read a byte of data from a memory location, for example,
Page 8 of 27
Lecture One
Introduction to Computer &
Microcomputers
Assist.Prof. Dr. Hadeel Nasrat
University of Technology
Electrical Eng. Department
Microprocessor Engineering &
Microcontroller
the CPU sends out the memory address of the desired byte on the address bus and
then sends out a Memory Read signal on the control bus. The Memory Read signal
enables the addressed memory device to output a data word onto the data bus. The
data word from memory travels along the data bus to the CPU.
The Control Bus: is another group of signals whose functions are to provide
synchronization ( timing control ) between the MPU and the other system
components.
Control signals are unidirectional, and are mainly outputs from the MPU.
Example Control signals
RD: read signal asserted to read data into MPU
WR: write signal asserted to write data from MPU
Main memory
The memory section usually consists of a mixture of RAM (Random Access
Memory) and ROM (Read Only Memory). It may also have magnetic floppy disks,
magnetic hard disks, or optical disks (CDs, DVDs). Memory has two purposes. The
first purpose is to store the binary codes for the sequences of instructions you want
the computer to carry out. When you write a computer program, what you are really
doing is writing a sequential list of instructions for the computer. The second purpose
of the memory is to store the binary-coded data with which the computer is going to
be working. This data might be the inventory records of a supermarket, for example.
The duties of the memory are :
To store programs
To provide data to the MPU on request
To accept result from the MPU for storage
Main memory Types
ROM : read only memory. Contains program (Firmware). does not lose
its contents when power is removed (Non-volatile)
RAM: random access memory (read/write memory) used as variable
data, loses contents when power is removed volatile. When power up
will contain random data values
Page 9 of 27
Lecture One
Introduction to Computer &
Microcomputers
Assist.Prof. Dr. Hadeel Nasrat
University of Technology
Electrical Eng. Department
Microprocessor Engineering &
Microcontroller
Read-Only Memory
uP can read instructions from ROM quickly
Cannot write new data to the ROM
ROM remembers the data, even after power cycled
Typically, when the power is turned on, the microprocessor will start fetching
instructions from the still-remembered program in ROM (bootstrap )
Available ROMs
Masked ROM or just ROM
PROM or programmable ROM(once only)
EPROM (erasable via ultraviolet light)
Flash (can be erased and re-written about 10000 times, usually must write a
whole block not just 1 byte or 2 bytes, slow writing, fast reading)
EEPROM (electrically erasable read-only memory, also known as EEROM
both reading and writing are very slow but can program millions of
timesuseless for storing a program but good for say configuration
information.
A0
A1
ROM
m+1 bit
Addres
D0
D1
A2
m +1
D2
(n + 1)
Am
Dn
ROM
PROM
EEPROM
Capacity: 2m+1
( )
Page 10 of 27
OE
n+1
bit
bit
Data
Lecture One
Introduction to Computer &
Microcomputers
Assist.Prof. Dr. Hadeel Nasrat
University of Technology
Electrical Eng. Department
Microprocessor Engineering &
Microcontroller
m+1 bit
Address
A0
A1
D0
D1
A2
D2
2
m +1
(n + 1)
Am
Capacity: 2m+1
n+1 bit
Data
Dn
Data bus is
Bidirectional
RAM
WR
RD
Page 11 of 27
Lecture One
Introduction to Computer &
Microcomputers
Assist.Prof. Dr. Hadeel Nasrat
University of Technology
Electrical Eng. Department
Microprocessor Engineering &
Microcontroller
from memory, decodes the instructions into a series of simple actions, and carries out
these actions in a sequence of steps. The CPU also contains an address counter or
instruction pointer register, which holds the address of the next instruction or data
item to be fetched from memory; general-purpose registers, which are used for
temporary storage of binary data; and circuitry, which generates the control bus
signals.
Computer Architecture
In computer engineering, computer architecture is the conceptual design and
fundamental operational structure of a computer system. It is a blueprint and functional
description of requirements (especially speeds and interconnections) and design
implementations for the various parts of a computer focusing largely on the way by
which the central processing unit (CPU) performs internally and accesses addresses in
memory.
Computer architecture comprises at least three main subcategories
Instruction set architecture, or ISA, is the abstract image of a computing
system that is seen by a machine language (or assembly language) programmer,
including the instruction set, memory address modes, processor registers, and
address and data formats.
Microarchitecture, also known as Computer organization is a lower level, more
concrete, description of the system that involves how the constituent parts of the
system are interconnected and how they interoperate in order to implement the
ISA. The size of a computer's cache for instance, is an organizational issue that
generally has nothing to do with the ISA.
System Design which includes all of the other hardware components within a
computing system such as:
Page 12 of 27
Lecture One
Introduction to Computer &
Microcomputers
Assist.Prof. Dr. Hadeel Nasrat
University of Technology
Electrical Eng. Department
Microprocessor Engineering &
Microcontroller
CPU off-load mechanisms such as direct memory access issues like multiprocessing.
Once both ISA and microarchitecture has been specified, the actual device needs to be
designed into hardware. This design process is often called implementation.
Implementation is usually not considered architectural definition, but rather hardware
design engineering.
Computer Organization deals with the advances in computer architecture right from the
Von Neumann machines to the current day super scalar architectures.
Von Neumann Architecture
The earliest computing machines had fixed programs. Some very simple
computers still use this design, either for simplicity or training purposes. For example, a
desk calculator (in principle) is a fixed program computer. It can do basic mathematics,
but it cannot be used as a word processor or to run video games. To change the
program of such a machine, you have to re-wire, re-structure, or even re-design the
machine. Indeed, the earliest computers were not so much "programmed" as they were
"designed". "Reprogramming", when it was possible at all, was a very manual process,
starting with flow charts and paper notes, followed by detailed engineering designs, and
then the often-arduous process of implementing the physical changes.
The idea of the stored-program computer changed all that. By creating an
instruction set architecture and detailing the computation as a series of instructions (the
program), the machine becomes much more flexible. By treating those instructions in the
same way as data, a stored-program machine can easily change the program, and can
do so under program control.
The von Neumann architecture is a computer design model that uses a
processing unit and a single separate storage structure to hold both instructions and data
as shown in Fig. (2). It is named after mathematician and early computer scientist John
von Neumann. Such a computer implements a universal Turing machine, and the
common "referential model" of specifying sequential architectures, in contrast with
parallel architectures. The term "stored-program computer" is generally used to mean a
Page 13 of 27
Lecture One
Introduction to Computer &
Microcomputers
Assist.Prof. Dr. Hadeel Nasrat
University of Technology
Electrical Eng. Department
Microprocessor Engineering &
Microcontroller
computer of this design, although as modern computers are usually of this type, the term
has fallen into disuse. All general-purpose computers are now based on the key
concepts of the von Neumann architecture.
Though the von Neumann model is universal in general-purpose computing, it
suffers from one obvious problem. All information (instructions and data) must flow back
and forth between the processor and memory through a single channel, and this channel
will have finite bandwidth. When this bandwidth is fully used the processor can go no
faster. This performance limiting factor is called the von Neumann bottleneck.
Hardvard Architecture
A Harvard Architecture as shown in Fig. (3) has one memory for instructions and a
second for data. The name comes from the Harvard Mark 1, an electromechanical
computer which pre-dates the stored-program concept of von Neumann, as does the
architecture in this form. It is still used for applications which run fixed programs, in
areas such as digital signal processing, but not for general-purpose computing. The
Page 14 of 27
Lecture One
Introduction to Computer &
Microcomputers
Assist.Prof. Dr. Hadeel Nasrat
University of Technology
Electrical Eng. Department
Microprocessor Engineering &
Microcontroller
Page 15 of 27
Lecture One
Introduction to Computer &
Microcomputers
Assist.Prof. Dr. Hadeel Nasrat
University of Technology
Electrical Eng. Department
Microprocessor Engineering &
Microcontroller
Page 16 of 27
Lecture One
Introduction to Computer &
Microcomputers
Assist.Prof. Dr. Hadeel Nasrat
University of Technology
Electrical Eng. Department
Microprocessor Engineering &
Microcontroller
Page 17 of 27
Lecture One
Introduction to Computer &
Microcomputers
Assist.Prof. Dr. Hadeel Nasrat
University of Technology
Electrical Eng. Department
Microprocessor Engineering &
Microcontroller
Page 18 of 27
Lecture One
Introduction to Computer &
Microcomputers
Assist.Prof. Dr. Hadeel Nasrat
University of Technology
Electrical Eng. Department
Microprocessor Engineering &
Microcontroller
1. Memory space interface. This is the most common type. It is flexible and reliable
to be applied in any application. Moreover it supports data cash transfer. It can
also be accomplished by several data communication techniques. The drawback
of this technique is the complicated design and usage.
2. I/O ports interface such as serial and parallel ports. I/O port interface is simpler
but less efficient and than memory interface.
5. Indirect bus interface using external buses such as GPIB, SCSI, CAMAC, etc.,
see figure 8.
Page 19 of 27
Lecture One
Introduction to Computer &
Microcomputers
Assist.Prof. Dr. Hadeel Nasrat
University of Technology
Electrical Eng. Department
Microprocessor Engineering &
Microcontroller
BUS Basics
A computer bus is a method of transmitting data from one part of the computer to
another part of the computer. The computer bus connects all devices to the computer
CPU and main memory. The computer bus consists of three parts the address bus, a
data bus and control bus . The data bus transfers actual data whereas the address bus
transfers information about where the data should go. The control bus exchanges all
control signals. The following part contains a brief overview on each of the computer
buses.
Definitions:
1- PnP
Short for Plug and Play, PnP is an ability of a computer to detect and configure a
new piece of hardware automatically, without the requirement of the user to physically
configure the hardware device with jumpers or dipswitches. Plug and Play was
introduced on IBM compatible computers with the release of Microsoft Windows 95,
where Apple Macintosh computers have always supported the ability to automatically
detect and install hardware.
For Plug and Play to operate properly on IBM compatible computers the user must have
the following:
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Lecture One
Introduction to Computer &
Microcomputers
Assist.Prof. Dr. Hadeel Nasrat
University of Technology
Electrical Eng. Department
Microprocessor Engineering &
Microcontroller
Page 21 of 27
Lecture One
Introduction to Computer &
Microcomputers
Assist.Prof. Dr. Hadeel Nasrat
University of Technology
Electrical Eng. Department
Microprocessor Engineering &
Microcontroller
Many manufacturers are trying to eliminate the usage of the ISA slots however for
backwards compatibility you may find 1 or 2 ISA slots with additional PCI slots, AGP
slots, etc. However, today you may also have a motherboard that has no ISA slots. We
highly recommend when purchasing any new internal expansion card that you stay away
from ISA as it has for the most part disappeared.
EISA BUS
Short for Extended Industry Standard Architecture, EISA was announced
September of 1988. EISA is a computer bus designed by 9 competitors to compete with
IBM's MCA BUS. These competitors were AST Research, Compaq, Epson, Hewlett
Packard, NEC, Olivetti, Tandy, WYSE, and Zenith Data Systems.
The EISA Bus provided 32-bit slots at an 8.33 MHz cycle rate for the use with
386DX, or higher processors. In addition the EISA can accommodate a 16-bit ISA card in
the first row.
Unfortunately, while the EISA bus is backwards compatible and is not a
proprietary bus the EISA bus never became widely used and is no longer found in
computers today.
Page 22 of 27
Lecture One
Introduction to Computer &
Microcomputers
Assist.Prof. Dr. Hadeel Nasrat
University of Technology
Electrical Eng. Department
Microprocessor Engineering &
Microcontroller
MCA BUS
Short for Micro Channel Architecture, MCA was introduced by IBM in 1987,
MCA or the Micro Channel bus was a competition for ISA BUS. The MCA bus offered
several additional features over the ISA such as a 32-bit bus, automatically configure
cards (similar to what Plug and Play is today), and bus mastering for greater efficiency.
One of the major downfalls of the MCA bus was it being a proprietary BUS and because
of competing BUS designs. The MCA BUS never became widely used and has since
been fazed out of the desktop computers.
PCI BUS
Introduced by Intel in 1992, revised in 1993 to version 2.0, and later revised in
1995 to PCI 2.1. PCI is short for Peripheral Component Interconnect and is a 32-bit
computer bus that is also available as a 64-bit bus today. The PCI bus is the most
commonly used and found bus in computers today.
MINI PCI
Mini PCI is a new standard which measures at 2.75-inch x 1.81-inch x 0.22-inch is
a new standard developed by leading notebook manufactures. This technology could
allow manufactures to lower their price as the motherboards would be simpler to design.
Type I - Identical to Type II, except requires extra cables for connectors like the
RJ-11 and RJ-45. However, offers more flexibility to where it can be placed in the
computer.
Type II - Used when size is not important. Type II is able to integrate the RJ-11
and RJ-45 connectors and due away with extra cables.
Type III - SO-DIMM style connector that can be installed with a mere 5 mm overall
height above the system board. In addition cabling to the I/O connectors allow Type III
cards to be placed anywhere in the system.
PCI-X
PCI-X is a high performance bus that is designed to meet the increased I/O
demands of technologies such as Fiber Channel, Gigabit Ethernet and Ultra3 SCSI. PCIX capabilities include:
Page 23 of 27
Lecture One
Introduction to Computer &
Microcomputers
Assist.Prof. Dr. Hadeel Nasrat
University of Technology
Electrical Eng. Department
Microprocessor Engineering &
Microcontroller
Page 24 of 27
Lecture One
Introduction to Computer &
Microcomputers
Assist.Prof. Dr. Hadeel Nasrat
University of Technology
Electrical Eng. Department
Microprocessor Engineering &
Microcontroller
USB Bus
USB (Universal Serial Bus) is a new external bus developed by Intel, Compaq,
DEC, IBM, Microsoft, NEC and Northern Telcom and released to the public in 1996 with
the Intel 430HX Triton II Mother Board. USB has the capability of transferring 12 Mbps,
supporting up to 127 devices and only utilizing one IRQ. For PC computers to take
advantage of USB the user must be running Windows 95 OSR2, Windows 98 or
Windows 2000. Linux users also have the capability of running USB with the proper
support drivers installed. To determine if your computer supports USB on the back, front
or sides of the computer look for a small connector with the following symbol.
USB cables are hot swappable which allows users to connect and disconnect the cable
while the computer is on without any physical damage to the cable.
The above illustration is an example of what the end of a USB connector looks like.
There are two standards of USB connectors. Type A connectors are found on the
computer and or USB hub and Type B connectors are found on the peripheral. All USB
cables should only be legally 5m (16ft) max as defined by the USB standard. When
Page 25 of 27
Lecture One
Introduction to Computer &
Microcomputers
Assist.Prof. Dr. Hadeel Nasrat
University of Technology
Electrical Eng. Department
Microprocessor Engineering &
Microcontroller
exceeding this length or utilizing extensions in the cables data loss will occur. The below
illustration is the slots used for each of the connectors shown in the above illustration.
USB VERSIONS
USB 1.0 - The original release of USB supports 127 devices transferring 12 Mbps.
USB 1.1 - Also known as full-speed USB, USB 1.1 is similar to the original release of
USB however minor modifications for the hardware and the specifications. This version
of USB still only supports a rate of 12 Mbps.
USB 2.0 - USB 2.0 also known as hi-speed USB was developed by Compaq, Hewlett
Packard, Intel, Lucent, Microsoft, NEC and Philips and was introduced in 2001. Hi-speed
USB is capable of supporting a transfer rate of up to 480 Mbps and is backwards
compatible meaning it is capable of supporting USB 1.0 and 1.1 devices and cables.
Page 26 of 27
Lecture One
Introduction to Computer &
Microcomputers
Assist.Prof. Dr. Hadeel Nasrat
University of Technology
Electrical Eng. Department
Microprocessor Engineering &
Microcontroller
Exercises:
1) Describe and draw the diagram of Von Neumann model.
2)
3)
4)
5)
6)
Define and explain the following terms PnP, throughput and proprietary.
7)
8)
9)
Compare the performance of the following buses, ISA, EISA, PCI, AGP and USB
Page 27 of 27
Lecture Two
Introduction to Microprocessors
Assist.Prof. Dr. Hadeel Nasrat
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
INTRODUCTION TO MICROPROCESSORS
Microprocessor
Microprocessor: A silicon chip that contains a CPU. In the world of personal computers,
the terms microprocessor and CPU are used interchangeably.
A microprocessor (sometimes abbreviated P) is a digital electronic component with
miniaturized transistors on a single semiconductor integrated circuit (IC).
One or more microprocessors typically serve as a central processing unit (CPU) in a
computer system or handheld device.
Microprocessors made possible the advent of the microcomputer.
Three basic characteristics differentiate microprocessors:
Instruction set: The set of instructions that the microprocessor can execute.
Bandwidth: The number of bits processed in a single instruction.
Clock speed: Given in megahertz (MHz), the clock speed determines how
many instructions per second the processor can execute.
In both cases, the higher the value, the more powerful the CPU. For example, a 32 bit
microprocessor that runs at 50MHz is more powerful than a 16-bit microprocessor that
runs at 25MHz.
In addition to bandwidth and clock speed, microprocessors are classified as being either
RISC (reduced instruction set computer) or CISC (complex instruction set computer).
Page 1 of 22
Lecture Two
Introduction to Microprocessors
Assist.Prof. Dr. Hadeel Nasrat
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
power has led to the dominance of microprocessors over every other form of computer;
every system from the largest mainframes to the smallest handheld computers now uses
a microprocessor at its core.
The microprocessor has changed the way computers work by making them
faster. The microprocessor is often called the brain of the C.P.U.(or the central
processing unit) and without the microprocessor the computer is more or less
useless. Motorola and Intel have invented most of the microprocessors over the last
decade. Over the years their has been a constant battle over cutting edge
technology. In the 80's Motorola won the battle, but in the 90's it looks as Intel has won
the war. Table 1 lists some of types that belong to these companies (families) of
microprocessors.
Table 1: Some Types of Microprocessors
Company
4 bit
8 bit
16 bit
32 bit
64 bit
Intel
4004
4040
8008
8080
8085
8088/6
80186
80286
80386
80486
80860
pentium
Zilog
Z80
Z8000
Z8001
Z8002
Motorola
6800
6802
6809
68006
68008
68010
68020
68030
68040
Page 2 of 22
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
Page 3 of 22
Lecture Two
Introduction to Microprocessors
Assist.Prof. Dr. Hadeel Nasrat
Lecture Two
Introduction to Microprocessors
Assist.Prof. Dr. Hadeel Nasrat
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
8085 Microprocessor
Z80 Microprocessor
74 instructions
158 Instructions
Operates at 3 to 5MHz
Operates at 4 to 20 MHz
It has 5 interrupts
8085 Microprocessor
MC6800 Microprocessor
Page 4 of 22
Lecture Two
Introduction to Microprocessors
Assist.Prof. Dr. Hadeel Nasrat
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
8086 Microprocessor
8088 Microprocessor
Page 5 of 22
Lecture Two
Introduction to Microprocessors
Assist.Prof. Dr. Hadeel Nasrat
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
8086 Microprocessor
It is a 16 bit microprocessor and it
is first 16 bit microprocessor after
8085(8-bit).
It has pipelined architecture (not
highly) and high speed bus
interface on single chip.
80386 Microprocessor
It is a 32 bit microprocessor and it is
logical extension of the 80236.
It is highly pipelined architecture and
much faster speed bus than 8086.
6
7
8
9
10
11
12
13
14
15
Page 6 of 22
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
Lecture Two
Introduction to Microprocessors
Assist.Prof. Dr. Hadeel Nasrat
Other microprocessors
80486: introduced in 1989
Introduction of cache memory (Static RAM with very fast access time).
Thus the Pentium began as the fifth generation of the Intel x86
architecture.
The Pentium had an L2 cache from 256KB to 1MB, used a 50, 60 or 66MH
system bus and contained from 3.1 to 3.3 million transistors.
The Pentium uses a 32-bit expansion bus; however the data bus is 64-bits.
Page 7 of 22
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
Lecture Two
Introduction to Microprocessors
Assist.Prof. Dr. Hadeel Nasrat
The Pro chip was the first chip to be offered in the AT or the ATX format.
The ATX format was preferred, as the Pro consumed more than 25 W of
power, which generated a fair amount of heat.
There were several major improvements of Pentium pro over Pentium, for
example:
It had a superscalar architecture (microprocessor architecture
containing more than one execution unit)
2-stage super pipeline
Internal micro-ops similar to RISC like instructions and internal
thermal protection.
Pentium II
Intel began by separating the processor, and cache of the Pentium Pro,
mounting them together on the circuit board with a big heat sink. Then by
dropping the whole assembly onto the system board, using a Single Edge
Contact (SEC) with 242 pins in the slot, and adding the 57 MMX (Multimedia
extension) micro-code instructions, then Intel had the Pentium II. This way,
defective cache modules don't force throwing out of a perfectly good CPU,
because of a bad cache. And to further improve cache yields, the Pentium II
ran cache at half the speed of the CPU.
The pipelined Floating-Point Unit (FPU) supports the 32-bit and 64-bit formats
specified in IEEE standard 754, as well as an 80-bit format.
Page 8 of 22
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
Lecture Two
Introduction to Microprocessors
Assist.Prof. Dr. Hadeel Nasrat
Parity protected address/request and response system bus signals with a retry
mechanism for high data integrity and reliability.
An on-die diode monitors the die temperature. A thermal sensor located on the
motherboard can monitor the die temperature of the Pentium II processor for
thermal management purposes.
Pentium III
Similar to Pentium II, the Pentium III processor also uses a Dynamic Execution
micro-architecture: a unique combination of multiple branch prediction, data
flow analysis, and speculative execution.
The Pentium III has two major differences with Pentium II: Improved MMX and
Processor serial number feature. The improved MMX has totally 70
instructions enabling advanced imaging, 3D streaming audio and video, and
speech recognition for enhanced Internet Experience: technology instructions
for enhanced media and communication performance.
Data Pre-fetch Logic anticipates the data needed by the application programs
and pre-loads into the Advanced Transfer Cache increasing performance.
The processor has multiple low power states such as Sleep, and Deep to
conserve power during idle times. The system bus runs at 100MHz and
133MHz allowing for a 33% increase in available bandwidth to the processor.
Page 9 of 22
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
Lecture Two
Introduction to Microprocessors
Assist.Prof. Dr. Hadeel Nasrat
It includes several important new features and innovations that will allow the
Intel Pentium 4 processor to deliver industry-leading performance for the next
several years.
The Pentium 4 processor enables real time MPEG2 video encoding and near
real-time MPEG4 encoding, allowing efficient video editing and video
conferencing.
It adds 144 new 128-bit Single Instruction Multiple Data (SIMD) instructions
called SSE2 (Streaming SIMD Extension 2) that improves performance for
multi-media, content creation, scientific, and engineering applications.
Page 10 of 22
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
Lecture Two
Introduction to Microprocessors
Assist.Prof. Dr. Hadeel Nasrat
The Pentium 4 processor has a system bus with 3.2 G-bytes per second of
bandwidth. This bandwidth is achieved with a 64-bit wide bus capable of
transferring data at a rate of 400MHz.
Itanium
Itanium core processor is not binary compatible with X86 processors, instead it
has a separate compatibility unit in hardware to provide IA32 compatibility.
Itanium only allow memory operands in load and store operations.
The Itanium processor was specifically designed to provide a very high level of
parallel processing, to enable high performance without requiring very high
clock frequencies (which can lead to excessive power consumption and heat
generation).
the dual-core version can support up to two software threads per core,
Extensive execution resources per core: 256 application registers (128 general
purpose, 128 floating point) and 64 predicate registers,
Large cache: 24MB in the dual-core version (12MB per core), providing data
to each core at up to 48GB/s,
Page 11 of 22
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
Lecture Two
Introduction to Microprocessors
Assist.Prof. Dr. Hadeel Nasrat
it has fewer transistors in each core. This may be an advantage in current and
future multi-core designs.
Itanium 2
The Itanium 2 is an IA-64 microprocessor developed jointly by Hewlett Packard
(HP) and Intel, and introduced on July 8, 2002. The first Itanium 2 processor
(code-named McKinley) was substantially more powerful than the original Itanium
processor, roughly doubling performance, and providing competitive performance
across a range of data- and compute-intensive workloads. Several generations of
Itanium 2 processors have followed.
The Itanium 2 processor architecture is, dubbed Explicitly Parallel Instruction
Computing (EPIC). It is theoretically capable of performing roughly 8 times more
work per clock cycle than other CISC and RISC architectures due to its Parallel
Computing Micro-architecture. However, performance is heavily dependent on
software compilers and their ability to generate code which efficiently uses the
available execution units of the processor.
All Itanium 2 processors to date share a common cache hierarchy. They have 16
KB of Level 1 instruction cache and 16 KB of Level 1 data cache. The L2 cache is
unified (both instruction and data) and is 256 KB. The Level 3 cache is also
unified and varies in size from 1.5 MB to 24 MB. In an interesting design choice,
the L2 cache contains sufficient logic to handle semaphore operations without
disturbing the main ALU.
The latest Itanium processor, however, features a split L2 cache, adding a
dedicated 1MB L2 cache for instructions and thereby effectively growing the
original 256 KB L2 cache, which becomes a dedicated data cache.
Most systems sold by enterprise server vendors that contain 4 or more processor
sockets use proprietary Non-Uniform Memory Access (NUMA) architectures
that supersede the more limited front side bus of 1 and 2 CPU socket servers.
The Itanium 2 bus is occasionally referred to as the Scalability Port, but much
more frequently as the McKinley bus. It is a 200 MHz, 128-bit wide, double
Page 12 of 22
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
Lecture Two
Introduction to Microprocessors
Assist.Prof. Dr. Hadeel Nasrat
pumped bus capable of 6.4 GB/s more than three times the bandwidth of the
original Itanium bus, known as the Merced bus.
In 2004, Intel released processors with a 266 MHz bus, increasing bandwidth to
8.5 GB/s. In early 2005, processors with a 10.6 GB/s, 333 MHz bus were
released.
Pentium D
A 9xx-series Pentium D package contains two Pentium 4 dies, unlike other multicore processors (including the Pentium D 8xx-series) that place both cores on a
single die.
The Pentium D was the first announced multi-core CPU (along with its more
expensive twin, the Pentium Extreme Edition) from any manufacturer intended for
desktop computers.
Intel underscored the significance of this introduction by predicting that by the end
of 2006 over 70% of its shipping desktop CPUs would be multi-core.
With heat rising incrementally faster than the rate at which signals move through
the processor, known as clock speed, an increase in performance can create an
even larger increase in heat. The answer is multi-core microprocessor. For
example, by moving from a single high-speed core, which generates a
corresponding increase in heat, to multiple slower cores, which produce a
corresponding reduction in heat, enterprises can potentially improve application
performance while reducing their thermal output.
Page 13 of 22
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
Lecture Two
Introduction to Microprocessors
Assist.Prof. Dr. Hadeel Nasrat
The Pentium D 820 runs in at 2.8GHz, is dual-core, its highlights are; it features
two 16KB data caches in addition to data cache, each core includes an Execution
Trace Cache that stores up to 12 K decoded micro-ops in the order of program
execution,
Microprocessor Fundamentals
Microprocessors are the "brains" of a computer. They direct the computer how to
perform the calculations and handle the data per user's instructions. Most of the logical
functionality resides in the central processing unit (CPU).
Components
A microprocessor contains an arithmetic logic unit (ALU) which processes any addition,
multiplication or Boolean operations that come through the device. It sends the results to the
control unit. The control unit processes any instructions and data and sends it to the registers for
temporary memory or through either the data, address or control bus.
Page 14 of 22
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
Lecture Two
Introduction to Microprocessors
Assist.Prof. Dr. Hadeel Nasrat
Instruction Cycle
Each microprocessor model has a set of instructions such as add, move, branch
and jump. The microprocessor fetches each of these instructions from the memory. They
are stored in strings containing the number code of the instruction and the data relevant
to the instruction. Microprocessors follow an instruction cycle of fetch, decode and
execute.
Pipelining
Microprocessors pipeline instructions by overlapping the different parts of the
instruction cycle. Rather than wait for one cycle of fetch-decode-execute for one
instruction to complete, the microprocessor fetches the next instruction while it decodes
the previous instruction. This allows the microprocessor to process more instructions in a
given amount of time.
Cache
Cache is a small amount of memory that holds the most recently used data. This
memory allows a computer to get data quickly. This cuts the time it takes a computer to
access a recent program and computer data. Typically, the more cache memory
available, the faster the computer.
Clock Speed
Clock speed is the most recognized specification of a microprocessor. It is
typically measured in megahertz (MHz) or gigahertz (GHz). Generally speaking, the
faster your clock speed, the faster your computer can compute data. Also, be aware that
dual and quad core microprocessors are available. According to the Computer Shopper
website, a quad-core 2.5GHz Core 2 Quad Q9400 from Intel will outperform a 3GHz
Core 2 Duo E8400 in many computing tasks.
Bus Speed
Bus speed, typically called front-side bus (FBS), is the rate that a microprocessor
communicates with a motherboard's memory controller. High FSB speeds will increase
the performance of computer operations that are RAM-intensive, such as video and
audio editing and coding programs, or high-end 3D games.
Page 15 of 22
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
Lecture Two
Introduction to Microprocessors
Assist.Prof. Dr. Hadeel Nasrat
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
Lecture Two
Introduction to Microprocessors
Assist.Prof. Dr. Hadeel Nasrat
Control:
Most systems have at least 4 control bus connections (active low).
MRDC (Memory ReaD Control), MWRC, IORC (I/O Read Control), IOWC
Fig. 2: The block diagram of computer system showing the buses structure
Bus Standards:
EISA: 8 MHz
32-bit (older 386 and 486 machines).
Page 17 of 22
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
Lecture Two
Introduction to Microprocessors
Assist.Prof. Dr. Hadeel Nasrat
Only disk and video.Competes with the PCI but is not popular.
USB (Universal Serial Bus): 1.5 Mbps,12 Mbps and now 480 Mbps.
Newest systems.
Serial connection to microprocessor.
For keyboards, the mouse, modems and sound cards.
To reduce system cost through fewer wires.
The memory
The memory structures of all Intel 80X86-Pentium 4 personal computer systems
are similar. This includes the first personal computers based upon the 8088 introduced in
1981 by IBM to the most powerful high-speed versions of today based on the Pentium 4.
The memory system is divided into three main parts: TPA (T ransient P rogram Area),
system area, and XMS (Extended Memory System). The type of microprocessor in
your computer determines whether an extended memory system exists. If the computer
is based upon an older 8086 or 8088 (a PC or XT), the TPA and system areas exist, but
there is no extended memory area. The PC and XT contain 640K bytes of TPA and 384K
bytes of system memory, for a total memory size of IM bytes. We often call the first IM
byte of memory the real or conventional memory system because each Intel
microprocessor is designed to function in this area by using its real mode of operation.
I/O Devices
Page 18 of 22
Lecture Two
Introduction to Microprocessors
Assist.Prof. Dr. Hadeel Nasrat
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
8088
80386DX, 80486
Page 19 of 22
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
Lecture Two
Introduction to Microprocessors
Assist.Prof. Dr. Hadeel Nasrat
Pentium/Pro/II/III
Page 20 of 22
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
Lecture Two
Introduction to Microprocessors
Assist.Prof. Dr. Hadeel Nasrat
4. Superscalar Processors
The architecture of Super-scalar Processors allows the computer to execute
several instructions simultaneously and independently. Super-scalar microprocessors
use pipe-lining to enable processing multiple instructions, but each instruction has to be
Page 21 of 22
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
Lecture Two
Introduction to Microprocessors
Assist.Prof. Dr. Hadeel Nasrat
Others
General Purpose Processor (GPP) is designed for a variety of tasks and not only
for one specific application or software. A Special Purpose Processor (SPP) has
functions similar to the microcomputer peripheral chip. The only difference is that SPP
has a specialized instruction set to control the functions independently, while a peripheral
chip is controlled by the CPU. Application-Specific Integrated Circuit (ASIC) is a type of
integrated circuit designed for a special purpose application. For example, an ASIC
created for a company's line of mobile phones only works on that specific line of mobile
phones. Digital Signal Processor (DSP) is a type of very fast microprocessor, mostly
used in math-intensive, signal-processing applications. It transforms analog signals into
digital data that is analyzed.
Page 22 of 22
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
Lecture Three
8085 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
8085 Microprocessor
It is a 8 bit microprocessor.
It has 16-bit address bus and hence can address up to 216 = 65536 bytes
(64KB) memory locations through A0-A15
The first 8 lines of address bus and 8 lines of data bus are multiplexed AD0
AD7
Six 8-bit general purpose register arranged in pairs: BC, DE, HL.
It requires a signal +5V power supply and operates at 3.2 MHZ single phase
clock.
Page 1 of 18
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
Lecture Three
8085 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
Page 2 of 18
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
Lecture Three
8085 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
8085 is a 40 pin IC, DIP package. The signals from the pins can be grouped as
follows:
1. Power supply and clock signals
2. Address bus
3. Data bus
4. Control and status signals
5. Interrupts and externally initiated signals
6. Serial I/O ports
Vcc
Vss
Ground
X1, X2 :
Page 3 of 18
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
Lecture Three
8085 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
The frequency is internally divided by two. Since the basic operating timing
frequency is 3 MHz, a 6 MHz crystal is connected externally.
CLK (output)-Clock Output is used as the system clock for peripheral and devices
interfaced with the microprocessor.
2. Address Bus:
It carries the most significant 8 bits of the memory address or the 8 bits of the I/O
address;
These multiplexed set of lines used to carry the lower order 8 bit address as well
as data bus.
During the opcode fetch operation, in the first clock cycle, the lines deliver the
lower order address A0 - A7.
In the subsequent IO / memory, read / write clock cycle the lines are used as data
bus.
The CPU may read or write out data through these lines.
This signal helps to capture the lower order address presented on the multiplexed
address / data bus.
This indicates that the selected memory location or I/O device is to be read and
that the data bus is ready for accepting data from the memory or I/O device.
This indicates that the data on the data bus is to be written into the selected
memory location or I/O device.
This status signal indicates that the read / write operation relates to whether the
memory or I/O device.
Page 4 of 18
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
Lecture Three
8085 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
5. Status Signals:
IO M
S0
S1
Halt
MEMORY WRITE
MEMORY READ
IO WRITE
IO READ
Opcode fetch
Interrupt Acknowledge
They are the signals initiated by an external device to request the microprocessor
to do a particular task or work.
INTR
INTRA (active low output)
Page 5 of 18
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
Lecture Three
8085 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
RESETOUT (Output)
Used to reset all the connected devices when the microprocessor is reset.
3 output states are high & low states and additionally a high impedance state.
When enable E is high the gate is enabled and the output Q can be 1 or 0 (if A is
0, Q is 1, otherwise Q is 0). However, when E is low the gate is disabled and the
output Q enters into a high impedance state.
When 2 or more devices are connected to a common bus, to prevent the devices
from interfering with each other, the tristate gates are used to disconnect all
devices except the one that is communicating at a given instant.
The CPU controls the data transfer operation between memory and I/O device.
Direct Memory Access operation is used for large volume data transfer between
memory and an I/O device directly.
The CPU is disabled by tri-stating its buses and the transfer is effected directly by
external control circuits.
HOLD signal is generated by the DMA controller circuit. On receipt of this signal,
the microprocessor acknowledges the request by sending out HLDA signal and
leaves out the control of the buses. After the HLDA signal the DMA controller
starts the direct transfer of data.
Page 6 of 18
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
Lecture Three
8085 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
READY (Output)
Memory and I/O devices will have slower response compared to microprocessors.
Before completing the present job such a slow peripheral may not be able to
handle further data or control signal from CPU.
The processor sets the READY signal after completing the present job to access
the data.
The microprocessor enters into WAIT state while the READY pin is disabled.
SID (input)
SOD (output)
Page 7 of 18
Lecture Three
8085 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
Page 8 of 18
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
Lecture Three
8085 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
Registers of 8085:
The 8085 have six general-purpose registers to store 8-bit data during program
execution.
They can be combined as register pairs BC, DE, and HL-to perform some 16-bit
operations.
Accumulator (A):
The accumulator is an 8-bit register that is part of the arithmetic/logic unit (ALU).
This register is used to store 8-bit data and to perform arithmetic and logical
operations.
Flags:
The ALU includes five flip-flops that are set or reset according to the result of an
operation.
The microprocessor uses the flags for testing the data conditions.
They are Zero (Z), Carry (CY), Sign (S), Parity (P), and Auxiliary Carry (AC) flags.
The most commonly used flags are Sign, Zero, and Carry.
Page 9 of 18
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
Lecture Three
8085 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
It is a memory pointer. Memory locations have 16-bit addresses, and that is why
this is a 16-bit register.
The function of the program counter is to point to the memory address of the next
instruction to be executed.
The beginning of the stack is defined by loading a 16-bit address in the stack
pointer (register).
Temporary Register: It is used to hold the data during the arithmetic and logical
operations.
Instruction Register: When an instruction is fetched from the memory, it is loaded in
the instruction register.
Instruction Decoder: It gets the instruction from the instruction register and decodes the
instruction. It identifies the instruction to be performed.
Page 10 of 18
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
Lecture Three
8085 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
Serial I/O Control: It has two control signals named SID and SOD for serial data
transmission.
RD
and WR
1. Immediate Addressing:
In immediate addressing mode, the data is specified in the instruction itself. The
data will be a part of the program instruction.
For Example:
MVI B, 3EH
Page 11 of 18
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
Lecture Three
8085 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
2. Direct Addressing:
In direct addressing mode, the address of the data is specified in the instruction.
The data will be in memory. In this addressing mode, the program instructions and
data can be stored in different memory.
For Example:
; Load the data available in memory location 1050H in to Acc
LDA 1050H
SHLD 3000H
3. Register Addressing:
In register addressing mode, the instruction specifies the name of the register in
which the data is available.
For Example:
MOV A, B
In register indirect addressing mode, the instruction specifies the name of the
register in which the address of the data is available. Here the data will be in
memory and the address will be in the register pair.
For Example:
MOV A, M
LDAX B
5. Implied Addressing:
For Example:
CMA
Page 12 of 18
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
Lecture Three
8085 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
2. ARITHMETIC INSTRUCTIONS:
Includes the instructions, which performs the addition, subtraction, increment or
decrement operations. The flag conditions are altered after execution of an instruction in
this group.
ADD A,B
SUI B,05H
3. LOGICAL INSTRUCTIONS:
The instructions which performs the logical operations like AND, OR, EXCLUSIVEOR, complement, compare and rotate instructions are grouped under this heading. The
flag conditions are altered after execution of an instruction in this group.
ORA A
ANI B, 01H
4. BRANCHING INSTRUCTIONS:
The instructions that are used to transfer the program control from one memory
location to another memory location are grouped under this heading.
CALL
JMP 4100
Page 13 of 18
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
Lecture Three
8085 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
Page 14 of 18
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
Lecture Three
8085 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
Page 15 of 18
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
Lecture Three
8085 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
Page 16 of 18
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
Lecture Three
8085 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
EXERCISE 1:
1.
2.
3.
4.
5.
6.
7.
8.
9.
EXERCISE 2:
1.
Using LDA and STA instructions, write a program that will transfer five byte of
memory from location 3000H through 3004H to location 3200H through 3204H
Page 17 of 18
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
Lecture Three
8085 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
Page 18 of 18
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
Lecture Four
8086 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
8086 Microprocessor
Page 1 of 35
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
Lecture Four
8086 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
The Microprocessor 8086 is a 16-bit CPU available in different clock rates and
packaged in a 40 pin CERDIP or plastic package.
mode)
and
other
function
in
maximum
(multiprocessor mode).
mode
configuration
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
Lecture Four
8086 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
The first are the signal having common functions in minimum as well as
maximum mode.
The second are the signals which have special functions for minimum
mode
The third are the signals having special functions for maximum mode.
AD15-AD0:
o
These are the time multiplexed memory I/O address and data lines.
Contain the rightmost eight bits of the memory address or I/O port number
when ALE is active logic 1 or contain data whenever ALE is logic 0
(Multiplexed address(ALE=1)/data bus(ALE=0).
These pins are at their high impedance stste during a hold acknowledge
These pins also attain a high impedance state during the hold
acknowledge.
S5 is the logic level of the internal interrupt enable flag,( Indicates condition
of IF flag bits)
S6 is always logic 0.
S4
S3
Function
Extra segment
Stack segment
Code or No segment
Data segment
BHE/S7: The bus high enable is used to Enables the most significant data bus
bits (D15 -D8 ) during a read or write operation. The state of S7 is always a logic 1.
Page 3 of 35
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
Lecture Four
8086 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
RD Read: This signal on low indicates the peripheral that the processor is
performing memory or I/O read operation. The signal remains tristated (high
impedance state) during a hold acknowledge.
READY : This is the acknowledgement from the slow device or memory that they
have completed the data transfer. The signal made available by the devices is
synchronized by the 8284A clock generator to provide ready input to the 8086.
The signal is active high.
INTR-Interrupt Request : This is a triggered input. This is sampled during the last
clock cycles of each instruction to determine the availability of the request. If any
interrupt request is pending, the processor enters the interrupt acknowledge cycle.
This can be internally masked by resulting the interrupt enable flag. This signal is
active high and internally synchronized.
TEST :
o
This input is examined by a WAIT instruction. If the TEST pin goes low,
execution will continue, else the processor remains in an idle state. The
input is synchronized internally during each clock cycle on leading edge of
clock.
CLK- Clock Input: The clock input provides the basic timing for processor
operation and bus control activity. Its an asymmetric square wave with 33% duty
cycle.
NMI - Non-maskable interrupt: Similar to INTR except IF flag bit is not consulted
and interrupt is vector 2.
RESET:
o
Page 4 of 35
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
Lecture Four
8086 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
In this mode, all the control signals are given out by the microprocessor chip itself.
Page 5 of 35
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
Lecture Four
8086 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
is low, it indicates the CPU is having an I/O operation, and when it is high, it
indicates that the CPU is having a memory operation. It is tristated during local
bus hold acknowledge .
INTA Interrupt Acknowledge: This signal is used as a read strobe for interrupt
acknowledge cycles. i.e. when it goes low, the processor has accepted the
interrupt.
ALE Address Latch Enable: This output signal indicates the availability of the
valid address on the address/data lines, and is connected to latch enable input of
latches. This signal is active high and is never tristated.
HOLD :The hold input Requests a direct memory access (DMA). When the HOLD
signal is logic 1, the microprocessor stops execution software and places its
address, data and control bus at the high-impedance state.
HLDA- Hold Acknowledge: Indicates that the microprocessor has entered the
hold state.
In the maximum mode, the 8086 is operated by strapping the MN/MX pin to
ground.
In this mode, the processor derives the status signal S2, S1, S0. Another chip
called bus controller derives the control signal using this status information .
In the maximum mode, there may be more than one microprocessor in the system
configuration.
Page 6 of 35
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
Lecture Four
8086 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
The following pin functions are applicable for maximum mode operation of 8086.
accesses (DMA) during maximum mode operation. These lines are bi-directional,
and are used to both request and grant a DMA operation.
S2 , S1 , S0 Status Lines: the status bits indicate the function of the current bus
cycle. These signals are normally decoded by the 8288 bus controller. Table (2)
shows the function of these three statues bits in the maximum mode.
Page 7 of 35
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
Lecture Four
8086 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
Table (2): Bus control function generated by the bus controller using
Function
S2
S1
S0
Interrupt Acknowledge
Halt
Op-Code Fetch
Read Memory
Write Memory
Passive
LOCK: Lock output is used to lock peripherals off the system. Activated by using
the LOCK: prefix on any instruction.
QS1 and QS0- Queue statues bits: show the status of the internal instruction.
These pins are provides for access by the numeric coprocessor see table (3) for
the operation of the queue status bits.
Table (2): Queue status bits
QS1
QS0
Indication
Empty Queue
Page 8 of 35
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
Lecture Four
8086 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
Page 9 of 35
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
Lecture Four
8086 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
8086 has two blocks Bus Interfacing Unit (BIU) and Execution Unit (EU).
The BIU performs all bus operations such as instruction fetching, reading and
writing operands for memory and calculating the addresses of the memory
operands. The instruction bytes are transferred to the instruction queue.
EU contains Control circuitry, Instruction decoder, ALU, Pointer and Index register
Flag register.
It provides a full 16 bit bidirectional data bus and 20 bit address bus.
The bus interface unit is responsible for performing all external bus operations.
This queue permits prefetch of up to six bytes of instruction code. When ever the
queue of the BIU is not full, it has room for at least two more bytes and at the
same time the EU is not requesting it to read or write operands from memory, the
BIU is free to look ahead in the program by prefetching the next sequential
instruction.
These prefetching instructions are held in its FIFO queue. With its 16 bit data bus,
the BIU fetches two instruction bytes in a single memory cycle.
After a byte is loaded at the input end of the queue, it automatically shifts up
through the FIFO to the empty location nearest the output.
Page 10 of 35
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
Lecture Four
8086 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
The EU accesses the queue from the output end. It reads one instruction byte
after the other from the output of the queue. If the queue is full and the EU is not
requesting access to operand in memory.
These intervals of no bus activity, which may occur between bus cycles are known
as Idle state.
If the BIU is already in the process of fetching an instruction when the EU request
it to read or write operands from memory or I/O, the BIU first completes the
instruction fetch bus cycle before initiating the operand read / write cycle.
The BIU also contains a dedicated adder which is used to generate the 20bit
physical address that is output on the address bus. This address is formed by
adding an appended 16 bit segment address and a 16 bit offset address.
For example: The physical address of the next instruction to be fetched is formed
by combining the current contents of the code segment CS register and the
current contents of the instruction pointer IP register.
The BIU is also responsible for generating bus control signals such as those for
memory read or write and I/O read or write.
EXECUTION UNIT
The Execution unit is responsible for decoding and executing all instructions.
The EU extracts instructions from the top of the queue in the BIU, decodes them,
generates operands if necessary, passes them to the BIU and requests it to
perform the read or write bys cycles to memory or I/O and perform the operation
specified by the instruction on the operands.
During the execution of the instruction, the EU tests the status and control flags
and updates them based on the results of executing the instruction.
If the queue is empty, the EU waits for the next instruction byte to be fetched and
shifted to top of the queue.
Whenever this happens, the BIU automatically resets the queue and then begins
to fetch instructions from this new location to refill the queue.
Page 11 of 35
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
Lecture Four
8086 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
Registers of 8086
The 8086 microprocessor has a total of fourteen registers that are accessible to the
programmer. It is divided into four groups. They are:
Page 12 of 35
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
Lecture Four
8086 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
Source Index (SI) is a 16-bit register. SI is used for indexed, based indexed and register
indirect addressing, as well as a source data address in string manipulation instructions.
Used in conjunction with the DS register to point to data locations in the data segment.
Destination Index (DI) is a 16-bit register. Used in conjunction with the ES register in
string operations.
Page 13 of 35
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
Lecture Four
8086 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
registers (AX, BX, CX, DX) and index register (SI, DI) is located in the data segment. DS
register can be changed directly using POP and LDS instructions.
Extra segment (ES) used to hold the starting address of Extra segment. Extra segment
is provided for programs that need to access a second data segment. Segment registers
cannot be used in arithmetic operations.
1. Status Flags
Status Flags represent result of last arithmetic or logical instruction executed.
Conditional flags are as follows:
Carry Flag (CF):
arithmetic.
lower nibble (i.e. D0 D3) to upper nibble (i.e. D4 D7), the AF flag is set i.e. carry given
by D3 bit to D4 is AF flag. This is not a general-purpose flag, it is used internally by the
processor to perform Binary to BCD conversion.
Parity Flag (PF): This flag is used to indicate the parity of result. If lower order 8-bits of
the result contains even number of 1s, the Parity Flag is set and for odd number of 1s,
the Parity Flag is reset.
Page 14 of 35
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
Lecture Four
8086 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
Zero Flag (ZF): It is set; if the result of arithmetic or logical operation is zero else it is
reset.
Sign Flag (SF): In sign magnitude format the sign of number is indicated by MSB bit. If
the result of operation is negative, sign flag is set.
Overflow Flag (OF): It occurs when signed numbers are added or subtracted. An OF
indicates that the result has exceeded the capacity of machine.
2. Control Flags
Control flags are set or reset deliberately to control the operations of the execution unit.
Control flags are as follows:
When trap flag is set, program can be run in single step mode.
2. Interrupt Flag (IF):
It is an interrupt enable/disable flag.
If it is set, the maskable interrupt of 8086 is enabled and if it is reset, the
interrupt is disabled.
instruction.
When it is reset, the string bytes are accessed from lower memory address
to higher memory address.
Page 15 of 35
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
Lecture Four
8086 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
64 K
384 K ROM
A0000H
640 K RAM
1K
ROM BIOS
ROM BASIC
F0000H FFFFFH
Present in older computers
Reserved ROM
Video BIOS ROM
C0000H - C7FFFH
Video RAM
A0000H BFFFFH
User RAM
Varies between 12 K to 40 K
00400H - 005FFH
00000H - 003FFH
Page 16 of 35
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
Lecture Four
8086 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
The diagram is called a memory map. This is because, like a road map, it is a guide
showing how the system memory is allocated. This type of information is vital to the
programmer, who must know exactly where his or her programs can be safely loaded.
Note that some memory locations are marked reserved and others dedicated. The
dedicated locations are used for processing specific system interrupts and the reset
function. Intel has also reserved several locations for future H/W and S/W products. If
you make use of these memory locations, you risk incompatibility with these future
products.
MEMORY SEGMENTATION
The Memory Address Space (MAS) is divided into 65,536 (i.e., 10,000H)
paragraphs. Each paragraph is 16 (i.e., 10H) consecutive bytes. Thus each paragraph
starts at a physical address whose rightmost hexadecimal digit is zero:
Addresses within a segment can range from address 00000h to address 0FFFFh. This
corresponds to the 64K-byte length of the segment. An address within a segment is
called an offset or logical address. A logical address gives the displacement from the
address base of the segment to the desired location within it, as opposed to its "real"
address, which maps directly anywhere into the 1 MB memory space. This "real" address
is called the physical address.
What is the difference between the physical and the logical address?
The physical address is 20 bits long and corresponds to the actual binary code output by
the BIU on the address bus lines. The logical address is an offset from location 0 of a
given segment.
When two segments overlap it is certainly possible for two different logical addresses to
map to the same physical address. This can have disastrous results when the data
begins to overwrite the subroutine stack area, or vice versa. For this reason you must be
very careful when segments are allowed to overlap.
Page 17 of 35
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
Lecture Four
8086 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
You should also be careful when writing addresses on paper to do so clearly. To specify
the logical address XXXX in the stack segment, use the convention SS:XXXX, which is
equal to [SS] * 16 + XXXX.
FFFFFH
10H bytes
Paragraph
FFFFH
FFFF0H
FFFEFH
00030H
0002FH
10H bytes
00020H
0001FH
10H bytes
Paragraph 2H
Paragraph
1H
00010H
0000FH
10H bytes
Paragraph
0H
00000H
Page 18 of 35
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
Lecture Four
8086 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
A physical memory segment is a block of 216 (i.e., 64K or 10,000H) consecutive bytes
starting at a paragraph boundary.
The segments overlap but they all begin at different paragraph boundaries.
All segments from the one starting at F0000h to the one starting at FFFF0h wrap
around and end at lower memory addresses.
Since each segment starts at a physical address whose leftmost hexadecimal digit is
zero, this digit need not be stored, hence a 16-bit segment register can be used to
store the remaining four digits of the 20-bit address.
Within a segment, a memory location is specified by giving an offset. This is the
number of bytes from the beginning of the segment.
Since a segment is 10,000H bytes, the first byte in a segment has offset 0000h and
the last byte has offset FFFFh (Note: Offsets are unsigned numbers).
Thus a memory location may be specified by providing the 16-bit segment base
address, and a 16-bit offset, written in the form segment:offset; this is known as a
logical address for the memory location.
Page 19 of 35
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
Lecture Four
8086 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
For example, the logical address A4FB:4872h means offset 4872h within segment
A4FBh, that is, the segment starting at physical address A4FB0h. To obtain the
corresponding 20-bit physical (i.e., absolute) address, the 8086/8088 microprocessor
first shifts the segment base address 4 bits to the left (this is equivalent to multiplying
by 10H), and then adds the offset. Thus the physical address for A4FB:4872h is:
A4FB0h
+
4872h
A9822h
Because segments may overlap, the segment:offset form of an address is not unique
for a particular memory location as is the case for the physical address of that
memory location. For example consider the following:
Example:
A memory location has physical address 80FD2h. In what segment does it have offset
BFD2h ?
Solution:
physical address = segment * 10h
offset
Hence:
physical address = 80FD2h
-
offset =
BFD2h
75000h
Example:
For the memory location whose physical address is 1256Ah, give the address in
segment:offset form for segments 1256h and 1240h.
Solution:
Let X be the offset in segment 1256h and Y the offset in segment 1240h. We have:
Page 20 of 35
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
Lecture Four
8086 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
(1)
(2)
000Ah
1256h
016Ah
1240h
Page 21 of 35
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
Lecture Four
8086 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
The Code segment contains the instructions of a program. The Data segment
provides a read/write memory in which the data of a program can be stored. The
Extra segment is usually used for data storage. Some string operations use the Extra
segment to handle memory addressing. The Stack segment is used for temporary
storage of addresses and data. It is in this segment that the values of the IP register,
the Flags register, and other registers are stored whenever an Interrupt or subroutine
call occurs.
Every 8086/8088 assembly language program must contain an explicitly defined
Code segment. An 8086/8088 assembly language program which generates an
executable file with extension .EXE must have an explicitly defined Stack segment.
Such a program may or may not contain the Data or the Extra segment. An
8086/8088 assembly language program which generates an executable file with
extension .COM has only one explicitly defined segment: the Code segment. The
Stack segment for such a program is implicit. Thus the maximum size for an
8086/8088 COM format Assembly language program is 64K.
An EXE format 8086/8088 Assembly language program may contain multiple
segments of a certain type; however only four logical segments can be active at a
time.
To keep track of the various logical segments, the 8086/8088 uses each of its four
segment registers to hold a 16-bit portion (called a segment number) of the 20-bit
starting address of a logical segment. The remaining four rightmost bits of the
address are implied 0000 because a logical segment starts at a paragraph boundary.
The CS, DS, SS, and ES registers contain the code, data, stack, and extra segment
numbers, respectively. The segment registers provide the segment base address part
of a logical memory address (i.e., segment:offset address):
CS:IP
DS:offset is the segment:offset address of the byte with the given offset in the data
segment.
SS:SP
Page 22 of 35
University of Technology
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Microprocessor Engineering & Microcontroller
SS:BP
Lecture Four
8086 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
is the segment:offset address of the byte, in the stack, whose offset is in the
BP register.
DS:SI
ES:DI
The segment registers must be loaded with the segment numbers. Just what values are
loaded is dependent in part on how the linker and loader have assigned the logical
segments to memory locations, and on how the segment registers have been initialized
during the loading process. Typically, the CS register will be loaded with the proper code
segment number so that, in conjunction with the IP register, the programs first
executable instruction will be referenced. The SS and SP registers will also be properly
loaded if the stack segment is explicitly defined in the program. The other segment
registers, DS and ES, must be explicitly loaded by the programmer if they are
used by the program.
Page 23 of 35
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
Lecture Four
8086 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
Implicit
Explicit
Implicit operands mean that the instruction by definition has some specific operands.
The programmers do NOT select these operands.
Example: Implicit operands
XLAT ; automatically takes AL and BX as operands
AAM ; it operates on the contents of AX.
Explicit operands mean the instruction operates on the operands specified by the
programmer.
Example: Explicit operands
MOV AX, BX; it takes AX and BX as operands
XCHG SI, DI; it takes SI and DI as operands
The location of an operand value in memory space is called the Effective Address (EA)
We can classify the addressing modes of 8086 into four groups:
Page 24 of 35
University of Technology
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Microprocessor Engineering & Microcontroller
Immediate addressing
Register addressing
Memory addressing
Lecture Four
8086 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
ADD AX, 5
reg16: 16-bit general registers: AX, BX, CX, DX, SI, DI, SP or BP.
reg8 : 8-bit general registers: AH, BH, CH, DH, AL, BL, CL, or DL.
Sreg : segment registers: CS, DS, ES, or SS. There is an exception: CS cannot
be a destination.
For register addressing modes, there is no need to compute the effective address. The
operand is in a register and to get the operand there is no memory access involved.
Page 25 of 35
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
Lecture Four
8086 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
ADD AX, SI
MOV DS, AX
Page 26 of 35
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
Lecture Four
8086 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
values provide offsets into the data segment. If you want to provide an offset into a
different segment, you must use a segment override prefix before your address. For
example, to access location 1234H in the extra segment (ES) you would use an
instruction of the form MOV AX,ES:[1234H]. Likewise, to access this location in the code
segment you would use the instruction MOV AX, CS:[1234H]. The DS: prefix in the
previous examples is not a segment override.
The instruction MOV AL,DS:[8088H] is same as MOV AL, [8088H]. If not mentioned DS
register is taken by default.
different
segments.
The
following
Page 27 of 35
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
Lecture Four
8086 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
Page 28 of 35
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
Lecture Four
8086 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
AL, [BX][SI]
MOV
AL, [BX][DI]
MOV
AL, [BP][SI]
MOV
AL, [BP][DI]
Suppose that
BX = 1000H, SI = 880H.
Then the instruction
MOV
AL, [BX][SI]
Page 29 of 35
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
Lecture Four
8086 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
MOV
AL, DISP[BX][SI]
MOV
AL, DISP[BX+DI]
MOV
AL, [BP+SI+DISP]
MOV
AL, [BP][DI][DISP]
Suppose
BP = 1000H,
BX =2000H,
SI = 120H, and DI = 5.
Then
MOV AL, 10H[BX+SI]
loads AL from
address DS:2130;
MOV CH, 125H[BP+DI] loads CH from location SS:112A;
MOV BX, CS:2[BX][DI] loads BX from location CS:2007.
Page 30 of 35
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
Lecture Four
8086 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
The DATA TRANSFER INSTRUCTIONS are those, which transfers the DATA
from any one source to any one destination. The datas may be of any type. They are
again classified into four groups. They are:
General Purpose
Special Address
Flag Transfer
Byte Or Word
Output Port
Transfer
Instructions
Instruction
MOV
LEA
LAHF
PUSH
IN
LDS
SAHF
POP
OUT
LES
PUSHF
XCHG
POPF
XLAT
2. ARITHMETIC INSTRUCTIONS
These instructions are those which are useful to perform Arithmetic calculations,
such as addition, subtraction, multiplication and division. They are again classified into
four groups. They are:
Addition
Subtraction
Multiplication
Division
Instructions
Instructions
Instructions
Instructions
ADD
SUB
MUL
DIV
ADC
SBB
IMUL
IDIV
INC
DEC
AAM
AAD
AAA
NEG
CBW
DAA
CMP
CWD
AAS
DAS
SHIFT
Page 31 of 35
ROTATE
University of Technology
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Microprocessor Engineering & Microcontroller
Lecture Four
8086 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
SHL / SAL
ROL
AND
SHR
ROR
OR
SAR
RCL
XOR
RCR
TEST
4. STRING INSTRUCTIONS
The string instructions function easily on blocks of memory. They are user friendly
instructions, which help for easy program writing and execution. They can speed up the
manipulating code. They are useful in array handling, tables and records.
STRING INSTRUCTIONS
REP
REPE
REPZ
REPNE
REPNZ
MOVS
MOVSB
MOVSW
SCASB
SCASW
LODS
LODSB
LODSW
Page 32 of 35
University of Technology
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Microprocessor Engineering & Microcontroller
Unconditional
Transfer
Instructions
CALL
RET
JMP
Lecture Four
8086 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
Conditional Transfer
Instructions
JA /
JNBE
JAE /
JNB
JB /
JNAE
JBE /
JNA
JC
JE / JZ
JG /
JNLE
JGE /
JNL
JL /
JNGE
Iteration Control
Instructions
LOOP
JLE / JNG
LOOPE / LOOPZ
JNC
LOOPNE
/ LOOPNZ
JNE / JNZ
JCXZ
JNO
JNP / JPO
JNS
JO
JP / JPE
JS
Interrupt
Instructions
INT
INTO
IRET
External Hardware
Synchronization Instructions
STC
CLC
CMC
STD
CLD
STI
CLI
HLT
WAIT
ESC
LOCK
NOP
Page 33 of 35
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
Lecture Four
8086 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
11.
12.
13.
Which is the tool used to connect the user and the computer?
14.
What is the position of the Stack Pointer after the PUSH instruction?
15.
What is the position of the Stack Pointer after the POP instruction?
16.
17.
18.
19.
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
Lecture Four
8086 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
20.
Which Segment is used to store interrupt and subroutine return address registers?
21.
Which Flags can be set or reset by the programmer and also used to control the
22.
23.
Which microprocessor accepts the program written for 8086 without any changes?
24.
Exercise
Write an 8086 Program to
Page 35 of 35
Lecture Five
80386 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
80386 Microprocessor
The third x86 generation of x86 microprocessors, Intel 80386 (i386) was a 32-bit
microprocessor backwards compatible with previous generations of 80x86 CPUs. Major
new feature in the i386 CPU was 80386 protected mode - this mode fixed many
shortcomings that existed in the 80286 processor and in the 80286 protected mode:
The 80386 mode included complete set of 32-bit registers and 32-bit instructions.
Although in this mode the CPU still used memory segment architecture similar to the one
present in earlier x86 microprocessors, the size of memory segments was increased to 4
GB. This simplified development of 32-bit software, and in most cases applications could
run without worrying about switching memory segments.
It became possible to switch from protected mode back to real-mode without simulating
processor reset.
Another new mode in the 80386 CPU was 8086 virtual mode. In this mode the CPU
could run old 8086 applications while providing necessary protection of memory and
other resources. Introduction of this mode and 80386 protected mode was very
significant step. All current 32-bit x86-based operating systems use these modes to run
legacy 16-bit and more modern 32-bit applications.
The Intel 80386 was produced at speeds up to 33 MHz, AMD produced even faster 40
MHz version.
There were a few different versions of the 80386 CPUs:
80386DX - this CPU could work with 16-bit and 32-bit external buses.
80386SX - low cost version of the 80386. This processor had 16 bit external
data bus and 24-bit external address bus.
80386SL - low-power microprocessor with power management features, with
16-bit external data bus and 24-bit external address bus. The processor
included ISA bus controller, memory controller and cache controller.
Embedded 80376 and 80386EX processors.
Page 1 of 43
Lecture Five
80386 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
Page 2 of 43
Lecture Five
80386 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
Page 3 of 43
Lecture Five
80386 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
HLDA: The bus Hold Acknowledge output indicates that a valid bus hold request
has been received and the bus has been relinquished by the CPU.
BUSY : The Busy input signal indicates to the CPU that the coprocessor is busy with
the allocated task.
ERROR : The error input pin indicates to the CPU that the coprocessor has
encountered an error while executing its instruction.
PEREQ: The coprocessor request asks the 80386 to relinquish control and is a
direct connection to the 80387 arithmetic coprocessor.
INTR: This interrupt request pin is a maskable interrupt, that can be masked using
the IF of the flag register.
NMI: A non Maskable Interrupt requests a non-maskable interrupt as it did on the
earlier versions of the microprocessor.
RESET: A high at this input pin suspends the current operation and restart the
execution from the starting location.
N/C: No connection pins are expected to be left open while connecting the 80386 in
the circuit.
M IO
when a logic 0. During the I/O operation, the address bus contains a 16 bit I/O
address on address connections A15-A2.
W R : Write/ Read indicates that the current bus cycle is a write when a logic 1 or a
read when a logic 0.
LOCK : Lock becomes a logic 0 whenever an instruction is prefixed with the LOCK:
prefix. This is used most ofen during DMA accesses.
D C : Data/Control indicates that the data bus contains data for or from memory or
I/O when a logic 1. If D C is a logic 0, the microprocessor is halted or executes an
interrupt acknowledge.
NA : Next Address causes the 80386 to output the address of the next instruction or
data in the current bus cycle. This pin is often used for pipelining the address.
Page 4 of 43
Lecture Five
80386 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
80386
Processor
Page 5 of 43
Lecture Five
80386 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
Page 6 of 43
Lecture Five
80386 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
Prefetch Unit
Instructions stored in FIFO queue
Holds code until ready for decoding
Whenever the queue is not full, prefetch the next sequential instructions
Time to fetch many of the instructions in a microcomputer program is
hidden.
Page 7 of 43
Lecture Five
80386 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
Decode Unit
Offloads the responsibility of instruction decoding from the execution unit
Decodes instructions into the microcode instruction format used by the
execution unit
Contains another instruction queue that holds 3 fully decoded instructions
Decoded instructions are held until requested by the execution unit
Execution Unit
Responsible for executing instructions
Element of the EU
Arithmetic/logic unit (ALU)
Performs the operation identified by the instruction: ADD, SUB,
AND, etc.
Flags register
Holds status and control information
General-purpose registers
Holds address or data information
Control ROM
Contains microcode sequences that define operations performed by
machine instructions
Special multiply, shift, and barrel shift hardware
Accelerate multiply, divide, and rotate operations
Page 8 of 43
Lecture Five
80386 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
Page 9 of 43
Lecture Five
80386 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
Register set
Memory address space
Input/output address space
Could also consider operations processor can perform
What the programmer must know about the microprocessor
Registers available within the device
Purpose, operating capabilities of each
Size, organization of memory and I/O address spaces
Types of data
Page 10 of 43
Lecture Five
80386 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
two index registers (ESI, EDI) and two pointer registers (EBP, ESP);
ESI (extended source index register) and EDI (extended destination index
register)
Instruction Pointer
Page 11 of 43
Lecture Five
80386 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
FLAGS REGISTER
32-bit flags; just nine of its bits are active in the real mode
1. Statues Flag:
Carry flag(CF): carry-out, borrow-in
Parity flag (PF): set if even parity
Auxiliary carry flag (AF): carry-out from the low nibble
Zero flag(ZF): arithmetic or logic 0
Sign bit (SF): sign
Overflow flag (OF): the signed result is out of range
2. Control Flag:
Direction flag (DF): string operation; when set, the string ops automatically
decrements the address.
TF (Trap Flag): Setting TF puts the processor into single-step mode for
debugging. In
each
the
80386.
IF (Interrupt-Enable Flag, bit 9): Setting IF allows the CPU to recognize external
(maskable) interrupt
effect on
3. Systems Flags
Page 12 of 43
Lecture Five
80386 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
NT (Nested Task, bit 14): The processor uses the nested task flag to control
chaining of
instruction.
RF (Resume Flag, bit 16): The RF flag is used with the debug register
breakpoints. It is checked at the starting of every instruction cycle and if it is set,
any debug fault is ignored during the instruction cycle. The RF is automatically
reset after successful execution of every instruction, except for IRET and POPF
instructions.
VM (Virtual 8086 Mode, bit 17): If this flag is set, the 80386 enters the virtual
8086 mode within the protection mode. This is to be set only when the 80386 is in
protected mode. In this mode, if any privileged instruction is executed an exception
13 is generated. This bit can be set using IRET instruction or any task switch
operation only in the protected mode.
Systems Registers
The registers designed for use by systems programmers fall into these classes:
Memory-Management Registers
Control Registers
Debug Registers and Test Registers
Memory-Management Registers
Four registers of the 80386 locate the data structures that control segmented
memory management:
GDTR (Global Descriptor Table Register) / LDTR (Local Descriptor Table Register)
These registers point to the segment descriptor tables GDT and LDT.
IDTR (Interrupt Descriptor Table Register)
This register points to a table of entry points for interrupt handlers
TR
(the IDT).
(Task Register)
This register points to the information needed by the processor to define the current
task. Refer to Chapter 7 for a description of the
Page 13 of 43
Lecture Five
80386 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
Control Registers
The 80386 has three 32 bit control registers CR0, CR2 and CR3 to hold global
machine status independent of the executed task. Load and store instructions are
available to access these registers.
Address Space
Memory organized as individual bytes
Memory address space corresponds to the
1M addresses in the range 00000H to
FFFFFH
00000H= 000000000000000000002
FFFFFH= 111111111111111111112
220= 1,048,576 = 1M unique addresses
Data organization:
Byte: content of any individual byte
address
Page 14 of 43
Lecture Five
80386 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
Page 15 of 43
Lecture Five
80386 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
Page 16 of 43
Lecture Five
80386 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
Fig. (4):
Page 17 of 43
Lecture Five
80386 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
Page 18 of 43
Lecture Five
80386 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
Page 19 of 43
Lecture Five
80386 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
In virtual mode, the paging mechanism and protection capabilities are available at
the service of the programmers.
The 80386 supports multiprogramming, hence more than one programmer may be
using the CPU at a time.
Page 20 of 43
Lecture Five
80386 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
However, the real mode programs are executed at the highest privilege level,
i.e. level 0.
The virtual mode may be entered using an IRET instruction at CPL=0 or a task
switch at any CPL, executing any task whose TSS is having a flag image with
VM flag set to 1.
The IRET instruction may be used to set the VM flag and consequently enter
the virtual mode.
The PUSHF and POPF instructions are unable to read or set the VM bit, as
they do not access it.
Even in the virtual mode, all the interrupts and exceptions are handled by the
protected mode interrupt handler.
To return to the protected mode from the virtual mode, any interrupt or
execution may be used.
As a part of interrupt service routine, the VM bit may be reset to zero to pull
back the 80386 into protected mode.
Page 21 of 43
Lecture Five
80386 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
XCHG (Exchange) swaps the contents of two operands. This instruction takes the place
of three MOV instructions. It does not require a temporary location to save the contents
of one operand while load the other is being loaded. XCHG is especially useful for
implementing semaphores or similar data structures for process synchronization.
The XCHG instruction can swap two byte operands, two word operands, or two
doubleword operands. The operands for the XCHG instruction may be two register
operands, or a register operand with a memory operand. When used with a memory
operand, XCHG automatically activates the LOCK signal. (Refer to Chapter 11 for more
information on the bus lock.)
Page 22 of 43
Lecture Five
80386 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
EAX
register.
2. The forms MOVSX and MOVZX, which permit one operand to be in any general
register while permitting the other operand to be in memory or in a register.
Page 23 of 43
Lecture Five
80386 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
CWD (Convert Word to Double word) and CDQ (Convert Double word to Quad-Word)
double the size of the source operand. CWD extends the sign of the word in register AX
throughout register DX. CDQ extends the sign of the double word in EAX throughout
EDX. CWD can be used to produce a double word dividend from a word before a word
division, and CDQ can be used to produce a quad-word dividend from a double word
before double word division.
CBW (Convert Byte to Word) extends the sign of the byte in register AL throughout AX.
CWDE (Convert Word to Double word Extended) extends the sign of the word in
register AX throughout EAX.
MOVSX (Move with Sign Extension) sign-extends an 8-bit value to a 16-bit value and a
8- or 16-bit value to 32-bit value.
MOVZX (Move with Zero Extension) extends an 8-bit value to a 16-bit value and an 8or 16-bit value to 32-bit value by inserting high-order zeros.
Page 24 of 43
Lecture Five
80386 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
borrowed) into the high-order bit (subtraction instructions SUB, SBB, AAS, DAS, CMP,
and NEG).
If the integer is signed, both SF and OF should be tested. SF always has the same value
as the sign bit of the result. The most significant bit (MSB) of a signed integer is the bit
next to the sign--bit 6 of a byte, bit 14 of a word, or bit 30 of a doubleword. OF is set in
either of these cases:
A one-bit was carried out of the MSB into the sign bit but no one bit
of the sign bit (addition instructions ADD, ADC, INC, AAA, and DAA). In other words, the
result was greater than the greatest positive number that could be contained in the
destination operand.
A one-bit was carried from the sign bit into the MSB but no one bit was carried into
the sign bit (subtraction instructions SUB, SBB, DEC, AAS, DAS, CMP, and NEG). In
other words, the result was smaller that the smallest negative number that could be
contained in the destination operand.
These status flags are tested by executing one of the two families of conditional
instructions: Jcc (jump on condition cc) or SETcc (byte set on condition).
Page 25 of 43
Lecture Five
80386 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
operand. If CF is cleared, SBB performs the same operation as SUB. SUB followed by
multiple SBB instructions may be used to subtract numbers longer than 32 bits. If CF is
cleared, SBB performs the same operation as SUB.
DEC (Decrement) subtracts 1 from the destination operand. DEC does not update CF.
Use SUB with an immediate value of 1 to perform a decrement that affects carry.
Multiplication Instructions
The 80386 has separate multiply instructions for unsigned and signed operands. MUL
operates on unsigned numbers, while IMUL operates on signed integers as well as
unsigned.
MUL (Unsigned Integer Multiply) performs an unsigned multiplication of the source
operand and the accumulator. If the source is a byte, the processor multiplies it by the
contents of AL and returns the double-length result to AH and AL. If the source operand
is a word, the processor multiplies it by the contents of AX and returns the double-length
result to DX and AX. If the source operand is a double word, the processor multiplies it
by the contents of EAX and returns the 64-bit result in EDX and EAX. MUL sets CF and
OF when the upper half of the result is nonzero; otherwise, they are cleared.
IMUL (Signed Integer Multiply) performs a signed multiplication operation. IMUL has
three variations:
1. A one-operand form. The operand may be a byte, word, or double word located in
memory or in a general register. This instruction uses EAX and EDX as implicit
operands in the same way as the MUL instruction.
Page 26 of 43
Lecture Five
80386 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
register
3. A three-operand form; two are source and one is the destination operand. One of
the source operands is an immediate value stored in the instruction; the second
may be in memory or in any general register. The product may be stored in any
general register. The immediate operand is treated as signed. If the immediate
operand is a byte, the processor automatically sign-extends it to the size of the
second operand before performing the multiplication.
The three forms are similar in most respects:
The length of the product is calculated to twice the length of the operands.
The CF and OF flags are set when significant bits are carried into the
high-order
half of the result. CF and OF are cleared when the high-order half of the result is the
sign-extension of the low-order half.
However, forms 2 and 3 differ in that the product is truncated to the length of the
operands before it is stored in the destination register. Because of this truncation, OF
should be tested to ensure that no significant bits are lost. (For ways to test OF, refer to
the INTO and PUSHF instructions)
Forms 2 and 3 of IMUL may also be used with unsigned operands because, whether the
operands are signed or unsigned, the low-order half of the product is the same.
Division Instructions
The 80386 has separate division instructions for unsigned and signed operands.
DIV operates on unsigned numbers, while IDIV operates on signed integers as well as
unsigned. In either case, an exception (interrupt zero) occurs if the divisor is zero or if the
quotient is too large for AL, AX, or EAX.
DIV (Unsigned Integer Divide) performs an unsigned division of the accumulator by the
source operand. The dividend (the accumulator) is twice the size of the divisor (the
source operand); the quotient and remainder have the same size as the divisor, as the
following table shows.
Page 27 of 43
Lecture Five
80386 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
Dividend
Quotient
Remainder
Byte
AX
AL
AH
Word
DX:AX
AX
DX
Double word
EDX:EAX
EAX
EDX
produce a valid
that the
result.
These instructions operate only on the AL or AH registers. Most utilize the AF flag.
Lecture Five
80386 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
DAA (Decimal Adjust after Addition) adjusts the result of adding two valid packed
decimal operands in AL. DAA must always follow the addition of two pairs of packed
decimal numbers (one digit in each half-byte) to obtain a pair of valid packed decimal
digits as results. The carry flag is set if carry was needed.
DAS (Decimal Adjust after Subtraction) adjusts the result of subtracting two valid packed
decimal operands in AL. DAS must always follow the subtraction of one pair of packed
decimal numbers (one digit in each halfbyte) from another to obtain a pair of valid packed
decimal digits as results. The carry flag is set if a borrow was needed.
3. Logical Instructions
The group of logical instructions includes:
Page 29 of 43
Lecture Five
80386 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
The Boolean operation instructions: they are AND, OR, XOR, and NOT.
Bit test and modify instructions
Bit scan instructions
Rotate and shift instructions
Byte set on condition
Bit Test and Modify Instructions
This group of instructions operates on a single bit which can be in memory or in a
general register. The location of the bit is specified as an offset from the low-order end of
the operand. The value of the offset either may be given by an immediate byte in the
instruction or may be contained in a general register.
These instructions first assign the value of the selected bit to CF, the carry flag. Then a
new value is assigned to the selected bit, as determined by the operation. OF, SF, ZF,
AF, PF are left in an undefined state. Table 1 defines these instructions.
Effect on CF
CF BIT
(none)
CF BIT
CF BIT
BIT 0
CF BIT
BIT NOT(BIT)
BIT 1
Page 30 of 43
Lecture Five
80386 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
BSR (Bit Scan Reverse) scans from high-order to low-order (starting from bit index 15
of a word or index 31 of a doubleword).
Shift Instructions
The bits in bytes, words, and doublewords may be shifted arithmetically or logically.
Depending on the value of a specified count, bits can be shifted up to 31 places.
A shift instruction can specify the count in one of three ways. One form of shift
instruction implicitly specifies the count as a single shift. The second form specifies
the count as an immediate value. The third form specifies the count as the value
contained in CL. This last form allows the shift count to be a variable that the program
supplies during execution. Only the low order 5 bits of CL are used.
SAL (Shift Arithmetic Left)/ SHL (Shift Logical Left): The SHL and SAL mnemonics
are synonyms. They represent the same instruction and use identical binary encodings.
These instructions move each bit in the destination operand one bit position to the left
the number of times specied by the count operand. Zeros ll vacated positions at the
L.O. bit; the H.O. bit shifts into the carry ag
SHR (Shift Logical Right) shifts the destination byte, word, or doubleword operand right
by one or by the number of bits specified in the count operand (an immediate value or
Page 31 of 43
Lecture Five
80386 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
the value contained in CL). The processor shifts zeros in from the left side of the operand
as bits exit from the right side.
SAR (Shift Arithmetic Right) shifts the destination byte, word, or doubleword operand
to the right by one or by the number of bits specified in the count operand (an immediate
value or the value contained in CL). The processor preserves the sign of the operand by
shifting in zeros on the left (high-order) side if the value is positive or by shifting by ones
if the value is negative.
SHLD (Shift Left Double) shifts bits of the R/M field to the left, while shifting high-order
bits from the Reg field into the R/M field on the right (see Figure 3-10). The result is
stored back into the R/M operand. The Reg field is not modified.
SHRD (Shift Right Double) shifts bits of the R/M field to the right, while shifting loworder bits from the Reg field into the R/M field on the left (see Figure 3-11). The result is
stored back into the R/M operand. The Reg field is not modified.
Page 32 of 43
Lecture Five
80386 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
Example:
Rotate Instructions
Rotate instructions allow bits in bytes, words, and doublewords to be rotated. Bits
rotated out of an operand are not lost as in a shift, but are "circled" back into the other
"end" of the operand.
ROL (Rotate Left) rotates the byte, word, or doubleword destination operand left by one
or by the number of bits specified in the count operand (an immediate value or the value
contained in CL).
Page 33 of 43
Lecture Five
80386 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
ROR (Rotate Right) rotates the byte, word, or doubleword destination operand right by
one or by the number of bits specified in the count operand (an immediate value or the
value contained in CL).
RCL (Rotate Through Carry Left) rotates bits in the byte, word, or doubleword
destination operand left by one or by the number of bits specified in the count operand
(an immediate value or the value contained in CL).
RCR (Rotate Through Carry Right) rotates bits in the byte, word, or doubleword
destination operand right by one or by the number of bits specified in the count operand
(an immediate value or the value contained in CL).
Byte-Set-On-Condition Instructions
The set on condition (or setcc) instructions set a single byte operand (register or
memory location) to zero or one depending on the values in theags register. The
general formats for the setcc instructions are
Page 34 of 43
Lecture Five
80386 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
SETcc reg8
SETcc mem8
SETcc represents a mnemonic appearing in the following tables. These instructions store
a zero into the corresponding operand if the condition is false, they store a one into the
eight bit operand if the condition is true.
Table 2: SETcc Instructions That Test Flags
The CMP instruction works synergistically with the SETcc instructions. Immediately
after a CMP operation the processor ags provide information concerning the relative
values of those operands. They allow you to see if one operand is less than, equal to,
greater than, or any combination of these.
There are two groups of SETcc instructions that are very useful after a CMP operation.
The rst group deals with the result of an unsigned comparison, the second group deals
with the result of a signed comparison.
Page 35 of 43
Lecture Five
80386 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
Page 36 of 43
Lecture Five
80386 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
4. Input/Output Instructions
The 80x86 supports two I/O instructions: in and out.They take the forms:
IN eax/ax/al, port
IN eax/ax/al, dx
OUT port, eax/ax/al
OUT dx, eax/ax/al
port is a value between 0 and 255. The 80x86 supports up to 65,536 different I/O
ports (requiring a 16 bit I/O address).
The port value above, however, is a single byte value. Therefore, you can only
directly address the rst 256 I/O ports in the 80x86s I/O address space. To address
all 65,536 different I/O ports, you must load the address of the desired port (assuming
its above 255) into the dx register and access the port indirectly.
The in instruction reads the data at the specied I/O port and copies it into the
accumulator. The out instruction writes the value in the accumulator to the speci
ed
I/O port.
5. String Instructions
The 80386 supports twelve string instructions:
MOVS (move string)
LODS (load string element into the accumulator)
STOS (store accumulator into string element)
SCAS (Scan string and check for match against the value in the accumulator)
CMPS (compare two strings)
INS (input a string from an I/O port)
OUTS (output a string to an I/O port
REP (repeat a string operation)
REPZ (repeat while zero)
REPE (repeat while equal)
REPNZ (repeat while not zero)
REPNE (repeat while not equal)
Page 37 of 43
Lecture Five
80386 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
You can use the MOVS, STOS, SCAS, CMPS, INS and OUTS instructions to manipulate
a single element (byte, word, or double word) in a string, or to process an entire string.
Generally, you would only use the LODS instruction to manipulate a single item at a time.
These instructions can operate on strings of bytes, words, or double words. To specify
the object size, simply append a b, w, or d to the end of the instructions mnemonic, i.e.,
LODSB, MOVSW, CMPSD, etc. Of course, the double word forms are only available on
80386 and later processors
Jump Instruction
JMP (Jump) unconditionally transfers control to the target location. JMP is a oneway transfer of execution; it does not save a return address on the stack.
The JMP instruction always performs the same basic function of transferring control from
the current location to a new location. Its implementation varies depending on whether
the address is specified directly within the instruction or indirectly through a register or
memory.
Page 38 of 43
Lecture Five
80386 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
A direct JMP instruction includes the destination address as part of the instruction. An
indirect JMP instruction obtains the destination address indirectly through a register or a
pointer variable.
Direct near JMP. A direct JMP uses a relative displacement value contained in the
instruction. The displacement is signed and the size of the displacement may be a byte,
word, or doubleword. The processor forms an effective address by adding this relative
displacement to the address contained in EIP. When the additions have been performed,
EIP refers to the next instruction to be executed.
Indirect near JMP. Indirect JMP instructions specify an absolute address in one of
several ways:
1. The program can JMP to a location specified by a general register
(any of EAX,
EDX, ECX, EBX, EBP, ESI, or EDI). The processor moves this 32-bit value into EIP and
resumes execution.
2. The processor can obtain the destination address from a memory operand specified
in the instruction.
3. A register can modify the address of the memory pointer to select a destination
address.
Call Instruction
CALL (Call Procedure) activates an out-of-line procedure, saving on the stack the
address of the instruction following the CALL for later use by a RET (Return) instruction.
CALL places the current value of EIP on the stack. The RET instruction in the called
procedure uses this address to transfer control back to the calling program.
CALL instructions, like JMP instructions have relative, direct, and indirect versions.
Indirect CALL instructions specify an absolute address in one of these ways:
1. The program can CALL a location specified by a general register (any of EAX, EDX,
ECX, EBX, EBP, ESI, or EDI). The processor moves this
2. The processor can obtain the destination address from a memory operand specified
in the instruction.
Page 39 of 43
Lecture Five
80386 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
Page 40 of 43
Lecture Five
80386 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
Page 41 of 43
Lecture Five
80386 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
Loop Instructions
The loop instructions are conditional jumps that use a value placed in ECX to
specify the number of repetitions of a software loop. All loop instructions automatically
decrement ECX and terminate the loop when ECX=0. Four of the five loop instructions
specify a condition involving ZF that terminates the loop before ECX reaches zero.
LOOP (Loop While ECX Not Zero) is a conditional transfer that automatically
decrements the ECX register before testing ECX for the branch condition. If ECX is nonzero, the program branches to the target label specified in the instruction. The LOOP
instruction causes the repetition of a code section
until the operation of the LOOP instruction decrements ECX to a value of zero. If LOOP
finds ECX=0, control transfers to the instruction immediately following the LOOP
instruction. If the value of ECX is initially zero, then the LOOP executes 232 times.
LOOPE (Loop While Equal) and LOOPZ (Loop While Zero) are synonyms for the same
instruction. These instructions automatically decrement the ECX register before testing
ECX and ZF for the branch conditions. If ECX is non-zero and ZF=1, the program
branches to the target label specified in the instruction. If LOOPE or LOOPZ finds that
Page 42 of 43
Lecture Five
80386 Microprocessor
Assist.Prof. Dr. Hadeel Nasrat
University of Technology
Electrical Eng. Department
Microprocessor Engineering & Microcontroller
ECX=0 or ZF=0, control transfers to the instruction immediately following the LOOPE or
LOOPZ instruction.
LOOPNE (Loop While Not Equal) and LOOPNZ (Loop While Not Zero) are synonyms
for the same instruction. These instructions automatically decrement the ECX register
before testing ECX and ZF for the branch conditions. If ECX is non-zero and ZF=0, the
program branches to the target label specified in the instruction. If LOOPNE or LOOPNZ
finds that ECX=0 or ZF=1, control transfers to the instruction immediately following the
LOOPNE or LOOPNZ instruction.
7. Miscellaneous Instructions
There are various miscellaneous instructions on the 80x86 that dont fall into any
category above. Generally these are instructions that manipulate individual ags, provide
special processor services, or handle privileged mode operations.
There are several instructions that directly manipulateags in the 80x86 ags register.
They are
clc Clears the carry ag
stc Sets the carry ag
cmc Complements the carry ag
cld Clears the direction ag
std Sets the direction ag
cli Clears the interrupt enable/disable ag
sti Sets the interrupt enable/disable ag
Note: you should be careful when using the cli instruction in your programs. Improper
use could lock up your machine until you cycle the power.
The nop instruction doesnt do anything except waste a few processor cycles and take
up a byte of memory. Programmers often use it as a place holder or a debugging aid. As
it turns out, this isnt a unique instruction, its just a synonym for the
instruction.
Page 43 of 43
xchg ax, ax