Documenti di Didattica
Documenti di Professioni
Documenti di Cultura
Dr. M S Bhat
By
Aamodh K (15VL01F)
Arjun S Kumar (15VL04F)
(M.Tech VLSI Design)
Submitted to
ABSTRACT
Simulated annealing is a general adaptive heuristic and belongs to the class
of non-deterministic algorithms. It has been applied to several combinatorial
problems from various fields of science and engineering.
This report discusses how simulated annealing can be applied to very largescale integration (VLSI) cell placement problem in order to minimize
wirelength and chip area. The algorithm is applied to full custom layout
design. Perl and Python coding languages have been used to implement the
algorithm.
Page 1
CONTENTS
ABSTRACT
CONTENTS
LIST OF FIGURES
1. Problem Statement
2. Simulated Annealing
2.1 Introduction
4.
7
7
10
Simulation Results
REFERENCES
11
13
Page 2
LIST OF FIGURES
Figure 1: Typical graph of cost vs No. of configurations examined
11
11
12
12
Page 3
1. Problem Statement
1.1 Need for heuristic algorithm
VLSI cell placement problems are known to be NP complete. Trying to get an
exact solution by evaluating every possible placement to determine the best
one would take time proportional to the factorial of the number of modules.
This method is, therefore, impossible to use for circuits with any reasonable
number of modules. A wide range of heuristic algorithms exist in the
literature for efficiently arranging the logic cells on VLSI chip. Simulated
annealing is once such method. A strong feature of simulated annealing
method is that it is both effective and robust.
Chip area usage needs to be optimized in order to fit more functionality into
a given chip area.
goals
are
closely
related
since
minimizing
the
chip
area
will
Page 4
2. Simulated Annealing
2.1 Introduction
travelling
salesman
problem,
graph
partitioning,
quadratic
Page 5
cost reduction are accepted, and the algorithm converges to a low cost
configuration.
begin
T = initial_temperature;
P = initial_placement;
while (T > final_temperature) do
while (number_of_trials < trial_limit) do
new_P = PERTURB(P);
C = COST(new_P) COST(P);
if (C < 0) then
P = new_P;
elsif (random(0,1) > exp(C /T)) then
P = new_P;
T = SCHEDULE(T);
end
Page 6
We start our annealing procedure by placing the cells on the chip randomly.
We place the cells randomly so that the placement is not optimal. The initial
area occupied by the chip is calculated.
Since the cells are placed randomly thus, the distances between them and
the length of their interconnection will be huge. Next we will use the 3
different functions to get the optimal placement for the chip.
This is the PERTURB function in pseudo code. To generate a new possible cell
placement, we use two strategies
a. Move single cell randomly to a new location on the chip.
b. Swap the position of two cells
c. Rotate single cell by 900
Page 7
In our algorithm we use all three strategies randomly but with fixed
probability.
This is the COST function in pseudo code. The cost function in our algorithm
is comprised of two components
= 1+ 2
c1 is a measure of the total estimated wire-length. For any cell, we find out
the wire-length by calculating the horizontal and the vertical distance
between it and its out cell.
Let Dh(i,j) be the horizontal distance between cell i and its jth out cell and
Dv(i,j) be the vertical distance between cell i and its jth out cell, therefore
the total wire length for the chip can be derived by the following
mathematical expression
( ( , ) +
1=
( , ))
When a cell is swapped or rotated it may so happen that two cells overlap
with each other. Let O(I,j) indicate the overlap between two cells. Clearly
this overlap is undesirable and should be minimized. In order to penalize the
overlap severely we square the overlap so that we get larger penalties for
overlaps. The overlap penalty c2 is given by
( ( , ))
!
Page 8
Thus when we generate a new move we calculate the cost function for the
newly generated move. If we find that the new move has a cost lesser than
the previous best move, we accept it as the best move. But if we find a
solution that is not cost optimal, we do not reject it completely. We define an
Accept function which is the probabilistic acceptance function It determines
whether to accept a move or not. We have implemented an exponential
function for the accept method. We are accepting a non cost optimal solution
because we are giving the annealing schedule a chance to move out of a
local minimum which it may have hit.
For example, if a certain annealing schedule hits point B (local minima) and
if we do not accept a non cost optimal solution, then the annealing cannot
reach the global minima. By using the accept function we are giving the
annealing schedule a chance to get out of the local minima. As a nature of
the accept function used by us, the probability of accepting non cost optimal
Page 9
This is the schedule function in pseudo code. At first we start the annealing
procedure from a very high temperature 20,000K. We reduced our
temperature using
Tnew = T * T
T, the cooling rate is fixed by us. Initially we rapidly decreased the
temperature (T 0.8). In the middle portion of the annealing schedule we
reduced the temperature slowly (T 0.95), since this phase takes up the
maximum ( 75%) of the annealing schedule. In the low temperature, the
temperature is decreased rapidly again(T 0.8). The stopping condition is
when the temperature falls below 100K.
Within each temperature range we experimentally set the number of moves.
Once the number of moves is set, we fix it for the remainder of the
scheduling. For example in our code we have set the number of iterations for
the algorithm at 5*Number_of_Cells.
Page 10
4. Simulation results
Page 11
Page 12
REFERENCES
[1] C.Sechen and A.Sangiovanni-Vincentelli, The TimberWolf Placement and
Routing Package, IEEE Journal of Solid State Circuits, Vol. SC-20, No. 2,
April 1985.
Page 13