Low-Voltage, Low-Power and Highly-Tunable

1.8GHz CMOS LC Voltage Controlled Oscillator

L.Bouzerara, M.T.Belaroussi
Microelectronics and Nanotechnologies Division, Centre de Eveloppement des Technotogies Avancks
Cite 20 Aofit 1956, BP. 17,16303, Baba Hassen, Algiers, ALGERIA
bouzerara.lyes@lycos.com, mtbelaroussi@cdta.dz
Ahtruct- A fully integrated 1.8 CHz low phase noise LC-tank
W O i s presented and analyzed. Tho phase noise of the oscillator
has been greatly reduced by means of integrated source
degeneration inductors. The phase noise achieved is -105, -123
and -138 dWHz a t 100 KHz, 600 KHz and 3 MHz offsets
respectively from the carrier frequency of 1.6 CHz, with 1.8 V
power supply volfage and giving a low power consumption of only
2.8 mW by considering the p r o w VCO topology, which
consumes less power than the conventional differential
transconductor pair. A 15.8% broad tuning range has been
achieved by using the standard mode PMOS vnroctors in the
designed voltage tontrollod oscillator architecture. The tunability
of the designed VCO covers 290 MHz, from 1.69 CH2 up to 1.98
CHz w i I ~VCO gain Kvco of 320 MHzN.

I.

INTRODUCTION

The fast emerging of modem telecommunication systems,

such as DCS-1800, GSM-celldar telephones, and the DECT
cordless telephones, has caused an increase in the demand for
low cost and hi& performance integrated radio-frequency
transceivers. Of all RF building blocks, voltage-controlled
oscillators are considered as the key element and have gained
the most attention in recent years. Although most commercial
designs use bipolar or GaAs technologies, CMOS is a
promising candidate for full integration of RF front-ends, due to
its relatively low production cost. The design of high
performance monolithic VCOs in standard CMOS processes
has been the topic of several active research efforts [ 1-81. The
principal aim is to design a very low phase noise and low power
VCO With high tuning range, able to fulfill the tight
specifications of most RF portable communication systems. A
major challenge in the design of CMOS transceiver systems i s
the Phase-Locked-Loop Frequency synthesizer that generates
the local oscillator carrier signal. The 'phase noise of the
synthesizer is the most critical parameter for the quality and
reliability of the information transfer. It is well known that the
phase noise performance of a PLL is essentially determined by
the phase noise of the VCO. Due to the vety narrow
communication channel spacings, the output signal of the PLL
must be a very pure sinusoid. It is therefore of major importance
to design a low power, low-phase-noise oscillator. L C - d
voltage-controlled oscillator is a better choice than relaxation or
ring oscillators to fulfill the stringent high frequency and noise
specifications [I, 21, [6-8]. A monolithic LC-tank VCO

0-7803-9029-6/05/$20.00
02005 f E

requires the integration of high quality passive components such

as inductors and varactors in standard CMOS technology. The
design becomes more challenging, when a hgh hming range is
n e c e s q to provide the required frequency band over process
varktions. The cambination of a Wide tunkg range and low
power supply voltage requires a high VCO gain, which makes
the oscillator much more sensitive to voltage noise induced
phase noise. The use of integrated degeneration inductors has
proven very effective to reduce the phase noise of the oscillator
[4, 51. The present work applies the above idea to the
symetncal architecture-ofthe LC-tank VCO.
In this paper, 3 l l l y integrated l.8GHz voltage ~ ~ n t r ~ l l e d
oscillator, tuned by PMOS varactors, is presented and analyzed
that combines a wide t"g range at very low power supply
voltage with a low phase noise performance and stdl achieves
the specifications necessary for DCS-1800, GSM and DECT
mobile communication 'systems. Among major issues in
designing a voltage controlled oscillator is its power
consumption. It is therefore imperative that the' power
consumption of the VCO be minimized to lower overall power
consumption of low power wireless systems. For this purpose,
the proposed VCO topology exploits the concept of new linear
and low power differential transconductor architectures [9, 101,
connected to act as negative resistors, wtuch consume less
power than the classical LC oscillator using,the conventional
differential transconductor pair. The paper is organized as
follows: in section 2, the propoxd designed VCO circuit is
presented and analyzed. In section 3, the obtained results are
depicted while in last section, are presented the conclusions and
perspectives.
11. .ANALYSIS
OF THE DESIGNED
CMOS LC VCO
Generally, the quality factor of an LC oscillator, which is
mainly determined by the inductor in the resonator, is especialIy
important due to its effect on the globat pbse noise
performance of the voltage controlIed oscillator. A simplified
equation for oscillator phase noise presents the relation between
the quality factor and the output power of the signal produced
by the oscillator, to the normalized single side-band noise
spectral density [I 1, 121:

3 87

where L{w} is phase noise in d l 3 c f i ; k is Boltzmann's

constant; T is Temperature in K; P is oscillator signal output
power in W;
is offset frequency from the carrier in Hz; fa is
oscillation frequency in Hz;Q is quality factbr of the tank, F
represents a noise factor and fc is corner frequency. The above
equation shows clearly the importance of the tank circuit for a
VCO, since the phase noise drops as the square of the quality
factor. Low noise VCOs also require a large output amplitude in
order to achieve the best performance. As a consequence, it is
not expected that technoIo@caI improvements will improve
VCO phase noise at a given power dissipation for the
foreseeable future, since the inductor Q is relatively hard to
improve. The only other Congo1 variable is s i p 1 power, which
is directly related to IX:pwerdwipation.
The designed VCO. is shown @ figure 1. I t , is the
implementation of'the ~c-tankvco with the insertion of
source degeneration inductors (L, and L2)between each NMOS
switches M Iand M2 and the ground. These two degeneration
inductors significantly contribute in improving the phase noise
performance of the oscillator by. reducing the effect of low
frequency noise conversion into HF noise at the level of NMOS
switches. The VCO is tuned by the standard mode PMOS
varactors M3 and tv& combining low losses, low noise and high
tuning range. Due to their relatively good phase noise, ease of
implementation and differential op&abon, cross-coupled LC
vco play. an important role in hi& frequency circuit design.
The cross-coupled PMOS transistors M5and &I provide the
negative resistance to cancel the losses presented by the parallel
LC tank at resonance. This cross coupled PMOS transistors are
almost twice the width of their NMOS counterpart (MI, Mt)and
increase the loop gain. More importarit, the NMOS transistors
allow better symmetry to be achieved on each of the resonant
nodes. The VCO is biased by a resistor to avoid the phase noise
problem generated by the bias circuit. There is a compromise
between an'increase in the bias current causing an increase in
the power consumption, and an increase m the transistor width
leadmg to a demiase in the oscillation frequency and the gain at
high frequencies. The proposed VCO circuit uses a new
approach to design a linear, low noise and low power
differential VCO topology [lo]. As can be noticed, in such a
new arrangement,no dc current flows through the degeneration
transistor tv& and $e &amistorsM7,
h& are supposed to act as
the paths for the DC currents. The degenerationtransistor is still
isolated from the dc current pth. On the other hand, this
resistance can be increased such that to make the tramconductor
circuit more,linearand the dc biasing voltages of the transistors
Ms; & do not change. However, since no RC current flows
through h,
the tramondw~ceof M5,
& can be modified
by changing the drain current and &, independently. The
main advantage of such an arrangement -is that, due to the
configuration that M7, &are connected, &e variable c w n t
flowing through Mdtg is more than the input ac current. This fact
provides an &ded value to the d e g ~ a t i 0 ntransistor in the
oscillator circuit, and hence'malang the VCO more linear. The
transistors M7, & gate-source cbnnections receive ac voltages

opposite the ac voltages applied to.the bansistors Ms, gatesource connections respectively. Thus, when the gate voltage of
M5 increases, the gate voltage of M7 decreases. As a
consequence, when the' source of Ms wants to gwe more
current, the drain of M7wants to draw less current.
In addition, the dc current passes through M7,fi in place of
the two degeneration resistors in the classical differential
transconductor pair. Thus, from the DC point of view, the drainsource voltage.of M7, & replace the two degeneration resistors.
By taking into a5count the other parts composing the VCO
circuit, and based on the convenient sizes chosen for M7, h&,
the proposed oscillator topology will consume less power.
Hence, the presence of the transistors M7, & leads to a
reduction of current and hence lower power dissipation than the
conventional differential pair. The kmsistors M7 and M, serve
to regulate the current through the PMOS transistors M5,
thereby reducing power consumption. Regardless'of the value
of the degeneration trhsistor, the. VCO can consume much less
power than its classical count&
which uses the conventional
negative transconductor pair. The .main reason is that, in
classical arrangement, the.two degeneration resistors are'used to
linearize the VCO at the cost of an increasing in the p w e r
consumption ,In such a context, the value of ag,
and the
linearity obtained from it, does not affect the power
consumption of the designed oscillator. However, the power
consumption and the variation of the transconductance are
independent of each other, and thus these design parameters can
be analyzed separately. These are significant advantages of the
proposed voltage controlled oscillator obtained from the
isolation of the degeneration transistor from the DC current
path. &, Mlo, RI and Rz form buffers, which could be power
amplifiers, capable of driving 50n (spectrum analyzer), this will'
allow the VCO output signal to be measured at the drains of
transistors Mg and Mhowith an acceptable output voltage level.
In a standard process, metal layers can be used to construct
integrated spiral inductors. Several issues associated with an
integrated inductor need to be mentioned. First, there is series
resistance in the metal layers which reduces the quality factor of
the mductor. Second, there is capacitive coupling from the
metal to substrate which reduces the self-resonant frequency of
the inductor. Third, there is resistance in the conducting
substrate which also reduces the quality factor of the inductor,
None of these effects is negligible around an operation
frequency of 2 GHz. Much research effort has been devoted to
developing an accurate model for the spiral inductor.
Some software can' be used to optiinize the layout of the
inductor [13, 14, 151. One such effort by Niknejad and Meyer
has resulted in ASITIC, a tool that combines -a set of more
computationally-effcient techruques that has been developed
for solving electromagnetic fields around a metal windmg on a
multi-layered substrate, with a graphical interface for
conveniently generating 2-D spiral layouts of interest. These
progams take two effects into account. One, the eddy currents
induced by the changing magnetic field from the oscillating

3 88

m,

current in the inductor which flow in the opposite direction in

the substrate.
I

50x1 OpxO.35V

KHz and 3 MHz offsets respectively, Without the two

degeneration inductors. The oscillators tuning range is 15.8%
(1.69GHz-1.98GHz)
as depicted in figme 3, and havlng a gain
of 320 MHzN. This value corresponds to a control voltage
ranging from 0 to 1.W.
In thls design, ASITIC software has been used to optimize the
design of circular inductors in 0.35pmCMOS technology with
three Metal layers, by lowering their series resistances. A wide
Metal 3 turns have been used to achieve the quality factors
given in the table 1. The geometrical characteristics and
parameters of the designed circular inductors are listed in table
1.
The VCO, presented and analyzed in h s paper, addresses the
problem of fully tunable, low power consumption oscillator,
designed in standard 0.35pm CMOS TSMC process. As we
have seen, the standard mode PMOS varactors used in the
VCO, allow a hgh tuning range with the moderate contribution
of the transistors M,, A& and degeneration transistor
used
in the proposed VCO topology. For a maximal varactor quality
factor, a minimum channel length of 0.35pm should be
preferred to minimize the resistive paths in the channel. A high
Q varactor helps filter phase noise and a high linearity prevents
modulation of the varactor by the RF signal, which up-converts
bias noise. Each varactor is laid out with 200 fingers which are
IOpm wide and 0.35pm long.
In the VCO archtecture, multi-fingers MOS iransistors have
been considered in simulations and analysis, for a 1 gate
resistance and low noise devices (with aminimal channel length
of 0.35pm).

mq

3ox 1 ouxo 35u

0.7nH

&I

L1

Figure 1. The designed VCO topology.

This effect reduces the effective inductance and increase the

effective series resistance so that the quality factor is reduced.
The other is the skin effect which forces the current in the
inductor to flow on the outside of the spiral. Ths makes the
inner turns of the spiral less effective than the outer tuns and
the effective series resistance higher. The optimal layout of an
inductor depends on the inductance value, the particular
process, and the frequency of operation. At radio-frequency,
quality factors r a n p g from 3 to 20 have been reported in
recent publications [4, 15, 16, 171.
111. SIMULATION RESULTS AND DISCUSSiON

-50

-85
N

Predicted performance has been confmed by simulations using

Eldo-RF and IC-Layout tools from Mentor Graphics. All
simulations are based on 0.35pm CMOS TSMC technology
(three metal layers, two poly layers, twin tub, V e 0 . 4 6 V ,
VTp=4.61V, Lx=7 m).The VCO operates at 1.8 V power
supply voltage with a bias current of I. 55 mA by using a simple
resistor and giving a power dissipation of only 2.8 mW,
obtained by means of R new linear and low power differential
transconductor topology [IO] connected to act as a negative
resistor in the proposed VCO topology, thus consuming less
power than the classical LC VCO using the conventional
differentialtransconductor pair which consumes 5.5mW.
The phase noise of the proposed VCO achieved is -105, -123
and -138 dBc/Hz at IO0 KHz, 600 K f i and 3 M H z offsets
respectively from the carrier frequency of 1.8 GHz. The phase
noise performance of the VCO is shown in figure 2. This figure
shows clearly the effect of the inductive degeneration on the
phase noise performance of the oscillator where the phase noise
of the VCO is -102, -I20 and -135 dBc/Hz at 100 KHz, 600

389

sU

=z

-120

PI

UI

z
n

-155

-190
i , E + 0 3 1,E+04 l.E+OS i,E+061,E+07I . E + O B I . E + 0 9

Offset frequency, Hz
Figure 2. Sindated phase noise performance for VCO at 1.8 GHz carr~er
frequency

290 MHZ, obtained by using the standard- mode PMOS

varactors in the proposed VCO architecture. Such a designed

voltage controlled oscillator topolojy, stands as an interesting
arrangement to dissipate less power and to get more linear
oscillator than the standard LC VCO which uses the
conventjonal differential transconductor pair. The proposed
VCO could be a good and promising candidate for the
implementation of low power and low cost frequency
synthesizers used in DCS-1800, GSM and DECT mobile
communication systems.

U
E

REFERENCES
1.65

J. C ~ h c k xM.
, steyaett, A 1.8 GHz CMOS Low-Phase Noise Voltage
Controlled Oscillator With h c a l d , IEEE Journal of Solid-state
Circuits, vol. 30, No. 12, pp 1474-1482, December 1995.
[21 J. Craninckx, M. steyaerl, A 1.8 GHz CMOS Low-Phase Noise CMOS
VCO Using Optimized Hollow SpiraI Inductom:, EEE Journal of SolidStnte Circuits, vol. 32, No. 5, pp. 736-744, May 1997.
[3] F. Svelto, S. Deantani and R. Castello, A 1.3GHz Low-Phase Noise
Fully Tunable CMOS LC VCO, IEEE Journal of Solid-Statc Circuits,
Vol. 35, W.3, p ~356-361,
.
M m h 2000.
[4] E. Hegwi. H. Sjoland and A . A Abidi, A Filtering Technique to Lower
LC Oscillates Phase Noise, IEEE Joumal of Solid-state Citcuits, Vol.
36, N0.12,pp. 1921-1930, Deoemba2001.
[S] P. Andreani and H. Sjoland, Tail Current Noisc S u p p s i o n in RF
CMOS VCOs, IEEE Journal of Soiid-State C/rcuits, Vol. 37, NO.3, pp.
342-348, March 2002
[61 T.I. Ahrens, A. Hajimiri and T.H. Lee, A 1.6 GHz 0.5 mW CMOS LC
Low Phase Noise VCO. Using Bond wire Inductance, 1st International
Workshop on Design of Mixed-Mode Integrated Circuits and
Applications, Mexico,pp- 69-71, July 1997.
[7] L. Bouzerara, M.T. Belaroussi, A. Ziouohe, A 2 G k Low Power.
Highly Tunable and Low Phase Nolse Monolithic LC VCO in 0 . 3 5 ~
CMOS Technology, 16th International Conference on Microe~ectronics,
ICM04, Tunisia, pp. 21 1-214, December 2004.
[SI T.I. Ahrens snd T.H. Lee, A 1.4 GHz 3 mW CMOS LC Low Phase
Noise VCO Using Tapped Bond wire InductMces, International
Symposium on Low Power Electronics and Design, California, pp. 16-19,
August 1998.
191 H. Rem Sadr M. N,
A Novel Linear, Low Noise, Low Power
Differcntial Transomdudor and a Novel Linearization Technique, f 0th
IEEE hternational Conference on Electronics, Circuits and Systems
ICECS 2003, Vol. II, pp. 412-415, December 2003.
[IO] H. R e a Sadr M: N, A Novel Approach to the Linearization of the
Differential Transconducton , IEEE International Symposium on
Circuils and Systems, ISCAS 2004, pp. 1-1020- 1-1023, May 2004.
[ I l l T.H. Lee and A. Hajimiri, Y)scilla(or Phase Noise: A Tutorial, EEE
Journal of Solid-state Circuits, Vol. 35, NO.3, pp. 326-336, Mamh 2000.
[12] D.B. Lesson, A Simple Model of Feedback Oscillator Noise Spectrum.
Froceedmgs of the IEEE. vol. 54, pp. 329-330,1966,
[13] A. M. Niknejad, and R. G. Meyer, Analysis, Design and Optimization
of Spiral Inductors and Transformers for Si RF ICs, IEEE J. Solid-state
Cirouits, vol. 33, no. IO. pp- 1470-1481. Oct. 1998.
[I41 J. Crols, P. Kinget, J. Craninckx, and M.S . J. Steyaert, An Analyical
Model of Planar Inductors on Lowly Doped SiIicon Substrates for High
Frequency Analog Design up to 3GHz, Symposium On VLSI Circuits
Digest ofTechnical Paperp, pp. 28-29, June 1996.
[15] B. De Muer, C.De Ranter, J. Cmls and M. Steyacrt, A Simulator
Optimizer for the Design of very Low Phase Noise CMOS LCOscillators, IEEE Intematimal Cmfetenoe on Electronics, Circuits and
Systems ICECS99, Vol. 3, pp. 1557-1560, paphos, Cyprus
1161 B. De Muer, C.De Ranter and M. Steyaert, A Fully hiegrated 2 GHz
LC-VCO with Phase Noise of -125dBciHz at 600 K W , Roc. Of 1999
European Solid-State Circuits Cmfmnce, ESSCIRCW, pp. 206-209.
(I]

0,6

0.3

0,Q

1.2

15

1.8

Tuning Voltage, V
Figure 3. Simulated tuning range ofthe proposed VCO

TABLE L GEOMETRICAL
CHARACERISTICS AND
PPARAMETERS OFTHEDESIGNED CIRCULAR INWCTORS

Radius (pm)

200

I[

115

Figure 4. Layout of the proposed VCO

!v.

CONCLUSIONS AND PERSPECTIVES

A 1 8 GHz fully integrated voltage controlled oscillator has

been designed, analyzed and simulated using 0.35pm CMOS

technology. The use of the inductive degeneration allows a
considerable reduction of the tail current noise, which is the
main cause of phase noise in a CMOS differential VCO As a
result the VCO exhibits a good phase noise performance of 1 2 3 d B c f i at 600 KHz offset from the camer o f 1.8 GHz,
while the tunability is 15.8% of the central frequency or else

Germany.
[I71 J.N. Burghartz, M. Soyuer and K.A. Jenkins, Integrated RF and
Microwave Components in BiCMOS Technology, EFE Transactions
on Electron Devices, VoL 43, No9, pp. 1559-1570, September 1996.

390